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Poonam Aggrwal49249e12011-02-09 19:17:53 +00001/*
2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <common.h>
24#include <asm/processor.h>
25#include <asm/mmu.h>
26#include <asm/cache.h>
27#include <asm/immap_85xx.h>
28#include <asm/io.h>
29#include <miiphy.h>
30#include <libfdt.h>
31#include <fdt_support.h>
32#include <fsl_mdio.h>
33#include <tsec.h>
34#include <mmc.h>
35#include <netdev.h>
36#include <pci.h>
37#include <asm/fsl_serdes.h>
38#include <asm/fsl_ifc.h>
39#include <asm/fsl_pci.h>
40
41#ifndef CONFIG_SDCARD
42#include <hwconfig.h>
43#endif
44
45DECLARE_GLOBAL_DATA_PTR;
46
47#define GPIO4_PCIE_RESET_SET 0x08000000
48#define MUX_CPLD_CAN_UART 0x00
49#define MUX_CPLD_TDM 0x01
50#define MUX_CPLD_SPICS0_FLASH 0x00
51#define MUX_CPLD_SPICS0_SLIC 0x02
52
53#ifndef CONFIG_SDCARD
54struct cpld_data {
55 u8 cpld_ver; /* cpld revision */
56 u8 pcba_ver; /* pcb revision number */
57 u8 twindie_ddr3;
58 u8 res1[6];
59 u8 bank_sel; /* NOR Flash bank */
60 u8 res2[5];
61 u8 usb2_sel;
62 u8 res3[1];
63 u8 porsw_sel;
64 u8 tdm_can_sel;
65 u8 spi_cs0_sel; /* SPI CS0 SLIC/SPI Flash */
66 u8 por0; /* POR Options */
67 u8 por1; /* POR Options */
68 u8 por2; /* POR Options */
69 u8 por3; /* POR Options */
70};
71
72void cpld_show(void)
73{
74 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
75
76 printf("CPLD: V%x.%x PCBA: V%x.0\n",
77 in_8(&cpld_data->cpld_ver) & 0xF0,
78 in_8(&cpld_data->cpld_ver) & 0x0F,
79 in_8(&cpld_data->pcba_ver) & 0x0F);
80
81#ifdef CONFIG_DEBUG
82 printf("twindie_ddr =%x\n",
83 in_8(&cpld_data->twindie_ddr3));
84 printf("bank_sel =%x\n",
85 in_8(&cpld_data->bank_sel));
86 printf("usb2_sel =%x\n",
87 in_8(&cpld_data->usb2_sel));
88 printf("porsw_sel =%x\n",
89 in_8(&cpld_data->porsw_sel));
90 printf("tdm_can_sel =%x\n",
91 in_8(&cpld_data->tdm_can_sel));
92 printf("tdm_can_sel =%x\n",
93 in_8(&cpld_data->tdm_can_sel));
94 printf("spi_cs0_sel =%x\n",
95 in_8(&cpld_data->spi_cs0_sel));
96 printf("bcsr0 =%x\n",
97 in_8(&cpld_data->bcsr0));
98 printf("bcsr1 =%x\n",
99 in_8(&cpld_data->bcsr1));
100 printf("bcsr2 =%x\n",
101 in_8(&cpld_data->bcsr2));
102 printf("bcsr3 =%x\n",
103 in_8(&cpld_data->bcsr3));
104#endif
105}
106#endif
107
108int board_early_init_f(void)
109{
110 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
111#ifndef CONFIG_SDCARD
112 struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
113
114 /* Clock configuration to access CPLD using IFC(GPCM) */
115 setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
116#endif
117 /*
118 * Reset PCIe slots via GPIO4
119 */
120 setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET);
121 setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET);
122
123 return 0;
124}
125
126int board_early_init_r(void)
127{
128#ifndef CONFIG_SDCARD
129 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
130 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
131
132 /*
133 * Remap Boot flash region to caching-inhibited
134 * so that flash can be erased properly.
135 */
136
137 /* Flush d-cache and invalidate i-cache of any FLASH data */
138 flush_dcache();
139 invalidate_icache();
140
141 /* invalidate existing TLB entry for flash */
142 disable_tlb(flash_esel);
143
144 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
145 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
146 0, flash_esel, BOOKE_PAGESZ_16M, 1);
147
148 set_tlb(1, flashbase + 0x1000000,
149 CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
150 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
151 0, flash_esel+1, BOOKE_PAGESZ_16M, 1);
152#endif
153 return 0;
154}
155
156#ifdef CONFIG_PCI
157void pci_init_board(void)
158{
159 fsl_pcie_init_board(0);
160}
161#endif /* ifdef CONFIG_PCI */
162
163int checkboard(void)
164{
165 struct cpu_type *cpu;
166
Simon Glass67ac13b2012-12-13 20:48:48 +0000167 cpu = gd->arch.cpu;
Timur Tabi5d065c32012-03-15 11:42:27 +0000168 printf("Board: %sRDB\n", cpu->name);
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000169
170 return 0;
171}
172
173#ifdef CONFIG_TSEC_ENET
174int board_eth_init(bd_t *bis)
175{
176 struct fsl_pq_mdio_info mdio_info;
177 struct tsec_info_struct tsec_info[4];
178 struct cpu_type *cpu;
179 int num = 0;
180
Simon Glass67ac13b2012-12-13 20:48:48 +0000181 cpu = gd->arch.cpu;
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000182
183#ifdef CONFIG_TSEC1
184 SET_STD_TSEC_INFO(tsec_info[num], 1);
185 num++;
186#endif
187#ifdef CONFIG_TSEC2
188 SET_STD_TSEC_INFO(tsec_info[num], 2);
189 num++;
190#endif
191#ifdef CONFIG_TSEC3
192 /* P1014 and it's derivatives do not support eTSEC3 */
York Sun48f6a5c2012-07-06 17:10:33 -0500193 if (cpu->soc_ver != SVR_P1014) {
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000194 SET_STD_TSEC_INFO(tsec_info[num], 3);
195 num++;
196 }
197#endif
198 if (!num) {
199 printf("No TSECs initialized\n");
200 return 0;
201 }
202
203 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
204 mdio_info.name = DEFAULT_MII_NAME;
205
206 fsl_pq_mdio_init(bis, &mdio_info);
207
208 tsec_eth_init(bis, tsec_info, num);
209
210 return pci_eth_init(bis);
211}
212#endif
213
214#if defined(CONFIG_OF_BOARD_SETUP)
215void fdt_del_flexcan(void *blob)
216{
217 int nodeoff = 0;
218
219 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
Shengzhou Liuf68a7302013-03-25 07:30:09 +0000220 "fsl,p1010-flexcan")) >= 0) {
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000221 fdt_del_node(blob, nodeoff);
222 }
223}
224
225void fdt_del_spi_flash(void *blob)
226{
227 int nodeoff = 0;
228
229 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
230 "spansion,s25sl12801")) >= 0) {
231 fdt_del_node(blob, nodeoff);
232 }
233}
234
235void fdt_del_spi_slic(void *blob)
236{
237 int nodeoff = 0;
238
239 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
240 "zarlink,le88266")) >= 0) {
241 fdt_del_node(blob, nodeoff);
242 }
243}
244
245void fdt_del_tdm(void *blob)
246{
247 int nodeoff = 0;
248
249 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
250 "fsl,starlite-tdm")) >= 0) {
251 fdt_del_node(blob, nodeoff);
252 }
253}
254
Shengzhou Liu487e8ab2012-04-25 23:43:24 +0000255void fdt_del_sdhc(void *blob)
256{
257 int nodeoff = 0;
258
259 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
260 "fsl,esdhc")) >= 0) {
261 fdt_del_node(blob, nodeoff);
262 }
263}
264
265void fdt_disable_uart1(void *blob)
266{
267 int nodeoff;
268
269 nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550",
270 CONFIG_SYS_NS16550_COM2);
271
272 if (nodeoff > 0) {
273 fdt_status_disabled(blob, nodeoff);
274 } else {
275 printf("WARNING unable to set status for fsl,ns16550 "
276 "uart1: %s\n", fdt_strerror(nodeoff));
277 }
278}
279
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000280void ft_board_setup(void *blob, bd_t *bd)
281{
282 phys_addr_t base;
283 phys_size_t size;
284 struct cpu_type *cpu;
285
Simon Glass67ac13b2012-12-13 20:48:48 +0000286 cpu = gd->arch.cpu;
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000287
288 ft_cpu_setup(blob, bd);
289
290 base = getenv_bootm_low();
291 size = getenv_bootm_size();
292
293#if defined(CONFIG_PCI)
294 FT_FSL_PCI_SETUP;
295#endif
296
297 fdt_fixup_memory(blob, (u64)base, (u64)size);
298
Ramneek Mehresha311db62011-11-08 10:21:28 +0530299#if defined(CONFIG_HAS_FSL_DR_USB)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000300 fdt_fixup_dr_usb(blob, bd);
Ramneek Mehresha311db62011-11-08 10:21:28 +0530301#endif
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000302
303 /* P1014 and it's derivatives don't support CAN and eTSEC3 */
York Sun48f6a5c2012-07-06 17:10:33 -0500304 if (cpu->soc_ver == SVR_P1014) {
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000305 fdt_del_flexcan(blob);
306 fdt_del_node_and_alias(blob, "ethernet2");
307 }
308#ifndef CONFIG_SDCARD
Shengzhou Liu487e8ab2012-04-25 23:43:24 +0000309 /* disable sdhc due to sdhc bug */
310 fdt_del_sdhc(blob);
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000311 if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000312 fdt_del_tdm(blob);
313 fdt_del_spi_slic(blob);
Shengzhou Liu487e8ab2012-04-25 23:43:24 +0000314 } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000315 fdt_del_flexcan(blob);
316 fdt_del_spi_flash(blob);
Shengzhou Liu487e8ab2012-04-25 23:43:24 +0000317 fdt_disable_uart1(blob);
318 } else {
319 /*
320 * If we don't set fsl_p1010mux:tdm_can to "can" or "tdm"
321 * explicitly, defaultly spi_cs_sel to spi-flash instead of
322 * to tdm/slic.
323 */
324 fdt_del_tdm(blob);
325 fdt_del_flexcan(blob);
326 fdt_disable_uart1(blob);
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000327 }
328#endif
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000329}
330#endif
331
332#ifndef CONFIG_SDCARD
333int misc_init_r(void)
334{
335 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
336 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
337
338 if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
339 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM |
340 MPC85xx_PMUXCR_CAN1_UART |
341 MPC85xx_PMUXCR_CAN2_TDM |
342 MPC85xx_PMUXCR_CAN2_UART);
343 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
Shengzhou Liu487e8ab2012-04-25 23:43:24 +0000344 } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000345 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART |
346 MPC85xx_PMUXCR_CAN1_UART);
347 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM |
348 MPC85xx_PMUXCR_CAN1_TDM);
349 clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO);
350 setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM);
351 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
352 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
Shengzhou Liu487e8ab2012-04-25 23:43:24 +0000353 } else {
354 /* defaultly spi_cs_sel to flash */
355 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
356 }
357
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000358 return 0;
359}
360#endif