blob: 52fe8cad0c2be709a9f1b7e6c49eb6839d09bbde [file] [log] [blame]
Lunsheng Wangb0e32942005-07-29 10:20:29 -05001/*
2 * (C) Copyright 2002,2003, Motorola Inc.
3 * Xianghua Xiao, (X.Xiao@motorola.com)
4 *
5 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
Lunsheng Wangb0e32942005-07-29 10:20:29 -050026#include <common.h>
27#include <asm/processor.h>
28#include <asm/immap_85xx.h>
29#include <spd.h>
30
Jon Loeligerde1d0a62005-08-01 13:20:47 -050031extern long int spd_sdram (void);
Lunsheng Wangb0e32942005-07-29 10:20:29 -050032
33long int fixed_sdram (void);
34
Lunsheng Wangb0e32942005-07-29 10:20:29 -050035int board_pre_init (void)
36{
37#if defined(CONFIG_PCI)
38 volatile immap_t *immr = (immap_t *)CFG_IMMR;
39 volatile ccsr_pcix_t *pci = &immr->im_pcix;
40
41 pci->peer &= 0xffffffdf; /* disable master abort */
42#endif
43 return 0;
44}
45
46int checkboard (void)
47{
48 sys_info_t sysinfo;
49
50 get_sys_info (&sysinfo);
51
52 printf ("Board: Freescale MPC8540EVAL Board\n");
53 printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
54 printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
55 printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
56 if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
57 || (CFG_LBC_LCRR & 0x0f) == 8) {
Jon Loeligerde1d0a62005-08-01 13:20:47 -050058 printf ("\tLBC: %lu MHz\n",
59 sysinfo.freqSystemBus / 1000000/(CFG_LBC_LCRR & 0x0f));
Lunsheng Wangb0e32942005-07-29 10:20:29 -050060 } else {
61 printf("\tLBC: unknown\n");
62 }
63 printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
64 return (0);
65}
66
67long int initdram (int board_type)
68{
69 long dram_size = 0;
70 extern long spd_sdram (void);
71 volatile immap_t *immap = (immap_t *)CFG_IMMR;
72#if !defined(CONFIG_RAM_AS_FLASH)
73 volatile ccsr_lbc_t *lbc= &immap->im_lbc;
74 sys_info_t sysinfo;
75 uint temp_lbcdll = 0;
76#endif
77#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
Kumar Galaf59b55a2007-11-27 23:25:02 -060078 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
Lunsheng Wangb0e32942005-07-29 10:20:29 -050079#endif
80
81#if defined(CONFIG_DDR_DLL)
82 uint temp_ddrdll = 0;
83
84 /* Work around to stabilize DDR DLL */
85 temp_ddrdll = gur->ddrdllcr;
86 gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
87 asm("sync;isync;msync");
88#endif
89
90#if defined(CONFIG_SPD_EEPROM)
91 dram_size = spd_sdram ();
92#else
93 dram_size = fixed_sdram ();
94#endif
95
96#if defined(CFG_RAMBOOT)
97 return dram_size;
98#endif
99
100#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
101 get_sys_info(&sysinfo);
102 /* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
103 if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
104 lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
105 } else {
106 lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
107 udelay(200);
108 temp_lbcdll = gur->lbcdllcr;
109 gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
110 asm("sync;isync;msync");
111 }
112 lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
113 lbc->br2 = CFG_BR2_PRELIM;
114 lbc->lbcr = CFG_LBC_LBCR;
115 lbc->lsdmr = CFG_LBC_LSDMR_1;
116 asm("sync");
117 * (ulong *)0 = 0x000000ff;
118 lbc->lsdmr = CFG_LBC_LSDMR_2;
119 asm("sync");
120 * (ulong *)0 = 0x000000ff;
121 lbc->lsdmr = CFG_LBC_LSDMR_3;
122 asm("sync");
123 * (ulong *)0 = 0x000000ff;
124 lbc->lsdmr = CFG_LBC_LSDMR_4;
125 asm("sync");
126 * (ulong *)0 = 0x000000ff;
127 lbc->lsdmr = CFG_LBC_LSDMR_5;
128 asm("sync");
129 lbc->lsrt = CFG_LBC_LSRT;
130 asm("sync");
131 lbc->mrtpr = CFG_LBC_MRTPR;
132 asm("sync");
133#endif
134
135#if defined(CONFIG_DDR_ECC)
136 {
137 /* Initialize all of memory for ECC, then
138 * enable errors */
139 uint *p = 0;
140 uint i = 0;
141 volatile immap_t *immap = (immap_t *)CFG_IMMR;
142 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
143 dma_init();
144 for (*p = 0; p < (uint *)(8 * 1024); p++) {
145 if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
146 *p = (unsigned int)0xdeadbeef;
147 if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
148 }
149
150 /* 8K */
151 dma_xfer((uint *)0x2000,0x2000,(uint *)0);
152 /* 16K */
153 dma_xfer((uint *)0x4000,0x4000,(uint *)0);
154 /* 32K */
155 dma_xfer((uint *)0x8000,0x8000,(uint *)0);
156 /* 64K */
157 dma_xfer((uint *)0x10000,0x10000,(uint *)0);
158 /* 128k */
159 dma_xfer((uint *)0x20000,0x20000,(uint *)0);
160 /* 256k */
161 dma_xfer((uint *)0x40000,0x40000,(uint *)0);
162 /* 512k */
163 dma_xfer((uint *)0x80000,0x80000,(uint *)0);
164 /* 1M */
165 dma_xfer((uint *)0x100000,0x100000,(uint *)0);
166 /* 2M */
167 dma_xfer((uint *)0x200000,0x200000,(uint *)0);
168 /* 4M */
169 dma_xfer((uint *)0x400000,0x400000,(uint *)0);
170
171 for (i = 1; i < dram_size / 0x800000; i++) {
172 dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
173 }
174
175 /* Enable errors for ECC */
176 ddr->err_disable = 0x00000000;
177 asm("sync;isync;msync");
178 }
179#endif
180
181 return dram_size;
182}
183
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500184#if defined(CFG_DRAM_TEST)
185int testdram (void)
186{
187 uint *pstart = (uint *) CFG_MEMTEST_START;
188 uint *pend = (uint *) CFG_MEMTEST_END;
189 uint *p;
190
191 printf("SDRAM test phase 1:\n");
192 for (p = pstart; p < pend; p++)
193 *p = 0xaaaaaaaa;
194
195 for (p = pstart; p < pend; p++) {
196 if (*p != 0xaaaaaaaa) {
197 printf ("SDRAM test fails at: %08x\n", (uint) p);
198 return 1;
199 }
200 }
201
202 printf("SDRAM test phase 2:\n");
203 for (p = pstart; p < pend; p++)
204 *p = 0x55555555;
205
206 for (p = pstart; p < pend; p++) {
207 if (*p != 0x55555555) {
208 printf ("SDRAM test fails at: %08x\n", (uint) p);
209 return 1;
210 }
211 }
212
213 printf("SDRAM test passed.\n");
214 return 0;
215}
216#endif
217
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500218#if !defined(CONFIG_SPD_EEPROM)
219/*************************************************************************
220 * fixed sdram init -- doesn't use serial presence detect.
221 ************************************************************************/
222long int fixed_sdram (void)
223{
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500224#ifndef CFG_RAMBOOT
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500225 volatile immap_t *immap = (immap_t *)CFG_IMMR;
226 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
227
228 ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
229 ddr->cs0_config = CFG_DDR_CS0_CONFIG;
230 ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
231 ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
232 ddr->sdram_mode = CFG_DDR_MODE;
233 ddr->sdram_interval = CFG_DDR_INTERVAL;
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500234#if defined (CONFIG_DDR_ECC)
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500235 ddr->err_disable = 0x0000000D;
236 ddr->err_sbe = 0x00ff0000;
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500237#endif
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500238 asm("sync;isync;msync");
239 udelay(500);
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500240#if defined (CONFIG_DDR_ECC)
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500241 /* Enable ECC checking */
242 ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500243#else
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500244 ddr->sdram_cfg = CFG_DDR_CONTROL;
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500245#endif
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500246 asm("sync; isync; msync");
247 udelay(500);
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500248#endif
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500249 return (CFG_SDRAM_SIZE * 1024 * 1024);
250}
251#endif /* !defined(CONFIG_SPD_EEPROM) */