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Yoshihiro Shimoda1a2621b2012-11-04 15:53:22 +00001/*
2 * Configuation settings for the sh7752evb board
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Yoshihiro Shimoda1a2621b2012-11-04 15:53:22 +00007 */
8
9#ifndef __SH7752EVB_H
10#define __SH7752EVB_H
11
12#undef DEBUG
Yoshihiro Shimoda1a2621b2012-11-04 15:53:22 +000013#define CONFIG_CPU_SH7752 1
14#define CONFIG_SH7752EVB 1
15
16#define CONFIG_SYS_TEXT_BASE 0x5ff80000
17#define CONFIG_SYS_LDSCRIPT "board/renesas/sh7752evb/u-boot.lds"
18
Yoshihiro Shimoda1a2621b2012-11-04 15:53:22 +000019#define CONFIG_CMD_DFL
20#define CONFIG_CMD_SDRAM
Yoshihiro Shimoda1a2621b2012-11-04 15:53:22 +000021#define CONFIG_CMD_MD5SUM
22#define CONFIG_MD5
Yoshihiro Shimoda1a2621b2012-11-04 15:53:22 +000023#define CONFIG_DOS_PARTITION
24#define CONFIG_MAC_PARTITION
25
26#define CONFIG_BAUDRATE 115200
Yoshihiro Shimoda1a2621b2012-11-04 15:53:22 +000027#define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp"
28
Yoshihiro Shimoda1a2621b2012-11-04 15:53:22 +000029#undef CONFIG_SHOW_BOOT_PROGRESS
30#define CONFIG_CMDLINE_EDITING
31#define CONFIG_AUTO_COMPLETE
32
33/* MEMORY */
34#define SH7752EVB_SDRAM_BASE (0x40000000)
35#define SH7752EVB_SDRAM_SIZE (512 * 1024 * 1024)
36
37#define CONFIG_SYS_LONGHELP
Yoshihiro Shimoda1a2621b2012-11-04 15:53:22 +000038#define CONFIG_SYS_CBSIZE 256
39#define CONFIG_SYS_PBSIZE 256
40#define CONFIG_SYS_MAXARGS 16
41#define CONFIG_SYS_BARGSIZE 512
42#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
43
44/* SCIF */
45#define CONFIG_SCIF_CONSOLE 1
46#define CONFIG_CONS_SCIF2 1
47#undef CONFIG_SYS_CONSOLE_INFO_QUIET
48#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
49#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
50
51#define CONFIG_SYS_MEMTEST_START (SH7752EVB_SDRAM_BASE)
52#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
53 480 * 1024 * 1024)
54#undef CONFIG_SYS_ALT_MEMTEST
55#undef CONFIG_SYS_MEMTEST_SCRATCH
56#undef CONFIG_SYS_LOADS_BAUD_CHANGE
57
58#define CONFIG_SYS_SDRAM_BASE (SH7752EVB_SDRAM_BASE)
59#define CONFIG_SYS_SDRAM_SIZE (SH7752EVB_SDRAM_SIZE)
60#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
61 128 * 1024 * 1024)
62
63#define CONFIG_SYS_MONITOR_BASE 0x00000000
64#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
65#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
66#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
67
68/* FLASH */
69#define CONFIG_SYS_NO_FLASH
70
71/* Ether */
72#define CONFIG_SH_ETHER 1
73#define CONFIG_SH_ETHER_USE_PORT 0
74#define CONFIG_SH_ETHER_PHY_ADDR 18
75#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
76#define CONFIG_SH_ETHER_USE_GETHER 1
77#define CONFIG_PHYLIB
78#define CONFIG_BITBANGMII
79#define CONFIG_BITBANGMII_MULTI
80#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
81#define CONFIG_PHY_VITESSE
82
83#define SH7752EVB_ETHERNET_MAC_BASE_SPI 0x00090000
84#define SH7752EVB_SPI_SECTOR_SIZE (64 * 1024)
85#define SH7752EVB_ETHERNET_MAC_BASE SH7752EVB_ETHERNET_MAC_BASE_SPI
86#define SH7752EVB_ETHERNET_MAC_SIZE 17
87#define SH7752EVB_ETHERNET_NUM_CH 2
88#define CONFIG_BOARD_LATE_INIT
89
90/* SPI */
91#define CONFIG_SH_SPI 1
92#define CONFIG_SH_SPI_BASE 0xfe002000
Yoshihiro Shimoda1a2621b2012-11-04 15:53:22 +000093
94/* MMCIF */
95#define CONFIG_MMC 1
96#define CONFIG_GENERIC_MMC 1
97#define CONFIG_SH_MMCIF 1
98#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
99#define CONFIG_SH_MMCIF_CLK 48000000
100
101/* ENV setting */
102#define CONFIG_ENV_IS_EMBEDDED
103#define CONFIG_ENV_IS_IN_SPI_FLASH
104#define CONFIG_ENV_SECT_SIZE (64 * 1024)
105#define CONFIG_ENV_ADDR (0x00080000)
106#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
107#define CONFIG_ENV_OVERWRITE 1
108#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
109#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
110#define CONFIG_EXTRA_ENV_SETTINGS \
111 "netboot=bootp; bootm\0"
112
113/* Board Clock */
114#define CONFIG_SYS_CLK_FREQ 48000000
Nobuhiro Iwamatsu684a5012013-08-21 16:11:21 +0900115#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
116#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Yoshihiro Shimoda1a2621b2012-11-04 15:53:22 +0000117#define CONFIG_SYS_TMU_CLK_DIV 4
Yoshihiro Shimoda1a2621b2012-11-04 15:53:22 +0000118#endif /* __SH7752EVB_H */