blob: a2a26f927ecba050445cdb6d91292ccc8f761a43 [file] [log] [blame]
Holger Brunck0f2b7212012-03-21 13:42:46 +01001/*
2 * (C) Copyright 2012
3 * Holger Brunck, Keymile GmbH Hannover, <holger.brunck@keymile.com>
4 * Christian Herzig, Keymile AG Switzerland, <christian.herzig@keymile.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Holger Brunck0f2b7212012-03-21 13:42:46 +01007 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12/* KMBEC FPGA (PRIO) */
13#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
14#define CONFIG_SYS_KMBEC_FPGA_SIZE 64
15
16#if defined CONFIG_KMETER1
17#define CONFIG_HOSTNAME kmeter1
18#define CONFIG_KM_BOARD_NAME "kmeter1"
19#define CONFIG_KM_DEF_NETDEV "netdev=eth2\0"
20#elif defined CONFIG_KMCOGE5NE
21#define CONFIG_HOSTNAME kmcoge5ne
22#define CONFIG_KM_BOARD_NAME "kmcoge5ne"
23#define CONFIG_KM_DEF_NETDEV "netdev=eth1\0"
Holger Brunckbe7576f2013-01-21 03:55:23 +000024#define CONFIG_NAND_ECC_BCH
Holger Brunck0f2b7212012-03-21 13:42:46 +010025#define CONFIG_NAND_KMETER1
26#define CONFIG_SYS_MAX_NAND_DEVICE 1
27#define NAND_MAX_CHIPS 1
28#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
29
30#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
31#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
Holger Brunck0f2b7212012-03-21 13:42:46 +010032#else
33#error ("Board not supported")
34#endif
35
36/*
37 * High Level Configuration Options
38 */
39#define CONFIG_QE /* Has QE */
40#define CONFIG_MPC8360 /* MPC8360 CPU specific */
41
42#define CONFIG_SYS_TEXT_BASE 0xF0000000
43
44/* include common defines/options for all 83xx Keymile boards */
45#include "km/km83xx-common.h"
46
47/*
48 * System IO Setup
49 */
50#define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI)
51
52/*
53 * Hardware Reset Configuration Word
54 */
55#define CONFIG_SYS_HRCW_LOW (\
56 HRCWL_CSB_TO_CLKIN_4X1 | \
57 HRCWL_CORE_TO_CSB_2X1 | \
58 HRCWL_CE_PLL_VCO_DIV_2 | \
59 HRCWL_CE_TO_PLL_1X6)
60
61#define CONFIG_SYS_HRCW_HIGH (\
62 HRCWH_CORE_ENABLE | \
63 HRCWH_FROM_0X00000100 | \
64 HRCWH_BOOTSEQ_DISABLE | \
65 HRCWH_SW_WATCHDOG_DISABLE | \
66 HRCWH_ROM_LOC_LOCAL_16BIT | \
67 HRCWH_BIG_ENDIAN | \
68 HRCWH_LALE_EARLY | \
69 HRCWH_LDP_CLEAR)
70
71/**
72 * DDR RAM settings
73 */
74#define CONFIG_SYS_DDR_SDRAM_CFG (\
75 SDRAM_CFG_SDRAM_TYPE_DDR2 | \
76 SDRAM_CFG_SREN | \
77 SDRAM_CFG_HSE)
78
79#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
80
81#ifdef CONFIG_KMCOGE5NE
82/**
83 * KMCOGE5NE has 512 MB RAM
84 */
85#define CONFIG_SYS_DDR_CS0_CONFIG (\
86 CSCONFIG_EN | \
87 CSCONFIG_AP | \
Valentin Longchamp22554ba2015-11-17 10:53:33 +010088 CSCONFIG_ODT_WR_ONLY_CURRENT | \
Holger Brunck0f2b7212012-03-21 13:42:46 +010089 CSCONFIG_BANK_BIT_3 | \
90 CSCONFIG_ROW_BIT_13 | \
91 CSCONFIG_COL_BIT_10)
92#else
93#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
94 CSCONFIG_ROW_BIT_13 | \
95 CSCONFIG_COL_BIT_10 | \
Valentin Longchamp22554ba2015-11-17 10:53:33 +010096 CSCONFIG_ODT_WR_ONLY_CURRENT)
Holger Brunck0f2b7212012-03-21 13:42:46 +010097#endif
98
99#define CONFIG_SYS_DDR_CLK_CNTL (\
100 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
101
102#define CONFIG_SYS_DDR_INTERVAL (\
103 (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
104 (0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
105
106#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
107
108#define CONFIG_SYS_DDRCDR (\
109 DDRCDR_EN | \
110 DDRCDR_Q_DRN)
111#define CONFIG_SYS_DDR_MODE 0x47860452
112#define CONFIG_SYS_DDR_MODE2 0x8080c000
113
114#define CONFIG_SYS_DDR_TIMING_0 (\
115 (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
116 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
117 (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
118 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
119 (0 << TIMING_CFG0_WWT_SHIFT) | \
120 (0 << TIMING_CFG0_RRT_SHIFT) | \
121 (0 << TIMING_CFG0_WRT_SHIFT) | \
122 (0 << TIMING_CFG0_RWT_SHIFT))
123
124#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
125 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
126 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
127 (3 << TIMING_CFG1_WRREC_SHIFT) | \
128 (7 << TIMING_CFG1_REFREC_SHIFT) | \
129 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
130 (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
131 (3 << TIMING_CFG1_PRETOACT_SHIFT))
132
133#define CONFIG_SYS_DDR_TIMING_2 (\
134 (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
135 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
136 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
137 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
138 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
139 (5 << TIMING_CFG2_CPO_SHIFT) | \
140 (0 << TIMING_CFG2_ADD_LAT_SHIFT))
141
142#define CONFIG_SYS_DDR_TIMING_3 0x00000000
143
144/* EEprom support */
145#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
146
147/*
148 * Local Bus Configuration & Clock Setup
149 */
150#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
151#define CONFIG_SYS_LCRR_EADC LCRR_EADC_2
152#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
153
154/*
155 * PAXE on the local bus CS3
156 */
157#define CONFIG_SYS_PAXE_BASE 0xA0000000
158#define CONFIG_SYS_PAXE_SIZE 256
159
160#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE
161
162#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */
163
164#define CONFIG_SYS_BR3_PRELIM (\
165 CONFIG_SYS_PAXE_BASE | \
166 (1 << BR_PS_SHIFT) | \
167 BR_V)
168
169#define CONFIG_SYS_OR3_PRELIM (\
170 MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
171 OR_GPCM_CSNT | \
172 OR_GPCM_ACS_DIV2 | \
173 OR_GPCM_SCY_2 | \
174 OR_GPCM_TRLX | \
175 OR_GPCM_EAD)
176
177#ifdef CONFIG_KMCOGE5NE
178/*
179 * BFTIC3 on the local bus CS4
180 */
181#define CONFIG_SYS_BFTIC3_BASE 0xB0000000
182#define CONFIG_SYS_BFTIC3_SIZE 256
183
184#define CONFIG_SYS_BR4_PRELIM (\
185 CONFIG_SYS_BFTIC3_BASE |\
186 (1 << BR_PS_SHIFT) | \
187 BR_V)
188
189#define CONFIG_SYS_OR4_PRELIM (\
190 MEG_TO_AM(CONFIG_SYS_BFTIC3_SIZE) |\
191 OR_GPCM_CSNT | \
192 OR_GPCM_ACS_DIV2 |\
193 OR_GPCM_SCY_2 |\
194 OR_GPCM_TRLX |\
195 OR_GPCM_EAD)
196#endif
197
198/*
199 * MMU Setup
200 */
201
202/* PAXE: icache cacheable, but dcache-inhibit and guarded */
203#define CONFIG_SYS_IBAT5L (\
204 CONFIG_SYS_PAXE_BASE | \
205 BATL_PP_10 | \
206 BATL_MEMCOHERENCE)
207
208#define CONFIG_SYS_IBAT5U (\
209 CONFIG_SYS_PAXE_BASE | \
210 BATU_BL_256M | \
211 BATU_VS | \
212 BATU_VP)
213
214#define CONFIG_SYS_DBAT5L (\
215 CONFIG_SYS_PAXE_BASE | \
216 BATL_PP_10 | \
217 BATL_CACHEINHIBIT | \
218 BATL_GUARDEDSTORAGE)
219
220#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
221
Holger Brunck0f2b7212012-03-21 13:42:46 +0100222#ifdef CONFIG_KMCOGE5NE
223/* BFTIC3: icache cacheable, but dcache-inhibit and guarded */
224#define CONFIG_SYS_IBAT6L (\
225 CONFIG_SYS_BFTIC3_BASE | \
226 BATL_PP_10 | \
227 BATL_MEMCOHERENCE)
228
229#define CONFIG_SYS_IBAT6U (\
230 CONFIG_SYS_BFTIC3_BASE | \
231 BATU_BL_256M | \
232 BATU_VS | \
233 BATU_VP)
234
235#define CONFIG_SYS_DBAT6L (\
236 CONFIG_SYS_BFTIC3_BASE | \
237 BATL_PP_10 | \
238 BATL_CACHEINHIBIT | \
239 BATL_GUARDEDSTORAGE)
240
241#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
242
243/* DDR/LBC SDRAM next 256M: cacheable */
244#define CONFIG_SYS_IBAT7L (\
245 CONFIG_SYS_SDRAM_BASE2 |\
246 BATL_PP_10 |\
247 BATL_CACHEINHIBIT |\
248 BATL_GUARDEDSTORAGE)
249
250#define CONFIG_SYS_IBAT7U (\
251 CONFIG_SYS_SDRAM_BASE2 |\
252 BATU_BL_256M |\
253 BATU_VS |\
254 BATU_VP)
Thomas Herzmann95209b62012-05-04 10:55:56 +0200255/* enable POST tests */
256#define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS)
257#define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */
258#define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END
259#define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */
260#define CONFIG_TESTPIN_MASK 0x20 /* for kmcoge5ne */
Thomas Herzmann95209b62012-05-04 10:55:56 +0200261
Holger Brunck0f2b7212012-03-21 13:42:46 +0100262#else
263#define CONFIG_SYS_IBAT6L (0)
264#define CONFIG_SYS_IBAT6U (0)
265#define CONFIG_SYS_IBAT7L (0)
266#define CONFIG_SYS_IBAT7U (0)
267#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
268#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
269#endif
270
271#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
272#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
273
274#endif /* CONFIG */