blob: 59a3b06b71cdc300f171c48802ac0cd66af2b690 [file] [log] [blame]
wdenk935ecca2002-08-06 20:46:37 +00001/*----------------------------------------------------------------------------+
2|
3| This source code has been made available to you by IBM on an AS-IS
4| basis. Anyone receiving this source is licensed under IBM
5| copyrights to use it in any way he or she deems fit, including
6| copying it, modifying it, compiling it, and redistributing it either
7| with or without modifications. No license under IBM patents or
8| patent applications is to be implied by the copyright license.
9|
10| Any user of this software should understand that IBM cannot provide
11| technical support for this software and will not be responsible for
12| any consequences resulting from the use of this software.
13|
14| Any person who transfers this source code or any derivative work
15| must include the IBM copyright notice, this paragraph, and the
16| preceding two paragraphs in the transferred software.
17|
18| COPYRIGHT I B M CORPORATION 1999
19| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20+----------------------------------------------------------------------------*/
21
22#ifndef __PPC4XX_H__
23#define __PPC4XX_H__
24
Stefan Roese36ea16f2008-06-02 14:57:41 +020025/*
26 * Configure which SDRAM/DDR/DDR2 controller is equipped
27 */
28#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) || \
29 defined(CONFIG_AP1000) || defined(CONFIG_ML2)
30#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */
31#endif
32
33#if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
34 defined(CONFIG_440EP) || defined(CONFIG_440GR)
35#define CONFIG_SDRAM_PPC4xx_IBM_DDR /* IBM DDR controller */
36#endif
37
38#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
39#define CONFIG_SDRAM_PPC4xx_DENALI_DDR2 /* Denali DDR(2) controller */
40#endif
41
42#if defined(CONFIG_405EX) || \
43 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
Feng Kan96e5fc02008-07-08 22:48:07 -070044 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
45 defined(CONFIG_460SX)
Stefan Roese36ea16f2008-06-02 14:57:41 +020046#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */
47#endif
48
Prodyut Hazarika079589b2008-08-20 09:38:51 -070049/* PLB4 CrossBar Arbiter Core supported across PPC4xx families */
50#if defined(CONFIG_405EX) || \
51 defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
52 defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
53 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
54 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
55 defined(CONFIG_460SX)
56
57#define PLB_ARBITER_BASE 0x80
58
Stefan Roesef5564832008-08-21 11:05:03 +020059#define plb0_revid (PLB_ARBITER_BASE + 0x00)
60#define plb0_acr (PLB_ARBITER_BASE + 0x01)
Prodyut Hazarika079589b2008-08-20 09:38:51 -070061#define plb0_acr_ppm_mask 0xF0000000
62#define plb0_acr_ppm_fixed 0x00000000
63#define plb0_acr_ppm_fair 0xD0000000
64#define plb0_acr_hbu_mask 0x08000000
65#define plb0_acr_hbu_disabled 0x00000000
66#define plb0_acr_hbu_enabled 0x08000000
67#define plb0_acr_rdp_mask 0x06000000
68#define plb0_acr_rdp_disabled 0x00000000
69#define plb0_acr_rdp_2deep 0x02000000
70#define plb0_acr_rdp_3deep 0x04000000
71#define plb0_acr_rdp_4deep 0x06000000
72#define plb0_acr_wrp_mask 0x01000000
73#define plb0_acr_wrp_disabled 0x00000000
74#define plb0_acr_wrp_2deep 0x01000000
75
Stefan Roesef5564832008-08-21 11:05:03 +020076#define plb0_besrl (PLB_ARBITER_BASE + 0x02)
77#define plb0_besrh (PLB_ARBITER_BASE + 0x03)
78#define plb0_bearl (PLB_ARBITER_BASE + 0x04)
79#define plb0_bearh (PLB_ARBITER_BASE + 0x05)
80#define plb0_ccr (PLB_ARBITER_BASE + 0x08)
Prodyut Hazarika079589b2008-08-20 09:38:51 -070081
Stefan Roesef5564832008-08-21 11:05:03 +020082#define plb1_acr (PLB_ARBITER_BASE + 0x09)
Prodyut Hazarika079589b2008-08-20 09:38:51 -070083#define plb1_acr_ppm_mask 0xF0000000
84#define plb1_acr_ppm_fixed 0x00000000
85#define plb1_acr_ppm_fair 0xD0000000
86#define plb1_acr_hbu_mask 0x08000000
87#define plb1_acr_hbu_disabled 0x00000000
88#define plb1_acr_hbu_enabled 0x08000000
89#define plb1_acr_rdp_mask 0x06000000
90#define plb1_acr_rdp_disabled 0x00000000
91#define plb1_acr_rdp_2deep 0x02000000
92#define plb1_acr_rdp_3deep 0x04000000
93#define plb1_acr_rdp_4deep 0x06000000
94#define plb1_acr_wrp_mask 0x01000000
95#define plb1_acr_wrp_disabled 0x00000000
96#define plb1_acr_wrp_2deep 0x01000000
97
Stefan Roesef5564832008-08-21 11:05:03 +020098#define plb1_besrl (PLB_ARBITER_BASE + 0x0A)
99#define plb1_besrh (PLB_ARBITER_BASE + 0x0B)
100#define plb1_bearl (PLB_ARBITER_BASE + 0x0C)
101#define plb1_bearh (PLB_ARBITER_BASE + 0x0D)
Prodyut Hazarika079589b2008-08-20 09:38:51 -0700102
103#endif /* 440EP/EPX 440GR/GRX 440SP/SPE 460EX/GT/SX 405EX*/
104
wdenk935ecca2002-08-06 20:46:37 +0000105#if defined(CONFIG_440)
Stefan Roesef2302d42008-08-06 14:05:38 +0200106/*
107 * Enable long long (%ll ...) printf format on 440 PPC's since most of
108 * them support 36bit physical addressing
109 */
110#define CFG_64BIT_VSPRINTF
111#define CFG_64BIT_STRTOUL
wdenk935ecca2002-08-06 20:46:37 +0000112#include <ppc440.h>
113#else
114#include <ppc405.h>
115#endif
116
Stefan Roese36ea16f2008-06-02 14:57:41 +0200117#include <asm/ppc4xx-sdram.h>
Stefan Roese7ee26192008-06-24 17:18:50 +0200118#include <asm/ppc4xx-ebc.h>
Ricardo Ribalda Delgadod865fd02008-07-17 11:44:12 +0200119#if !defined(CONFIG_XILINX_440)
Stefan Roese4fb25a32008-06-25 10:59:22 +0200120#include <asm/ppc4xx-uic.h>
Ricardo Ribalda Delgadod865fd02008-07-17 11:44:12 +0200121#endif
Stefan Roese36ea16f2008-06-02 14:57:41 +0200122
Stefan Roese087dfdb2007-10-21 08:12:41 +0200123/*
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700124 * Macro for generating register field mnemonics
125 */
126#define PPC_REG_BITS 32
127#define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit)))
128
129/*
130 * Elide casts when assembling register mnemonics
131 */
132#ifndef __ASSEMBLY__
133#define static_cast(type, val) (type)(val)
134#else
135#define static_cast(type, val) (val)
136#endif
137
138/*
Stefan Roese087dfdb2007-10-21 08:12:41 +0200139 * Common stuff for 4xx (405 and 440)
140 */
141
142#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
143#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000)
144
145#define RESET_VECTOR 0xfffffffc
146#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache
147 line aligned data. */
148
149#define CPR0_DCR_BASE 0x0C
150#define cprcfga (CPR0_DCR_BASE+0x0)
151#define cprcfgd (CPR0_DCR_BASE+0x1)
152
153#define SDR_DCR_BASE 0x0E
154#define sdrcfga (SDR_DCR_BASE+0x0)
155#define sdrcfgd (SDR_DCR_BASE+0x1)
156
157#define SDRAM_DCR_BASE 0x10
158#define memcfga (SDRAM_DCR_BASE+0x0)
159#define memcfgd (SDRAM_DCR_BASE+0x1)
160
161#define EBC_DCR_BASE 0x12
162#define ebccfga (EBC_DCR_BASE+0x0)
163#define ebccfgd (EBC_DCR_BASE+0x1)
164
165/*
166 * Macros for indirect DCR access
167 */
168#define mtcpr(reg, d) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0)
169#define mfcpr(reg, d) do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0)
170
171#define mtebc(reg, d) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0)
172#define mfebc(reg, d) do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0)
173
174#define mtsdram(reg, d) do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0)
175#define mfsdram(reg, d) do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0)
176
177#define mtsdr(reg, d) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0)
178#define mfsdr(reg, d) do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0)
179
180#ifndef __ASSEMBLY__
181
182typedef struct
183{
184 unsigned long freqDDR;
185 unsigned long freqEBC;
186 unsigned long freqOPB;
187 unsigned long freqPCI;
188 unsigned long freqPLB;
189 unsigned long freqTmrClk;
190 unsigned long freqUART;
191 unsigned long freqProcessor;
192 unsigned long freqVCOHz;
193 unsigned long freqVCOMhz; /* in MHz */
194 unsigned long pciClkSync; /* PCI clock is synchronous */
195 unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
196 unsigned long pllExtBusDiv;
197 unsigned long pllFbkDiv;
198 unsigned long pllFwdDiv;
199 unsigned long pllFwdDivA;
200 unsigned long pllFwdDivB;
201 unsigned long pllOpbDiv;
202 unsigned long pllPciDiv;
203 unsigned long pllPlbDiv;
204} PPC4xx_SYS_INFO;
205
206#endif /* __ASSEMBLY__ */
207
wdenk935ecca2002-08-06 20:46:37 +0000208#endif /* __PPC4XX_H__ */