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wdenk327f7a02001-11-28 17:49:55 +00001/*
2 * (C) Copyright 2001
3 * Thomas Koeller, tkoeller@gmx.net
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __ASSEMBLY__
25#define __ASSEMBLY__ 1
26#endif
27
28#include <config.h>
29#include <asm/processor.h>
30#include <mpc824x.h>
31#include <ppc_asm.tmpl>
32
33#if defined(USE_DINK32)
34 /* We are running from RAM, so do not clear the MCCR1_MEMGO bit! */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020035 #define MCCR1VAL ((CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO)
wdenk327f7a02001-11-28 17:49:55 +000036#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020037 #define MCCR1VAL (CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT)
wdenk327f7a02001-11-28 17:49:55 +000038#endif
39
40 .text
41
42 /* Values to program into memory controller registers */
43tbl: .long MCCR1, MCCR1VAL
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044 .long MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT
wdenk327f7a02001-11-28 17:49:55 +000045 .long MCCR3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020046 .long (((CONFIG_SYS_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \
47 (CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT) | \
48 (CONFIG_SYS_RDLAT << MCCR3_RDLAT_SHIFT)
wdenk327f7a02001-11-28 17:49:55 +000049 .long MCCR4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050 .long (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \
51 (CONFIG_SYS_REGISTERD_TYPE_BUFFER << 20) | \
52 (((CONFIG_SYS_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \
53 ((CONFIG_SYS_SDMODE_CAS_LAT << 4) | (CONFIG_SYS_SDMODE_WRAP << 3) | \
54 (CONFIG_SYS_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \
55 (CONFIG_SYS_ACTTORW << MCCR4_ACTTORW_SHIFT) | \
56 ((CONFIG_SYS_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT )
wdenk327f7a02001-11-28 17:49:55 +000057 .long MSAR1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020058 .long (((CONFIG_SYS_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \
59 (((CONFIG_SYS_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \
60 (((CONFIG_SYS_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
61 (((CONFIG_SYS_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
wdenk327f7a02001-11-28 17:49:55 +000062 .long EMSAR1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063 .long (((CONFIG_SYS_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \
64 (((CONFIG_SYS_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \
65 (((CONFIG_SYS_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
66 (((CONFIG_SYS_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
wdenk327f7a02001-11-28 17:49:55 +000067 .long MSAR2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068 .long (((CONFIG_SYS_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \
69 (((CONFIG_SYS_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \
70 (((CONFIG_SYS_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
71 (((CONFIG_SYS_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
wdenk327f7a02001-11-28 17:49:55 +000072 .long EMSAR2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073 .long (((CONFIG_SYS_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \
74 (((CONFIG_SYS_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \
75 (((CONFIG_SYS_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
76 (((CONFIG_SYS_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
wdenk327f7a02001-11-28 17:49:55 +000077 .long MEAR1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078 .long (((CONFIG_SYS_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \
79 (((CONFIG_SYS_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \
80 (((CONFIG_SYS_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
81 (((CONFIG_SYS_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
wdenk327f7a02001-11-28 17:49:55 +000082 .long EMEAR1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083 .long (((CONFIG_SYS_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \
84 (((CONFIG_SYS_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \
85 (((CONFIG_SYS_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
86 (((CONFIG_SYS_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
wdenk327f7a02001-11-28 17:49:55 +000087 .long MEAR2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088 .long (((CONFIG_SYS_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \
89 (((CONFIG_SYS_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \
90 (((CONFIG_SYS_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
91 (((CONFIG_SYS_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
wdenk327f7a02001-11-28 17:49:55 +000092 .long EMEAR2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093 .long (((CONFIG_SYS_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \
94 (((CONFIG_SYS_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \
95 (((CONFIG_SYS_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
96 (((CONFIG_SYS_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
wdenk327f7a02001-11-28 17:49:55 +000097 .long 0
98
99
wdenk327f7a02001-11-28 17:49:55 +0000100 /*
101 * Early CPU initialization. Set up memory controller, so we can access any RAM at all. This
102 * must be done in assembly, since we have no stack at this point.
103 */
104 .global early_init_f
105early_init_f:
106 mflr r10
107
108 /* basic memory controller configuration */
109 lis r3, CONFIG_ADDR_HIGH
110 lis r4, CONFIG_DATA_HIGH
111 bl lab
112lab: mflr r5
113 lwzu r0, tbl - lab(r5)
114loop: lwz r1, 4(r5)
115 stwbrx r0, 0, r3
116 eieio
117 stwbrx r1, 0, r4
118 eieio
119 lwzu r0, 8(r5)
120 cmpli cr0, 0, r0, 0
121 bne cr0, loop
122
123 /* set bank enable bits */
124 lis r0, MBER@h
125 ori r0, 0, MBER@l
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126 li r1, CONFIG_SYS_BANK_ENABLE
wdenk327f7a02001-11-28 17:49:55 +0000127 stwbrx r0, 0, r3
128 eieio
129 stb r1, 0(r4)
130 eieio
131
132 /* delay loop */
133 lis r0, 0x0003
134 mtctr r0
135delay: bdnz delay
136
137 /* enable memory controller */
138 lis r0, MCCR1@h
139 ori r0, 0, MCCR1@l
140 stwbrx r0, 0, r3
141 eieio
142 lwbrx r0, 0, r4
143 oris r0, 0, MCCR1_MEMGO@h
144 stwbrx r0, 0, r4
145 eieio
146
147 /* set up stack pointer */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148 lis r1, CONFIG_SYS_INIT_SP_OFFSET@h
149 ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
wdenk327f7a02001-11-28 17:49:55 +0000150
151 mtlr r10
152 blr