blob: f0169959af407740732fca54c58b64eda69d556c [file] [log] [blame]
Jon Loeligerd9b94f22005-07-25 14:05:07 -05001/*
Kumar Gala7b626882009-11-04 11:15:29 -06002 * Copyright 2004, 2007, 200 Freescale Semiconductor, Inc.
Jon Loeligerd9b94f22005-07-25 14:05:07 -05003 *
4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
26#include <pci.h>
27#include <asm/processor.h>
Jon Loeligere31d2c12008-03-18 13:51:06 -050028#include <asm/mmu.h>
Jon Loeligerd9b94f22005-07-25 14:05:07 -050029#include <asm/immap_85xx.h>
Kumar Galac8514622009-04-02 13:22:48 -050030#include <asm/fsl_pci.h>
Jon Loeligere31d2c12008-03-18 13:51:06 -050031#include <asm/fsl_ddr_sdram.h>
Jon Loeligera30a5492008-03-04 10:03:03 -060032#include <spd_sdram.h>
Andy Fleming09f3e092006-09-13 10:34:18 -050033#include <miiphy.h>
Kumar Galab90d2542007-11-29 00:11:44 -060034#include <libfdt.h>
35#include <fdt_support.h>
Jon Loeligerd9b94f22005-07-25 14:05:07 -050036
37#include "../common/cadmus.h"
38#include "../common/eeprom.h"
Matthew McClintockbf1dfff2006-06-28 10:46:13 -050039#include "../common/via.h"
Jon Loeligerd9b94f22005-07-25 14:05:07 -050040
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -050041DECLARE_GLOBAL_DATA_PTR;
42
Jon Loeligerd9b94f22005-07-25 14:05:07 -050043void local_bus_init(void);
44void sdram_init(void);
45
Jon Loeligerd9b94f22005-07-25 14:05:07 -050046int checkboard (void)
47{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
49 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
Jon Loeligerd9b94f22005-07-25 14:05:07 -050050
51 /* PCI slot in USER bits CSR[6:7] by convention. */
52 uint pci_slot = get_pci_slot ();
53
Jon Loeligerd9b94f22005-07-25 14:05:07 -050054 uint cpu_board_rev = get_cpu_board_revision ();
55
56 printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
57 get_board_version (), pci_slot);
58
59 printf ("CPU Board Revision %d.%d (0x%04x)\n",
60 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
61 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
Jon Loeligerd9b94f22005-07-25 14:05:07 -050062 /*
63 * Initialize local bus.
64 */
65 local_bus_init ();
66
Jon Loeligerd9b94f22005-07-25 14:05:07 -050067 /*
68 * Hack TSEC 3 and 4 IO voltages.
69 */
70 gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
71
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -050072 ecm->eedr = 0xffffffff; /* clear ecm errors */
73 ecm->eeer = 0xffffffff; /* enable ecm errors */
Jon Loeligerd9b94f22005-07-25 14:05:07 -050074 return 0;
75}
76
Becky Bruce9973e3c2008-06-09 16:03:40 -050077phys_size_t
Jon Loeligerd9b94f22005-07-25 14:05:07 -050078initdram(int board_type)
79{
80 long dram_size = 0;
Jon Loeligerd9b94f22005-07-25 14:05:07 -050081
82 puts("Initializing\n");
83
84#if defined(CONFIG_DDR_DLL)
85 {
86 /*
87 * Work around to stabilize DDR DLL MSYNC_IN.
88 * Errata DDR9 seems to have been fixed.
89 * This is now the workaround for Errata DDR11:
90 * Override DLL = 1, Course Adj = 1, Tap Select = 0
91 */
92
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Jon Loeligerd9b94f22005-07-25 14:05:07 -050094
95 gur->ddrdllcr = 0x81000000;
96 asm("sync;isync;msync");
97 udelay(200);
98 }
99#endif
Jon Loeligere31d2c12008-03-18 13:51:06 -0500100
101 dram_size = fsl_ddr_sdram();
102 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
103 dram_size *= 0x100000;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500104
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500105 /*
106 * SDRAM Initialization
107 */
108 sdram_init();
109
110 puts(" DDR: ");
111 return dram_size;
112}
113
114/*
115 * Initialize Local Bus
116 */
117void
118local_bus_init(void)
119{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Becky Brucef51cdaf2010-06-17 11:37:20 -0500121 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500122
123 uint clkdiv;
124 uint lbc_hz;
125 sys_info_t sysinfo;
126
127 get_sys_info(&sysinfo);
Trent Piephoa5d212a2008-12-03 15:16:34 -0800128 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500129 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
130
131 gur->lbiuiplldcr1 = 0x00078080;
132 if (clkdiv == 16) {
133 gur->lbiuiplldcr0 = 0x7c0f1bf0;
134 } else if (clkdiv == 8) {
135 gur->lbiuiplldcr0 = 0x6c0f1bf0;
136 } else if (clkdiv == 4) {
137 gur->lbiuiplldcr0 = 0x5c0f1bf0;
138 }
139
140 lbc->lcrr |= 0x00030000;
141
142 asm("sync;isync;msync");
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500143
144 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
145 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500146}
147
148/*
149 * Initialize SDRAM memory on the Local Bus.
150 */
151void
152sdram_init(void)
153{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500155
156 uint idx;
Becky Brucef51cdaf2010-06-17 11:37:20 -0500157 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500159 uint cpu_board_rev;
160 uint lsdmr_common;
161
162 puts(" SDRAM: ");
163
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500165
166 /*
167 * Setup SDRAM Base and Option Registers
168 */
Becky Brucef51cdaf2010-06-17 11:37:20 -0500169 set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
170 set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500172 asm("msync");
173
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
175 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500176 asm("msync");
177
178 /*
179 * MPC8548 uses "new" 15-16 style addressing.
180 */
181 cpu_board_rev = get_cpu_board_revision();
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500183 lsdmr_common |= LSDMR_BSMA1516;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500184
185 /*
186 * Issue PRECHARGE ALL command.
187 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500188 lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500189 asm("sync;msync");
190 *sdram_addr = 0xff;
191 ppcDcbf((unsigned long) sdram_addr);
192 udelay(100);
193
194 /*
195 * Issue 8 AUTO REFRESH commands.
196 */
197 for (idx = 0; idx < 8; idx++) {
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500198 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500199 asm("sync;msync");
200 *sdram_addr = 0xff;
201 ppcDcbf((unsigned long) sdram_addr);
202 udelay(100);
203 }
204
205 /*
206 * Issue 8 MODE-set command.
207 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500208 lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500209 asm("sync;msync");
210 *sdram_addr = 0xff;
211 ppcDcbf((unsigned long) sdram_addr);
212 udelay(100);
213
214 /*
215 * Issue NORMAL OP command.
216 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500217 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500218 asm("sync;msync");
219 *sdram_addr = 0xff;
220 ppcDcbf((unsigned long) sdram_addr);
221 udelay(200); /* Overkill. Must wait > 200 bus cycles */
222
223#endif /* enable SDRAM init */
224}
225
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500226#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
Matthew McClintockbf1dfff2006-06-28 10:46:13 -0500227/* For some reason the Tundra PCI bridge shows up on itself as a
228 * different device. Work around that by refusing to configure it.
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500229 */
Matthew McClintockbf1dfff2006-06-28 10:46:13 -0500230void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500231
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500232static struct pci_config_table pci_mpc85xxcds_config_table[] = {
Matthew McClintockbf1dfff2006-06-28 10:46:13 -0500233 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
Randy Vinson7f3f2bd2007-02-27 19:42:22 -0700234 {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
235 {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
Andy Flemingffa621a2007-02-24 01:08:13 -0600236 mpc85xx_config_via_usbide, {0,0,0}},
Randy Vinson7f3f2bd2007-02-27 19:42:22 -0700237 {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
238 mpc85xx_config_via_usb, {0,0,0}},
239 {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
240 mpc85xx_config_via_usb2, {0,0,0}},
241 {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
Andy Flemingffa621a2007-02-24 01:08:13 -0600242 mpc85xx_config_via_power, {0,0,0}},
Randy Vinson7f3f2bd2007-02-27 19:42:22 -0700243 {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
244 mpc85xx_config_via_ac97, {0,0,0}},
Andy Flemingffa621a2007-02-24 01:08:13 -0600245 {},
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500246};
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500247
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500248static struct pci_controller pci1_hose = {
249 config_table: pci_mpc85xxcds_config_table};
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500250#endif /* CONFIG_PCI */
251
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500252#ifdef CONFIG_PCI2
253static struct pci_controller pci2_hose;
254#endif /* CONFIG_PCI2 */
255
256#ifdef CONFIG_PCIE1
257static struct pci_controller pcie1_hose;
258#endif /* CONFIG_PCIE1 */
259
Kumar Gala7b626882009-11-04 11:15:29 -0600260void pci_init_board(void)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500261{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Kumar Gala7b626882009-11-04 11:15:29 -0600263 struct fsl_pci_info pci_info[4];
264 u32 devdisr, pordevsr, io_sel;
265 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
266 int first_free_busno = 0;
267 int num = 0;
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500268
Kumar Gala7b626882009-11-04 11:15:29 -0600269 int pcie_ep, pcie_configured;
270
271 devdisr = in_be32(&gur->devdisr);
272 pordevsr = in_be32(&gur->pordevsr);
273 porpllsr = in_be32(&gur->porpllsr);
274 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
275
276 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500277
278#ifdef CONFIG_PCI1
Kumar Gala7b626882009-11-04 11:15:29 -0600279 pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
280 pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
281 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
282 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500283
Kumar Gala7b626882009-11-04 11:15:29 -0600284 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
285 SET_STD_PCI_INFO(pci_info[num], 1);
286 pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
287 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500288 (pci_32) ? 32 : 64,
289 (pci_speed == 33333000) ? "33" :
290 (pci_speed == 66666000) ? "66" : "unknown",
291 pci_clk_sel ? "sync" : "async",
292 pci_agent ? "agent" : "host",
Kumar Gala7b626882009-11-04 11:15:29 -0600293 pci_arb ? "arbiter" : "external-arbiter",
294 pci_info[num].regs);
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500295
Kumar Gala7b626882009-11-04 11:15:29 -0600296 first_free_busno = fsl_pci_init_port(&pci_info[num++],
297 &pci1_hose, first_free_busno);
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500298
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500299#ifdef CONFIG_PCIX_CHECK
Kumar Gala7b626882009-11-04 11:15:29 -0600300 if (!(pordevsr & MPC85xx_PORDEVSR_PCI1)) {
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500301 /* PCI-X init */
302 if (CONFIG_SYS_CLK_FREQ < 66000000)
303 printf("PCI-X will only work at 66 MHz\n");
304
305 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
306 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
307 pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
308 }
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500309#endif
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500310 } else {
311 printf (" PCI: disabled\n");
312 }
Kumar Gala7b626882009-11-04 11:15:29 -0600313
314 puts("\n");
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500315#else
Kumar Gala7b626882009-11-04 11:15:29 -0600316 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500317#endif
318
319#ifdef CONFIG_PCI2
320{
Kumar Gala7b626882009-11-04 11:15:29 -0600321 uint pci2_clk_sel = porpllsr & 0x4000; /* PORPLLSR[17] */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500322 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
323 if (pci_dual) {
324 printf (" PCI2: 32 bit, 66 MHz, %s\n",
325 pci2_clk_sel ? "sync" : "async");
326 } else {
327 printf (" PCI2: disabled\n");
328 }
329}
330#else
Kumar Gala7b626882009-11-04 11:15:29 -0600331 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500332#endif /* CONFIG_PCI2 */
333
334#ifdef CONFIG_PCIE1
Kumar Gala7b626882009-11-04 11:15:29 -0600335 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500336
Kumar Gala7b626882009-11-04 11:15:29 -0600337 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
338 SET_STD_PCIE_INFO(pci_info[num], 1);
339 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
340 printf (" PCIE1 connected to Slot as %s (base addr %lx)\n",
Peter Tyser64917ca2010-01-17 15:38:26 -0600341 pcie_ep ? "Endpoint" : "Root Complex",
Kumar Gala7b626882009-11-04 11:15:29 -0600342 pci_info[num].regs);
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500343
Kumar Gala7b626882009-11-04 11:15:29 -0600344 first_free_busno = fsl_pci_init_port(&pci_info[num++],
345 &pcie1_hose, first_free_busno);
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500346 } else {
Kumar Gala7b626882009-11-04 11:15:29 -0600347 printf (" PCIE1: disabled\n");
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500348 }
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500349
Kumar Gala7b626882009-11-04 11:15:29 -0600350 puts("\n");
351#else
352 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
353#endif
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500354}
Andy Fleming09f3e092006-09-13 10:34:18 -0500355
356int last_stage_init(void)
357{
Jon Loeligerf5012822006-10-20 15:54:34 -0500358 unsigned short temp;
Andy Fleming09f3e092006-09-13 10:34:18 -0500359
360 /* Change the resistors for the PHY */
361 /* This is needed to get the RGMII working for the 1.3+
362 * CDS cards */
363 if (get_board_version() == 0x13) {
Kim Phillips255a35772007-05-16 16:52:19 -0500364 miiphy_write(CONFIG_TSEC1_NAME,
Andy Fleming09f3e092006-09-13 10:34:18 -0500365 TSEC1_PHY_ADDR, 29, 18);
366
Kim Phillips255a35772007-05-16 16:52:19 -0500367 miiphy_read(CONFIG_TSEC1_NAME,
Andy Fleming09f3e092006-09-13 10:34:18 -0500368 TSEC1_PHY_ADDR, 30, &temp);
369
370 temp = (temp & 0xf03f);
371 temp |= 2 << 9; /* 36 ohm */
372 temp |= 2 << 6; /* 39 ohm */
373
Kim Phillips255a35772007-05-16 16:52:19 -0500374 miiphy_write(CONFIG_TSEC1_NAME,
Andy Fleming09f3e092006-09-13 10:34:18 -0500375 TSEC1_PHY_ADDR, 30, temp);
376
Kim Phillips255a35772007-05-16 16:52:19 -0500377 miiphy_write(CONFIG_TSEC1_NAME,
Andy Fleming09f3e092006-09-13 10:34:18 -0500378 TSEC1_PHY_ADDR, 29, 3);
379
Kim Phillips255a35772007-05-16 16:52:19 -0500380 miiphy_write(CONFIG_TSEC1_NAME,
Andy Fleming09f3e092006-09-13 10:34:18 -0500381 TSEC1_PHY_ADDR, 30, 0x8000);
382 }
383
384 return 0;
385}
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500386
387
Kumar Galab90d2542007-11-29 00:11:44 -0600388#if defined(CONFIG_OF_BOARD_SETUP)
Kumar Gala2dba0de2008-10-21 08:28:33 -0500389void ft_pci_setup(void *blob, bd_t *bd)
390{
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500391#ifdef CONFIG_PCI1
Kumar Gala2dba0de2008-10-21 08:28:33 -0500392 ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500393#endif
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500394#ifdef CONFIG_PCIE1
Kumar Gala2dba0de2008-10-21 08:28:33 -0500395 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500396#endif
397}
398#endif