| Tom Warren | 3f82b1d | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2010,2011 |
| 3 | * NVIDIA Corporation <www.nvidia.com> |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #ifndef _TEGRA2_H_ |
| 25 | #define _TEGRA2_H_ |
| 26 | |
| 27 | #define NV_PA_SDRAM_BASE 0x00000000 |
| Tom Warren | 74652cf | 2011-04-14 12:18:06 +0000 | [diff] [blame] | 28 | #define NV_PA_ARM_PERIPHBASE 0x50040000 |
| 29 | #define NV_PA_PG_UP_BASE 0x60000000 |
| Tom Warren | 3f82b1d | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 30 | #define NV_PA_TMRUS_BASE 0x60005010 |
| 31 | #define NV_PA_CLK_RST_BASE 0x60006000 |
| Tom Warren | 74652cf | 2011-04-14 12:18:06 +0000 | [diff] [blame] | 32 | #define NV_PA_FLOW_BASE 0x60007000 |
| Tom Warren | c5e9313 | 2011-04-14 12:09:40 +0000 | [diff] [blame] | 33 | #define NV_PA_GPIO_BASE 0x6000D000 |
| Tom Warren | 74652cf | 2011-04-14 12:18:06 +0000 | [diff] [blame] | 34 | #define NV_PA_EVP_BASE 0x6000F000 |
| Tom Warren | 3f82b1d | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 35 | #define NV_PA_APB_MISC_BASE 0x70000000 |
| 36 | #define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000) |
| 37 | #define NV_PA_APB_UARTB_BASE (NV_PA_APB_MISC_BASE + 0x6040) |
| 38 | #define NV_PA_APB_UARTC_BASE (NV_PA_APB_MISC_BASE + 0x6200) |
| 39 | #define NV_PA_APB_UARTD_BASE (NV_PA_APB_MISC_BASE + 0x6300) |
| 40 | #define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400) |
| Tom Warren | 9112ef8 | 2011-11-05 09:48:11 +0000 | [diff] [blame] | 41 | #define TEGRA2_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380) |
| Simon Glass | f4589a7 | 2012-02-03 15:13:52 +0000 | [diff] [blame^] | 42 | #define TEGRA2_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400) |
| Tom Warren | 74652cf | 2011-04-14 12:18:06 +0000 | [diff] [blame] | 43 | #define NV_PA_CSITE_BASE 0x70040000 |
| Simon Glass | 87f938c | 2012-02-27 10:52:49 +0000 | [diff] [blame] | 44 | #define TEGRA_USB1_BASE 0xC5000000 |
| 45 | #define TEGRA_USB3_BASE 0xC5008000 |
| Tom Warren | 3f82b1d | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 46 | |
| 47 | #define TEGRA2_SDRC_CS0 NV_PA_SDRAM_BASE |
| 48 | #define LOW_LEVEL_SRAM_STACK 0x4000FFFC |
| Tom Warren | 74652cf | 2011-04-14 12:18:06 +0000 | [diff] [blame] | 49 | #define EARLY_AVP_STACK (NV_PA_SDRAM_BASE + 0x20000) |
| 50 | #define EARLY_CPU_STACK (EARLY_AVP_STACK - 4096) |
| 51 | #define PG_UP_TAG_AVP 0xAAAAAAAA |
| Tom Warren | 3f82b1d | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 52 | |
| 53 | #ifndef __ASSEMBLY__ |
| 54 | struct timerus { |
| 55 | unsigned int cntr_1us; |
| 56 | }; |
| 57 | #else /* __ASSEMBLY__ */ |
| Simon Glass | f4589a7 | 2012-02-03 15:13:52 +0000 | [diff] [blame^] | 58 | #define PRM_RSTCTRL TEGRA2_PMC_BASE |
| Tom Warren | 3f82b1d | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 59 | #endif |
| 60 | |
| 61 | #endif /* TEGRA2_H */ |