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wdenk0442ed82002-11-03 10:24:00 +00001/*
2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
Stefan Roese3cb86f32007-03-24 15:45:34 +01005 * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
Grant Ericksonc821b5f2008-05-22 14:44:14 -07006 * Copyright (c) 2008 Nuovation System Designs, LLC
7 * Grant Erickson <gerickson@nuovations.com>
wdenk0442ed82002-11-03 10:24:00 +00008 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +020027/*------------------------------------------------------------------------------+
Josh Boyer31773492009-08-07 13:53:20 -040028 * This source code is dual-licensed. You may use it under the terms of the
29 * GNU General Public License version 2, or under the license below.
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +020030 *
31 * This source code has been made available to you by IBM on an AS-IS
32 * basis. Anyone receiving this source is licensed under IBM
33 * copyrights to use it in any way he or she deems fit, including
34 * copying it, modifying it, compiling it, and redistributing it either
35 * with or without modifications. No license under IBM patents or
36 * patent applications is to be implied by the copyright license.
37 *
38 * Any user of this software should understand that IBM cannot provide
39 * technical support for this software and will not be responsible for
40 * any consequences resulting from the use of this software.
41 *
42 * Any person who transfers this source code or any derivative work
43 * must include the IBM copyright notice, this paragraph, and the
44 * preceding two paragraphs in the transferred software.
45 *
46 * COPYRIGHT I B M CORPORATION 1995
47 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
48 *-------------------------------------------------------------------------------
49 */
wdenk0442ed82002-11-03 10:24:00 +000050
Wolfgang Denk0c8721a2005-09-23 11:05:55 +020051/* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards
wdenk0442ed82002-11-03 10:24:00 +000052 *
53 *
54 * The processor starts at 0xfffffffc and the code is executed
55 * from flash/rom.
56 * in memory, but as long we don't jump around before relocating.
57 * board_init lies at a quite high address and when the cpu has
58 * jumped there, everything is ok.
59 * This works because the cpu gives the FLASH (CS0) the whole
60 * address space at startup, and board_init lies as a echo of
61 * the flash somewhere up there in the memorymap.
62 *
63 * board_init will change CS0 to be positioned at the correct
64 * address and (s)dram will be positioned at address 0
65 */
66#include <config.h>
wdenk0442ed82002-11-03 10:24:00 +000067#include <ppc4xx.h>
Peter Tyser561858e2008-11-03 09:30:59 -060068#include <timestamp.h>
wdenk0442ed82002-11-03 10:24:00 +000069#include <version.h>
70
71#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
72
73#include <ppc_asm.tmpl>
74#include <ppc_defs.h>
75
76#include <asm/cache.h>
77#include <asm/mmu.h>
Dave Mitchellb14ca4b2008-11-20 14:00:49 -060078#include <asm/ppc4xx-isram.h>
wdenk0442ed82002-11-03 10:24:00 +000079
80#ifndef CONFIG_IDENT_STRING
81#define CONFIG_IDENT_STRING ""
82#endif
83
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#ifdef CONFIG_SYS_INIT_DCACHE_CS
85# if (CONFIG_SYS_INIT_DCACHE_CS == 0)
Stefan Roesed1c3b272009-09-09 16:25:29 +020086# define PBxAP PB1AP
87# define PBxCR PB0CR
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088# if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
89# define PBxAP_VAL CONFIG_SYS_EBC_PB0AP
90# define PBxCR_VAL CONFIG_SYS_EBC_PB0CR
Grant Ericksonc821b5f2008-05-22 14:44:14 -070091# endif
wdenk0442ed82002-11-03 10:24:00 +000092# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093# if (CONFIG_SYS_INIT_DCACHE_CS == 1)
Stefan Roesed1c3b272009-09-09 16:25:29 +020094# define PBxAP PB1AP
95# define PBxCR PB1CR
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096# if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR))
97# define PBxAP_VAL CONFIG_SYS_EBC_PB1AP
98# define PBxCR_VAL CONFIG_SYS_EBC_PB1CR
Grant Ericksonc821b5f2008-05-22 14:44:14 -070099# endif
wdenk0442ed82002-11-03 10:24:00 +0000100# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101# if (CONFIG_SYS_INIT_DCACHE_CS == 2)
Stefan Roesed1c3b272009-09-09 16:25:29 +0200102# define PBxAP PB2AP
103# define PBxCR PB2CR
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104# if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR))
105# define PBxAP_VAL CONFIG_SYS_EBC_PB2AP
106# define PBxCR_VAL CONFIG_SYS_EBC_PB2CR
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700107# endif
wdenk0442ed82002-11-03 10:24:00 +0000108# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109# if (CONFIG_SYS_INIT_DCACHE_CS == 3)
Stefan Roesed1c3b272009-09-09 16:25:29 +0200110# define PBxAP PB3AP
111# define PBxCR PB3CR
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112# if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR))
113# define PBxAP_VAL CONFIG_SYS_EBC_PB3AP
114# define PBxCR_VAL CONFIG_SYS_EBC_PB3CR
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700115# endif
wdenk0442ed82002-11-03 10:24:00 +0000116# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117# if (CONFIG_SYS_INIT_DCACHE_CS == 4)
Stefan Roesed1c3b272009-09-09 16:25:29 +0200118# define PBxAP PB4AP
119# define PBxCR PB4CR
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120# if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR))
121# define PBxAP_VAL CONFIG_SYS_EBC_PB4AP
122# define PBxCR_VAL CONFIG_SYS_EBC_PB4CR
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700123# endif
wdenk0442ed82002-11-03 10:24:00 +0000124# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125# if (CONFIG_SYS_INIT_DCACHE_CS == 5)
Stefan Roesed1c3b272009-09-09 16:25:29 +0200126# define PBxAP PB5AP
127# define PBxCR PB5CR
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128# if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR))
129# define PBxAP_VAL CONFIG_SYS_EBC_PB5AP
130# define PBxCR_VAL CONFIG_SYS_EBC_PB5CR
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700131# endif
wdenk0442ed82002-11-03 10:24:00 +0000132# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133# if (CONFIG_SYS_INIT_DCACHE_CS == 6)
Stefan Roesed1c3b272009-09-09 16:25:29 +0200134# define PBxAP PB6AP
135# define PBxCR PB6CR
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136# if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR))
137# define PBxAP_VAL CONFIG_SYS_EBC_PB6AP
138# define PBxCR_VAL CONFIG_SYS_EBC_PB6CR
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700139# endif
wdenk0442ed82002-11-03 10:24:00 +0000140# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141# if (CONFIG_SYS_INIT_DCACHE_CS == 7)
Stefan Roesed1c3b272009-09-09 16:25:29 +0200142# define PBxAP PB7AP
143# define PBxCR PB7CR
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144# if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR))
145# define PBxAP_VAL CONFIG_SYS_EBC_PB7AP
146# define PBxCR_VAL CONFIG_SYS_EBC_PB7CR
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700147# endif
148# endif
149# ifndef PBxAP_VAL
150# define PBxAP_VAL 0
151# endif
152# ifndef PBxCR_VAL
153# define PBxCR_VAL 0
154# endif
155/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156 * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700157 * used as temporary stack pointer for the primordial stack
158 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159# ifndef CONFIG_SYS_INIT_DCACHE_PBxAR
160# define CONFIG_SYS_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700161 EBC_BXAP_TWT_ENCODE(7) | \
162 EBC_BXAP_BCE_DISABLE | \
163 EBC_BXAP_BCT_2TRANS | \
164 EBC_BXAP_CSN_ENCODE(0) | \
165 EBC_BXAP_OEN_ENCODE(0) | \
166 EBC_BXAP_WBN_ENCODE(0) | \
167 EBC_BXAP_WBF_ENCODE(0) | \
168 EBC_BXAP_TH_ENCODE(2) | \
169 EBC_BXAP_RE_DISABLED | \
170 EBC_BXAP_SOR_NONDELAYED | \
171 EBC_BXAP_BEM_WRITEONLY | \
172 EBC_BXAP_PEN_DISABLED)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173# endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */
174# ifndef CONFIG_SYS_INIT_DCACHE_PBxCR
175# define CONFIG_SYS_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR) | \
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700176 EBC_BXCR_BS_64MB | \
177 EBC_BXCR_BU_RW | \
178 EBC_BXCR_BW_16BIT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179# endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */
180# ifndef CONFIG_SYS_INIT_RAM_PATTERN
181# define CONFIG_SYS_INIT_RAM_PATTERN 0xDEADDEAD
wdenk0442ed82002-11-03 10:24:00 +0000182# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#endif /* CONFIG_SYS_INIT_DCACHE_CS */
wdenk0442ed82002-11-03 10:24:00 +0000184
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_END > (4 << 10)))
186#error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_END!
Stefan Roese28d77d92008-01-30 14:48:28 +0100187#endif
188
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700189/*
190 * Unless otherwise overriden, enable two 128MB cachable instruction regions
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191 * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering
192 * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions.
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700193 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#if !defined(CONFIG_SYS_FLASH_BASE)
Stefan Roese64852d02008-06-02 14:35:44 +0200195/* If not already defined, set it to the "last" 128MByte region */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196# define CONFIG_SYS_FLASH_BASE 0xf8000000
Stefan Roese64852d02008-06-02 14:35:44 +0200197#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#if !defined(CONFIG_SYS_ICACHE_SACR_VALUE)
199# define CONFIG_SYS_ICACHE_SACR_VALUE \
200 (PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + ( 0 << 20)) | \
201 PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \
202 PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE))
203#endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700204
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#if !defined(CONFIG_SYS_DCACHE_SACR_VALUE)
206# define CONFIG_SYS_DCACHE_SACR_VALUE \
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700207 (0x00000000)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700209
Stefan Roese4978e602010-05-27 16:45:20 +0200210#if !defined(CONFIG_SYS_TLB_FOR_BOOT_FLASH)
211#define CONFIG_SYS_TLB_FOR_BOOT_FLASH 0 /* use TLB 0 as default */
212#endif
213
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +0200214#define function_prolog(func_name) .text; \
Stefan Roesecf959c72007-06-01 15:27:11 +0200215 .align 2; \
216 .globl func_name; \
217 func_name:
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +0200218#define function_epilog(func_name) .type func_name,@function; \
Stefan Roesecf959c72007-06-01 15:27:11 +0200219 .size func_name,.-func_name
220
wdenk0442ed82002-11-03 10:24:00 +0000221/* We don't want the MMU yet.
222*/
223#undef MSR_KERNEL
224#define MSR_KERNEL ( MSR_ME ) /* Machine Check */
225
226
227 .extern ext_bus_cntlr_init
Stefan Roese887e2ec2006-09-07 11:51:23 +0200228#ifdef CONFIG_NAND_U_BOOT
229 .extern reconfig_tlb0
230#endif
wdenk0442ed82002-11-03 10:24:00 +0000231
232/*
233 * Set up GOT: Global Offset Table
234 *
Joakim Tjernlund0f8aa152010-01-19 14:41:56 +0100235 * Use r12 to access the GOT
wdenk0442ed82002-11-03 10:24:00 +0000236 */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200237#if !defined(CONFIG_NAND_SPL)
wdenk0442ed82002-11-03 10:24:00 +0000238 START_GOT
239 GOT_ENTRY(_GOT2_TABLE_)
240 GOT_ENTRY(_FIXUP_TABLE_)
241
242 GOT_ENTRY(_start)
243 GOT_ENTRY(_start_of_vectors)
244 GOT_ENTRY(_end_of_vectors)
245 GOT_ENTRY(transfer_to_handler)
246
wdenk3b57fe02003-05-30 12:48:29 +0000247 GOT_ENTRY(__init_end)
wdenk0442ed82002-11-03 10:24:00 +0000248 GOT_ENTRY(_end)
wdenk5d232d02003-05-22 22:52:13 +0000249 GOT_ENTRY(__bss_start)
wdenk0442ed82002-11-03 10:24:00 +0000250 END_GOT
Stefan Roese887e2ec2006-09-07 11:51:23 +0200251#endif /* CONFIG_NAND_SPL */
252
253#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
254 /*
255 * NAND U-Boot image is started from offset 0
256 */
257 .text
Stefan Roesec440bfe2007-06-06 11:42:13 +0200258#if defined(CONFIG_440)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200259 bl reconfig_tlb0
Stefan Roesec440bfe2007-06-06 11:42:13 +0200260#endif
Stefan Roese887e2ec2006-09-07 11:51:23 +0200261 GET_GOT
262 bl cpu_init_f /* run low-level CPU init code (from Flash) */
263 bl board_init_f
264#endif
wdenk0442ed82002-11-03 10:24:00 +0000265
Stefan Roesed8731332009-05-11 13:46:14 +0200266#if defined(CONFIG_SYS_RAMBOOT)
267 /*
268 * 4xx RAM-booting U-Boot image is started from offset 0
269 */
270 .text
271 bl _start_440
272#endif
273
wdenk0442ed82002-11-03 10:24:00 +0000274/*
275 * 440 Startup -- on reset only the top 4k of the effective
276 * address space is mapped in by an entry in the instruction
277 * and data shadow TLB. The .bootpg section is located in the
278 * top 4k & does only what's necessary to map in the the rest
279 * of the boot rom. Once the boot rom is mapped in we can
280 * proceed with normal startup.
281 *
282 * NOTE: CS0 only covers the top 2MB of the effective address
283 * space after reset.
284 */
285
286#if defined(CONFIG_440)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200287#if !defined(CONFIG_NAND_SPL)
wdenk0442ed82002-11-03 10:24:00 +0000288 .section .bootpg,"ax"
Stefan Roese887e2ec2006-09-07 11:51:23 +0200289#endif
wdenk0442ed82002-11-03 10:24:00 +0000290 .globl _start_440
291
292/**************************************************************************/
293_start_440:
Wolfgang Denk511d0c72006-10-09 00:42:01 +0200294 /*--------------------------------------------------------------------+
295 | 440EPX BUP Change - Hardware team request
296 +--------------------------------------------------------------------*/
Stefan Roese887e2ec2006-09-07 11:51:23 +0200297#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
298 sync
299 nop
300 nop
301#endif
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200302 /*----------------------------------------------------------------+
303 | Core bug fix. Clear the esr
304 +-----------------------------------------------------------------*/
Marian Balakowiczedd6cf22006-07-06 21:17:24 +0200305 li r0,0
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200306 mtspr SPRN_ESR,r0
wdenk0442ed82002-11-03 10:24:00 +0000307 /*----------------------------------------------------------------*/
308 /* Clear and set up some registers. */
309 /*----------------------------------------------------------------*/
Wolfgang Denkf901a832005-08-06 01:42:58 +0200310 iccci r0,r0 /* NOTE: operands not used for 440 */
311 dccci r0,r0 /* NOTE: operands not used for 440 */
wdenk0442ed82002-11-03 10:24:00 +0000312 sync
313 li r0,0
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200314 mtspr SPRN_SRR0,r0
315 mtspr SPRN_SRR1,r0
316 mtspr SPRN_CSRR0,r0
317 mtspr SPRN_CSRR1,r0
Stefan Roese887e2ec2006-09-07 11:51:23 +0200318 /* NOTE: 440GX adds machine check status regs */
319#if defined(CONFIG_440) && !defined(CONFIG_440GP)
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200320 mtspr SPRN_MCSRR0,r0
321 mtspr SPRN_MCSRR1,r0
322 mfspr r1,SPRN_MCSR
323 mtspr SPRN_MCSR,r1
wdenkba56f622004-02-06 23:19:44 +0000324#endif
Stefan Roese20532832006-11-22 13:20:50 +0100325
326 /*----------------------------------------------------------------*/
327 /* CCR0 init */
328 /*----------------------------------------------------------------*/
329 /* Disable store gathering & broadcast, guarantee inst/data
330 * cache block touch, force load/store alignment
331 * (see errata 1.12: 440_33)
332 */
333 lis r1,0x0030 /* store gathering & broadcast disable */
334 ori r1,r1,0x6000 /* cache touch */
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200335 mtspr SPRN_CCR0,r1
Stefan Roese20532832006-11-22 13:20:50 +0100336
wdenk0442ed82002-11-03 10:24:00 +0000337 /*----------------------------------------------------------------*/
338 /* Initialize debug */
339 /*----------------------------------------------------------------*/
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200340 mfspr r1,SPRN_DBCR0
Stefan Roese887e2ec2006-09-07 11:51:23 +0200341 andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
342 bne skip_debug_init /* if set, don't clear debug register */
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200343 mtspr SPRN_DBCR0,r0
344 mtspr SPRN_DBCR1,r0
345 mtspr SPRN_DBCR2,r0
346 mtspr SPRN_IAC1,r0
347 mtspr SPRN_IAC2,r0
348 mtspr SPRN_IAC3,r0
349 mtspr SPRN_DAC1,r0
350 mtspr SPRN_DAC2,r0
351 mtspr SPRN_DVC1,r0
352 mtspr SPRN_DVC2,r0
wdenk0442ed82002-11-03 10:24:00 +0000353
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200354 mfspr r1,SPRN_DBSR
355 mtspr SPRN_DBSR,r1 /* Clear all valid bits */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200356skip_debug_init:
wdenk0442ed82002-11-03 10:24:00 +0000357
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200358#if defined (CONFIG_440SPE)
359 /*----------------------------------------------------------------+
360 | Initialize Core Configuration Reg1.
361 | a. ICDPEI: Record even parity. Normal operation.
362 | b. ICTPEI: Record even parity. Normal operation.
363 | c. DCTPEI: Record even parity. Normal operation.
364 | d. DCDPEI: Record even parity. Normal operation.
365 | e. DCUPEI: Record even parity. Normal operation.
366 | f. DCMPEI: Record even parity. Normal operation.
367 | g. FCOM: Normal operation
368 | h. MMUPEI: Record even parity. Normal operation.
369 | i. FFF: Flush only as much data as necessary.
Marian Balakowiczedd6cf22006-07-06 21:17:24 +0200370 | j. TCS: Timebase increments from CPU clock.
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200371 +-----------------------------------------------------------------*/
Marian Balakowiczedd6cf22006-07-06 21:17:24 +0200372 li r0,0
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200373 mtspr SPRN_CCR1, r0
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200374
375 /*----------------------------------------------------------------+
376 | Reset the timebase.
377 | The previous write to CCR1 sets the timebase source.
378 +-----------------------------------------------------------------*/
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200379 mtspr SPRN_TBWL, r0
380 mtspr SPRN_TBWU, r0
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200381#endif
382
wdenk0442ed82002-11-03 10:24:00 +0000383 /*----------------------------------------------------------------*/
384 /* Setup interrupt vectors */
385 /*----------------------------------------------------------------*/
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200386 mtspr SPRN_IVPR,r0 /* Vectors start at 0x0000_0000 */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200387 li r1,0x0100
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200388 mtspr SPRN_IVOR0,r1 /* Critical input */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200389 li r1,0x0200
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200390 mtspr SPRN_IVOR1,r1 /* Machine check */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200391 li r1,0x0300
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200392 mtspr SPRN_IVOR2,r1 /* Data storage */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200393 li r1,0x0400
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200394 mtspr SPRN_IVOR3,r1 /* Instruction storage */
wdenk0442ed82002-11-03 10:24:00 +0000395 li r1,0x0500
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200396 mtspr SPRN_IVOR4,r1 /* External interrupt */
wdenk0442ed82002-11-03 10:24:00 +0000397 li r1,0x0600
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200398 mtspr SPRN_IVOR5,r1 /* Alignment */
wdenk0442ed82002-11-03 10:24:00 +0000399 li r1,0x0700
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200400 mtspr SPRN_IVOR6,r1 /* Program check */
wdenk0442ed82002-11-03 10:24:00 +0000401 li r1,0x0800
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200402 mtspr SPRN_IVOR7,r1 /* Floating point unavailable */
wdenk0442ed82002-11-03 10:24:00 +0000403 li r1,0x0c00
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200404 mtspr SPRN_IVOR8,r1 /* System call */
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200405 li r1,0x0a00
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200406 mtspr SPRN_IVOR9,r1 /* Auxiliary Processor unavailable */
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200407 li r1,0x0900
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200408 mtspr SPRN_IVOR10,r1 /* Decrementer */
wdenk0442ed82002-11-03 10:24:00 +0000409 li r1,0x1300
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200410 mtspr SPRN_IVOR13,r1 /* Data TLB error */
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200411 li r1,0x1400
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200412 mtspr SPRN_IVOR14,r1 /* Instr TLB error */
wdenk0442ed82002-11-03 10:24:00 +0000413 li r1,0x2000
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200414 mtspr SPRN_IVOR15,r1 /* Debug */
wdenk0442ed82002-11-03 10:24:00 +0000415
416 /*----------------------------------------------------------------*/
417 /* Configure cache regions */
418 /*----------------------------------------------------------------*/
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200419 mtspr SPRN_INV0,r0
420 mtspr SPRN_INV1,r0
421 mtspr SPRN_INV2,r0
422 mtspr SPRN_INV3,r0
423 mtspr SPRN_DNV0,r0
424 mtspr SPRN_DNV1,r0
425 mtspr SPRN_DNV2,r0
426 mtspr SPRN_DNV3,r0
427 mtspr SPRN_ITV0,r0
428 mtspr SPRN_ITV1,r0
429 mtspr SPRN_ITV2,r0
430 mtspr SPRN_ITV3,r0
431 mtspr SPRN_DTV0,r0
432 mtspr SPRN_DTV1,r0
433 mtspr SPRN_DTV2,r0
434 mtspr SPRN_DTV3,r0
wdenk0442ed82002-11-03 10:24:00 +0000435
436 /*----------------------------------------------------------------*/
437 /* Cache victim limits */
438 /*----------------------------------------------------------------*/
439 /* floors 0, ceiling max to use the entire cache -- nothing locked
440 */
441 lis r1,0x0001
442 ori r1,r1,0xf800
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200443 mtspr SPRN_IVLIM,r1
444 mtspr SPRN_DVLIM,r1
wdenk0442ed82002-11-03 10:24:00 +0000445
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200446 /*----------------------------------------------------------------+
447 |Initialize MMUCR[STID] = 0.
448 +-----------------------------------------------------------------*/
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200449 mfspr r0,SPRN_MMUCR
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200450 addis r1,0,0xFFFF
451 ori r1,r1,0xFF00
452 and r0,r0,r1
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200453 mtspr SPRN_MMUCR,r0
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200454
wdenk0442ed82002-11-03 10:24:00 +0000455 /*----------------------------------------------------------------*/
456 /* Clear all TLB entries -- TID = 0, TS = 0 */
457 /*----------------------------------------------------------------*/
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200458 addis r0,0,0x0000
Stefan Roese0a371ca2009-07-14 15:53:08 +0200459#ifdef CONFIG_SYS_RAMBOOT
Stefan Roesed8731332009-05-11 13:46:14 +0200460 li r4,0 /* Start with TLB #0 */
Stefan Roese0a371ca2009-07-14 15:53:08 +0200461#else
462 li r4,1 /* Start with TLB #1 */
463#endif
464 li r1,64 /* 64 TLB entries */
465 sub r1,r1,r4 /* calculate last TLB # */
466 mtctr r1
Stefan Roesed8731332009-05-11 13:46:14 +0200467rsttlb:
468#ifdef CONFIG_SYS_RAMBOOT
469 tlbre r3,r4,0 /* Read contents from TLB word #0 to get EPN */
470 rlwinm. r3,r3,0,0xfffffc00 /* Mask EPN */
471 beq tlbnxt /* Skip EPN=0 TLB, this is the SDRAM TLB */
472#endif
473 tlbwe r0,r4,0 /* Invalidate all entries (V=0)*/
474 tlbwe r0,r4,1
475 tlbwe r0,r4,2
476tlbnxt: addi r4,r4,1 /* Next TLB */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200477 bdnz rsttlb
wdenk0442ed82002-11-03 10:24:00 +0000478
479 /*----------------------------------------------------------------*/
480 /* TLB entry setup -- step thru tlbtab */
481 /*----------------------------------------------------------------*/
Stefan Roese2a72e9e2010-04-09 14:03:59 +0200482#if defined(CONFIG_440SPE_REVA)
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200483 /*----------------------------------------------------------------*/
484 /* We have different TLB tables for revA and rev B of 440SPe */
485 /*----------------------------------------------------------------*/
486 mfspr r1, PVR
487 lis r0,0x5342
488 ori r0,r0,0x1891
489 cmpw r7,r1,r0
490 bne r7,..revA
491 bl tlbtabB
492 b ..goon
493..revA:
494 bl tlbtabA
495..goon:
496#else
wdenk0442ed82002-11-03 10:24:00 +0000497 bl tlbtab /* Get tlbtab pointer */
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200498#endif
wdenk0442ed82002-11-03 10:24:00 +0000499 mr r5,r0
500 li r1,0x003f /* 64 TLB entries max */
501 mtctr r1
502 li r4,0 /* TLB # */
503
504 addi r5,r5,-4
Stefan Roesed8731332009-05-11 13:46:14 +02005051:
506#ifdef CONFIG_SYS_RAMBOOT
507 tlbre r3,r4,0 /* Read contents from TLB word #0 */
508 rlwinm. r3,r3,0,0x00000200 /* Mask V (valid) bit */
509 bne tlbnx2 /* Skip V=1 TLB, this is the SDRAM TLB */
510#endif
511 lwzu r0,4(r5)
wdenk0442ed82002-11-03 10:24:00 +0000512 cmpwi r0,0
513 beq 2f /* 0 marks end */
514 lwzu r1,4(r5)
515 lwzu r2,4(r5)
516 tlbwe r0,r4,0 /* TLB Word 0 */
517 tlbwe r1,r4,1 /* TLB Word 1 */
518 tlbwe r2,r4,2 /* TLB Word 2 */
Stefan Roesed8731332009-05-11 13:46:14 +0200519tlbnx2: addi r4,r4,1 /* Next TLB */
wdenk0442ed82002-11-03 10:24:00 +0000520 bdnz 1b
521
522 /*----------------------------------------------------------------*/
523 /* Continue from 'normal' start */
524 /*----------------------------------------------------------------*/
Stefan Roese887e2ec2006-09-07 11:51:23 +02005252:
Stefan Roese887e2ec2006-09-07 11:51:23 +0200526 bl 3f
wdenk0442ed82002-11-03 10:24:00 +0000527 b _start
528
5293: li r0,0
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200530 mtspr SPRN_SRR1,r0 /* Keep things disabled for now */
wdenk0442ed82002-11-03 10:24:00 +0000531 mflr r1
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200532 mtspr SPRN_SRR0,r1
wdenk0442ed82002-11-03 10:24:00 +0000533 rfi
stroeseb867d702003-05-23 11:18:02 +0000534#endif /* CONFIG_440 */
wdenk0442ed82002-11-03 10:24:00 +0000535
536/*
537 * r3 - 1st arg to board_init(): IMMP pointer
538 * r4 - 2nd arg to board_init(): boot flag
539 */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200540#ifndef CONFIG_NAND_SPL
wdenk0442ed82002-11-03 10:24:00 +0000541 .text
542 .long 0x27051956 /* U-Boot Magic Number */
543 .globl version_string
544version_string:
545 .ascii U_BOOT_VERSION
Peter Tyser561858e2008-11-03 09:30:59 -0600546 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
wdenk0442ed82002-11-03 10:24:00 +0000547 .ascii CONFIG_IDENT_STRING, "\0"
548
wdenk0442ed82002-11-03 10:24:00 +0000549 . = EXC_OFF_SYS_RESET
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200550 .globl _start_of_vectors
551_start_of_vectors:
552
553/* Critical input. */
554 CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
555
556#ifdef CONFIG_440
557/* Machine check */
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +0200558 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200559#else
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +0200560 CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200561#endif /* CONFIG_440 */
562
563/* Data Storage exception. */
564 STD_EXCEPTION(0x300, DataStorage, UnknownException)
565
566/* Instruction Storage exception. */
567 STD_EXCEPTION(0x400, InstStorage, UnknownException)
568
569/* External Interrupt exception. */
570 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
571
572/* Alignment exception. */
573 . = 0x600
574Alignment:
575 EXCEPTION_PROLOG(SRR0, SRR1)
576 mfspr r4,DAR
577 stw r4,_DAR(r21)
578 mfspr r5,DSISR
579 stw r5,_DSISR(r21)
580 addi r3,r1,STACK_FRAME_OVERHEAD
Joakim Tjernlundfc4e1882010-01-19 14:41:55 +0100581 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200582
583/* Program check exception */
584 . = 0x700
585ProgramCheck:
586 EXCEPTION_PROLOG(SRR0, SRR1)
587 addi r3,r1,STACK_FRAME_OVERHEAD
Joakim Tjernlundfc4e1882010-01-19 14:41:55 +0100588 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
589 MSR_KERNEL, COPY_EE)
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200590
591#ifdef CONFIG_440
592 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
593 STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
594 STD_EXCEPTION(0xa00, APU, UnknownException)
Stefan Roesedf8a24c2007-06-19 16:42:31 +0200595#endif
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200596 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
597
598#ifdef CONFIG_440
599 STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
600 STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
601#else
602 STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
603 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
604 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
605#endif
606 CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
607
608 .globl _end_of_vectors
609_end_of_vectors:
610 . = _START_OFFSET
Stefan Roese887e2ec2006-09-07 11:51:23 +0200611#endif
wdenk0442ed82002-11-03 10:24:00 +0000612 .globl _start
613_start:
614
615/*****************************************************************************/
616#if defined(CONFIG_440)
617
618 /*----------------------------------------------------------------*/
619 /* Clear and set up some registers. */
620 /*----------------------------------------------------------------*/
621 li r0,0x0000
622 lis r1,0xffff
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200623 mtspr SPRN_DEC,r0 /* prevent dec exceptions */
624 mtspr SPRN_TBWL,r0 /* prevent fit & wdt exceptions */
625 mtspr SPRN_TBWU,r0
626 mtspr SPRN_TSR,r1 /* clear all timer exception status */
627 mtspr SPRN_TCR,r0 /* disable all */
628 mtspr SPRN_ESR,r0 /* clear exception syndrome register */
wdenk0442ed82002-11-03 10:24:00 +0000629 mtxer r0 /* clear integer exception register */
wdenk0442ed82002-11-03 10:24:00 +0000630
631 /*----------------------------------------------------------------*/
632 /* Debug setup -- some (not very good) ice's need an event*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200633 /* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */
wdenk0442ed82002-11-03 10:24:00 +0000634 /* value you need in this case 0x8cff 0000 should do the trick */
635 /*----------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200636#if defined(CONFIG_SYS_INIT_DBCR)
wdenk0442ed82002-11-03 10:24:00 +0000637 lis r1,0xffff
638 ori r1,r1,0xffff
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200639 mtspr SPRN_DBSR,r1 /* Clear all status bits */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200640 lis r0,CONFIG_SYS_INIT_DBCR@h
641 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200642 mtspr SPRN_DBCR0,r0
wdenk0442ed82002-11-03 10:24:00 +0000643 isync
644#endif
645
646 /*----------------------------------------------------------------*/
647 /* Setup the internal SRAM */
648 /*----------------------------------------------------------------*/
649 li r0,0
Stefan Roese887e2ec2006-09-07 11:51:23 +0200650
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200651#ifdef CONFIG_SYS_INIT_RAM_DCACHE
Stefan Roesec157d8e2005-08-01 16:41:48 +0200652 /* Clear Dcache to use as RAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200653 addis r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h
654 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
655 addis r4,r0,CONFIG_SYS_INIT_RAM_END@h
656 ori r4,r4,CONFIG_SYS_INIT_RAM_END@l
Stefan Roesec157d8e2005-08-01 16:41:48 +0200657 rlwinm. r5,r4,0,27,31
Wolfgang Denkf901a832005-08-06 01:42:58 +0200658 rlwinm r5,r4,27,5,31
659 beq ..d_ran
660 addi r5,r5,0x0001
Stefan Roesec157d8e2005-08-01 16:41:48 +0200661..d_ran:
Wolfgang Denkf901a832005-08-06 01:42:58 +0200662 mtctr r5
Stefan Roesec157d8e2005-08-01 16:41:48 +0200663..d_ag:
Wolfgang Denkf901a832005-08-06 01:42:58 +0200664 dcbz r0,r3
665 addi r3,r3,32
666 bdnz ..d_ag
Stefan Roesee02c5212008-01-09 10:23:16 +0100667
668 /*
669 * Lock the init-ram/stack in d-cache, so that other regions
670 * may use d-cache as well
671 * Note, that this current implementation locks exactly 4k
672 * of d-cache, so please make sure that you don't define a
673 * bigger init-ram area. Take a look at the lwmon5 440EPx
674 * implementation as a reference.
675 */
676 msync
677 isync
678 /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
679 lis r1,0x0201
680 ori r1,r1,0xf808
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200681 mtspr SPRN_DVLIM,r1
Stefan Roesee02c5212008-01-09 10:23:16 +0100682 lis r1,0x0808
683 ori r1,r1,0x0808
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200684 mtspr SPRN_DNV0,r1
685 mtspr SPRN_DNV1,r1
686 mtspr SPRN_DNV2,r1
687 mtspr SPRN_DNV3,r1
688 mtspr SPRN_DTV0,r1
689 mtspr SPRN_DTV1,r1
690 mtspr SPRN_DTV2,r1
691 mtspr SPRN_DTV3,r1
Stefan Roesee02c5212008-01-09 10:23:16 +0100692 msync
693 isync
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200694#endif /* CONFIG_SYS_INIT_RAM_DCACHE */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200695
696 /* 440EP & 440GR are only 440er PPC's without internal SRAM */
697#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
698 /* not all PPC's have internal SRAM usable as L2-cache */
Stefan Roese2801b2d2008-03-11 15:05:50 +0100699#if defined(CONFIG_440GX) || \
700 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
Feng Kan7d307932008-07-08 22:47:31 -0700701 defined(CONFIG_460SX)
Dave Mitchellb14ca4b2008-11-20 14:00:49 -0600702 mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */
Dave Mitchellddf45cc2008-11-20 14:09:50 -0600703#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
704 lis r1, 0x0000
705 ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */
706 mtdcr L2_CACHE_CFG,r1
wdenkba56f622004-02-06 23:19:44 +0000707#endif
wdenk0442ed82002-11-03 10:24:00 +0000708
Stefan Roese887e2ec2006-09-07 11:51:23 +0200709 lis r2,0x7fff
wdenk0442ed82002-11-03 10:24:00 +0000710 ori r2,r2,0xffff
Dave Mitchellb14ca4b2008-11-20 14:00:49 -0600711 mfdcr r1,ISRAM0_DPC
wdenk0442ed82002-11-03 10:24:00 +0000712 and r1,r1,r2 /* Disable parity check */
Dave Mitchellb14ca4b2008-11-20 14:00:49 -0600713 mtdcr ISRAM0_DPC,r1
714 mfdcr r1,ISRAM0_PMEG
Stefan Roese887e2ec2006-09-07 11:51:23 +0200715 and r1,r1,r2 /* Disable pwr mgmt */
Dave Mitchellb14ca4b2008-11-20 14:00:49 -0600716 mtdcr ISRAM0_PMEG,r1
wdenk0442ed82002-11-03 10:24:00 +0000717
718 lis r1,0x8000 /* BAS = 8000_0000 */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100719#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
wdenkba56f622004-02-06 23:19:44 +0000720 ori r1,r1,0x0980 /* first 64k */
Dave Mitchellb14ca4b2008-11-20 14:00:49 -0600721 mtdcr ISRAM0_SB0CR,r1
wdenkba56f622004-02-06 23:19:44 +0000722 lis r1,0x8001
723 ori r1,r1,0x0980 /* second 64k */
Dave Mitchellb14ca4b2008-11-20 14:00:49 -0600724 mtdcr ISRAM0_SB1CR,r1
wdenkba56f622004-02-06 23:19:44 +0000725 lis r1, 0x8002
726 ori r1,r1, 0x0980 /* third 64k */
Dave Mitchellb14ca4b2008-11-20 14:00:49 -0600727 mtdcr ISRAM0_SB2CR,r1
wdenkba56f622004-02-06 23:19:44 +0000728 lis r1, 0x8003
729 ori r1,r1, 0x0980 /* fourth 64k */
Dave Mitchellb14ca4b2008-11-20 14:00:49 -0600730 mtdcr ISRAM0_SB3CR,r1
Dave Mitchellddf45cc2008-11-20 14:09:50 -0600731#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT)
732 lis r1,0x0000 /* BAS = X_0000_0000 */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200733 ori r1,r1,0x0984 /* first 64k */
Dave Mitchellb14ca4b2008-11-20 14:00:49 -0600734 mtdcr ISRAM0_SB0CR,r1
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200735 lis r1,0x0001
736 ori r1,r1,0x0984 /* second 64k */
Dave Mitchellb14ca4b2008-11-20 14:00:49 -0600737 mtdcr ISRAM0_SB1CR,r1
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200738 lis r1, 0x0002
739 ori r1,r1, 0x0984 /* third 64k */
Dave Mitchellb14ca4b2008-11-20 14:00:49 -0600740 mtdcr ISRAM0_SB2CR,r1
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200741 lis r1, 0x0003
742 ori r1,r1, 0x0984 /* fourth 64k */
Dave Mitchellb14ca4b2008-11-20 14:00:49 -0600743 mtdcr ISRAM0_SB3CR,r1
Dave Mitchellddf45cc2008-11-20 14:09:50 -0600744#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
745 lis r2,0x7fff
746 ori r2,r2,0xffff
747 mfdcr r1,ISRAM1_DPC
748 and r1,r1,r2 /* Disable parity check */
Wolfgang Denk455ae7e2008-12-16 01:02:17 +0100749 mtdcr ISRAM1_DPC,r1
Dave Mitchellddf45cc2008-11-20 14:09:50 -0600750 mfdcr r1,ISRAM1_PMEG
751 and r1,r1,r2 /* Disable pwr mgmt */
752 mtdcr ISRAM1_PMEG,r1
753
754 lis r1,0x0004 /* BAS = 4_0004_0000 */
755 ori r1,r1,0x0984 /* 64k */
756 mtdcr ISRAM1_SB0CR,r1
757#endif
Feng Kan7d307932008-07-08 22:47:31 -0700758#elif defined(CONFIG_460SX)
759 lis r1,0x0000 /* BAS = 0000_0000 */
760 ori r1,r1,0x0B84 /* first 128k */
Dave Mitchellb14ca4b2008-11-20 14:00:49 -0600761 mtdcr ISRAM0_SB0CR,r1
Feng Kan7d307932008-07-08 22:47:31 -0700762 lis r1,0x0001
763 ori r1,r1,0x0B84 /* second 128k */
Dave Mitchellb14ca4b2008-11-20 14:00:49 -0600764 mtdcr ISRAM0_SB1CR,r1
Feng Kan7d307932008-07-08 22:47:31 -0700765 lis r1, 0x0002
766 ori r1,r1, 0x0B84 /* third 128k */
Dave Mitchellb14ca4b2008-11-20 14:00:49 -0600767 mtdcr ISRAM0_SB2CR,r1
Feng Kan7d307932008-07-08 22:47:31 -0700768 lis r1, 0x0003
769 ori r1,r1, 0x0B84 /* fourth 128k */
Dave Mitchellb14ca4b2008-11-20 14:00:49 -0600770 mtdcr ISRAM0_SB3CR,r1
Stefan Roese887e2ec2006-09-07 11:51:23 +0200771#elif defined(CONFIG_440GP)
wdenk0442ed82002-11-03 10:24:00 +0000772 ori r1,r1,0x0380 /* 8k rw */
Dave Mitchellb14ca4b2008-11-20 14:00:49 -0600773 mtdcr ISRAM0_SB0CR,r1
774 mtdcr ISRAM0_SB1CR,r0 /* Disable bank 1 */
wdenkba56f622004-02-06 23:19:44 +0000775#endif
Stefan Roese887e2ec2006-09-07 11:51:23 +0200776#endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
wdenk0442ed82002-11-03 10:24:00 +0000777
778 /*----------------------------------------------------------------*/
779 /* Setup the stack in internal SRAM */
780 /*----------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200781 lis r1,CONFIG_SYS_INIT_RAM_ADDR@h
782 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
wdenk0442ed82002-11-03 10:24:00 +0000783 li r0,0
784 stwu r0,-4(r1)
785 stwu r0,-4(r1) /* Terminate call chain */
786
787 stwu r1,-8(r1) /* Save back chain and move SP */
788 lis r0,RESET_VECTOR@h /* Address of reset vector */
789 ori r0,r0, RESET_VECTOR@l
790 stwu r1,-8(r1) /* Save back chain and move SP */
791 stw r0,+12(r1) /* Save return addr (underflow vect) */
792
Stefan Roese887e2ec2006-09-07 11:51:23 +0200793#ifdef CONFIG_NAND_SPL
Stefan Roese64852d02008-06-02 14:35:44 +0200794 bl nand_boot_common /* will not return */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200795#else
wdenk0442ed82002-11-03 10:24:00 +0000796 GET_GOT
Stefan Roese5568e612005-11-22 13:20:42 +0100797
798 bl cpu_init_f /* run low-level CPU init code (from Flash) */
wdenk0442ed82002-11-03 10:24:00 +0000799 bl board_init_f
Stefan Roese887e2ec2006-09-07 11:51:23 +0200800#endif
wdenk0442ed82002-11-03 10:24:00 +0000801
802#endif /* CONFIG_440 */
803
804/*****************************************************************************/
805#ifdef CONFIG_IOP480
806 /*----------------------------------------------------------------------- */
807 /* Set up some machine state registers. */
808 /*----------------------------------------------------------------------- */
809 addi r0,r0,0x0000 /* initialize r0 to zero */
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200810 mtspr SPRN_ESR,r0 /* clear Exception Syndrome Reg */
wdenk0442ed82002-11-03 10:24:00 +0000811 mttcr r0 /* timer control register */
812 mtexier r0 /* disable all interrupts */
wdenk0442ed82002-11-03 10:24:00 +0000813 addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */
814 ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */
815 mtdbsr r4 /* clear/reset the dbsr */
816 mtexisr r4 /* clear all pending interrupts */
817 addis r4,r0,0x8000
818 mtexier r4 /* enable critical exceptions */
819 addis r4,r0,0x0000 /* assume 403GCX - enable core clk */
820 ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */
821 mtiocr r4 /* since bit not used) & DRC to latch */
822 /* data bus on rising edge of CAS */
823 /*----------------------------------------------------------------------- */
824 /* Clear XER. */
825 /*----------------------------------------------------------------------- */
826 mtxer r0
827 /*----------------------------------------------------------------------- */
828 /* Invalidate i-cache and d-cache TAG arrays. */
829 /*----------------------------------------------------------------------- */
830 addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */
831 addi r4,0,1024 /* 1/4 of I-cache */
832..cloop:
833 iccci 0,r3
834 iccci r4,r3
835 dccci 0,r3
836 addic. r3,r3,-16 /* move back one cache line */
837 bne ..cloop /* loop back to do rest until r3 = 0 */
838
839 /* */
840 /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */
841 /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */
842 /* */
843
844 /* first copy IOP480 register base address into r3 */
845 addis r3,0,0x5000 /* IOP480 register base address hi */
846/* ori r3,r3,0x0000 / IOP480 register base address lo */
847
848#ifdef CONFIG_ADCIOP
849 /* use r4 as the working variable */
850 /* turn on CS3 (LOCCTL.7) */
851 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
852 andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */
853 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
854#endif
855
856#ifdef CONFIG_DASA_SIM
857 /* use r4 as the working variable */
858 /* turn on MA17 (LOCCTL.7) */
859 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
860 ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */
861 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
862#endif
863
864 /* turn on MA16..13 (LCS0BRD.12 = 0) */
865 lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
866 andi. r4,r4,0xefff /* make bit 12 = 0 */
867 stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
868
869 /* make sure above stores all comlete before going on */
870 sync
871
872 /* last thing, set local init status done bit (DEVINIT.31) */
873 lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */
874 oris r4,r4,0x8000 /* make bit 31 = 1 */
875 stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */
876
877 /* clear all pending interrupts and disable all interrupts */
878 li r4,-1 /* set p1 to 0xffffffff */
879 stw r4,0x1b0(r3) /* clear all pending interrupts */
880 stw r4,0x1b8(r3) /* clear all pending interrupts */
881 li r4,0 /* set r4 to 0 */
882 stw r4,0x1b4(r3) /* disable all interrupts */
883 stw r4,0x1bc(r3) /* disable all interrupts */
884
885 /* make sure above stores all comlete before going on */
886 sync
887
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700888 /* Set-up icache cacheability. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200889 lis r1, CONFIG_SYS_ICACHE_SACR_VALUE@h
890 ori r1, r1, CONFIG_SYS_ICACHE_SACR_VALUE@l
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700891 mticcr r1
892 isync
wdenk0442ed82002-11-03 10:24:00 +0000893
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700894 /* Set-up dcache cacheability. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200895 lis r1, CONFIG_SYS_DCACHE_SACR_VALUE@h
896 ori r1, r1, CONFIG_SYS_DCACHE_SACR_VALUE@l
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700897 mtdccr r1
wdenk0442ed82002-11-03 10:24:00 +0000898
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200899 addis r1,r0,CONFIG_SYS_INIT_RAM_ADDR@h
900 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack to SDRAM */
wdenk0442ed82002-11-03 10:24:00 +0000901 li r0, 0 /* Make room for stack frame header and */
902 stwu r0, -4(r1) /* clear final stack frame so that */
903 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
904
905 GET_GOT /* initialize GOT access */
906
907 bl board_init_f /* run first part of init code (from Flash) */
908
909#endif /* CONFIG_IOP480 */
910
911/*****************************************************************************/
Stefan Roesee01bd212007-03-21 13:38:59 +0100912#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
913 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200914 defined(CONFIG_405EX) || defined(CONFIG_405)
wdenk0442ed82002-11-03 10:24:00 +0000915 /*----------------------------------------------------------------------- */
916 /* Clear and set up some registers. */
917 /*----------------------------------------------------------------------- */
918 addi r4,r0,0x0000
Stefan Roesedbbd1252007-10-05 17:10:59 +0200919#if !defined(CONFIG_405EX)
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200920 mtspr SPRN_SGR,r4
Stefan Roesedbbd1252007-10-05 17:10:59 +0200921#else
922 /*
923 * On 405EX, completely clearing the SGR leads to PPC hangup
924 * upon PCIe configuration access. The PCIe memory regions
925 * need to be guarded!
926 */
927 lis r3,0x0000
928 ori r3,r3,0x7FFC
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200929 mtspr SPRN_SGR,r3
Stefan Roesedbbd1252007-10-05 17:10:59 +0200930#endif
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200931 mtspr SPRN_DCWR,r4
wdenk0442ed82002-11-03 10:24:00 +0000932 mtesr r4 /* clear Exception Syndrome Reg */
933 mttcr r4 /* clear Timer Control Reg */
934 mtxer r4 /* clear Fixed-Point Exception Reg */
935 mtevpr r4 /* clear Exception Vector Prefix Reg */
wdenk0442ed82002-11-03 10:24:00 +0000936 addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
937 /* dbsr is cleared by setting bits to 1) */
938 mtdbsr r4 /* clear/reset the dbsr */
939
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700940 /* Invalidate the i- and d-caches. */
wdenk0442ed82002-11-03 10:24:00 +0000941 bl invalidate_icache
942 bl invalidate_dcache
943
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700944 /* Set-up icache cacheability. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200945 lis r4, CONFIG_SYS_ICACHE_SACR_VALUE@h
946 ori r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700947 mticcr r4
wdenk0442ed82002-11-03 10:24:00 +0000948 isync
949
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700950 /* Set-up dcache cacheability. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200951 lis r4, CONFIG_SYS_DCACHE_SACR_VALUE@h
952 ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700953 mtdccr r4
wdenk0442ed82002-11-03 10:24:00 +0000954
Ricardo Ribalda Delgado1f4d5322008-10-21 18:29:46 +0200955#if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\
956 && !defined (CONFIG_XILINX_405)
wdenk0442ed82002-11-03 10:24:00 +0000957 /*----------------------------------------------------------------------- */
958 /* Tune the speed and size for flash CS0 */
959 /*----------------------------------------------------------------------- */
960 bl ext_bus_cntlr_init
961#endif
Stefan Roese64852d02008-06-02 14:35:44 +0200962
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200963#if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM))
Stefan Roesedbbd1252007-10-05 17:10:59 +0200964 /*
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700965 * For boards that don't have OCM and can't use the data cache
966 * for their primordial stack, setup stack here directly after the
967 * SDRAM is initialized in ext_bus_cntlr_init.
Stefan Roesedbbd1252007-10-05 17:10:59 +0200968 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200969 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
970 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in SDRAM */
Stefan Roesedbbd1252007-10-05 17:10:59 +0200971
972 li r0, 0 /* Make room for stack frame header and */
973 stwu r0, -4(r1) /* clear final stack frame so that */
974 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
975 /*
976 * Set up a dummy frame to store reset vector as return address.
977 * this causes stack underflow to reset board.
978 */
979 stwu r1, -8(r1) /* Save back chain and move SP */
980 lis r0, RESET_VECTOR@h /* Address of reset vector */
981 ori r0, r0, RESET_VECTOR@l
982 stwu r1, -8(r1) /* Save back chain and move SP */
983 stw r0, +12(r1) /* Save return addr (underflow vect) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200984#endif /* !(CONFIG_SYS_INIT_DCACHE_CS || !CONFIG_SYS_TEM_STACK_OCM) */
wdenk0442ed82002-11-03 10:24:00 +0000985
stroeseb867d702003-05-23 11:18:02 +0000986#if defined(CONFIG_405EP)
987 /*----------------------------------------------------------------------- */
988 /* DMA Status, clear to come up clean */
989 /*----------------------------------------------------------------------- */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200990 addis r3,r0, 0xFFFF /* Clear all existing DMA status */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200991 ori r3,r3, 0xFFFF
Stefan Roesed1c3b272009-09-09 16:25:29 +0200992 mtdcr DMASR, r3
stroeseb867d702003-05-23 11:18:02 +0000993
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200994 bl ppc405ep_init /* do ppc405ep specific init */
stroeseb867d702003-05-23 11:18:02 +0000995#endif /* CONFIG_405EP */
996
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200997#if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)
Stefan Roesee01bd212007-03-21 13:38:59 +0100998#if defined(CONFIG_405EZ)
999 /********************************************************************
1000 * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
1001 *******************************************************************/
1002 /*
1003 * We can map the OCM on the PLB3, so map it at
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001004 * CONFIG_SYS_OCM_DATA_ADDR + 0x8000
Stefan Roesee01bd212007-03-21 13:38:59 +01001005 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001006 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1007 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
Stefan Roesedf8a24c2007-06-19 16:42:31 +02001008 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001009 mtdcr OCM0_PLBCR1,r3 /* Set PLB Access */
Stefan Roesee01bd212007-03-21 13:38:59 +01001010 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001011 mtdcr OCM0_PLBCR2,r3 /* Set PLB Access */
Stefan Roesee01bd212007-03-21 13:38:59 +01001012 isync
1013
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001014 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1015 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001016 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001017 mtdcr OCM0_DSRC1, r3 /* Set Data Side */
1018 mtdcr OCM0_ISRC1, r3 /* Set Instruction Side */
Stefan Roesee01bd212007-03-21 13:38:59 +01001019 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001020 mtdcr OCM0_DSRC2, r3 /* Set Data Side */
1021 mtdcr OCM0_ISRC2, r3 /* Set Instruction Side */
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001022 addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001023 mtdcr OCM0_DISDPC,r3
Stefan Roesee01bd212007-03-21 13:38:59 +01001024
1025 isync
Stefan Roese3cb86f32007-03-24 15:45:34 +01001026#else /* CONFIG_405EZ */
wdenk0442ed82002-11-03 10:24:00 +00001027 /********************************************************************
1028 * Setup OCM - On Chip Memory
1029 *******************************************************************/
1030 /* Setup OCM */
wdenk8bde7f72003-06-27 21:31:46 +00001031 lis r0, 0x7FFF
1032 ori r0, r0, 0xFFFF
Stefan Roesed1c3b272009-09-09 16:25:29 +02001033 mfdcr r3, OCM0_ISCNTL /* get instr-side IRAM config */
1034 mfdcr r4, OCM0_DSCNTL /* get data-side IRAM config */
Stefan Roese3cb86f32007-03-24 15:45:34 +01001035 and r3, r3, r0 /* disable data-side IRAM */
1036 and r4, r4, r0 /* disable data-side IRAM */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001037 mtdcr OCM0_ISCNTL, r3 /* set instr-side IRAM config */
1038 mtdcr OCM0_DSCNTL, r4 /* set data-side IRAM config */
wdenk8bde7f72003-06-27 21:31:46 +00001039 isync
wdenk0442ed82002-11-03 10:24:00 +00001040
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001041 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1042 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
Stefan Roesed1c3b272009-09-09 16:25:29 +02001043 mtdcr OCM0_DSARC, r3
wdenk0442ed82002-11-03 10:24:00 +00001044 addis r4, 0, 0xC000 /* OCM data area enabled */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001045 mtdcr OCM0_DSCNTL, r4
wdenk8bde7f72003-06-27 21:31:46 +00001046 isync
Stefan Roesee01bd212007-03-21 13:38:59 +01001047#endif /* CONFIG_405EZ */
wdenk0442ed82002-11-03 10:24:00 +00001048#endif
1049
1050 /*----------------------------------------------------------------------- */
1051 /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
1052 /*----------------------------------------------------------------------- */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001053#ifdef CONFIG_SYS_INIT_DCACHE_CS
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001054 li r4, PBxAP
Stefan Roesed1c3b272009-09-09 16:25:29 +02001055 mtdcr EBC0_CFGADDR, r4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001056 lis r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h
1057 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l
Stefan Roesed1c3b272009-09-09 16:25:29 +02001058 mtdcr EBC0_CFGDATA, r4
wdenk0442ed82002-11-03 10:24:00 +00001059
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001060 addi r4, 0, PBxCR
Stefan Roesed1c3b272009-09-09 16:25:29 +02001061 mtdcr EBC0_CFGADDR, r4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001062 lis r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h
1063 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l
Stefan Roesed1c3b272009-09-09 16:25:29 +02001064 mtdcr EBC0_CFGDATA, r4
wdenk0442ed82002-11-03 10:24:00 +00001065
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001066 /*
1067 * Enable the data cache for the 128MB storage access control region
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001068 * at CONFIG_SYS_INIT_RAM_ADDR.
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001069 */
1070 mfdccr r4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001071 oris r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
1072 ori r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
wdenk0442ed82002-11-03 10:24:00 +00001073 mtdccr r4
1074
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001075 /*
1076 * Preallocate data cache lines to be used to avoid a subsequent
1077 * cache miss and an ensuing machine check exception when exceptions
1078 * are enabled.
1079 */
1080 li r0, 0
wdenk0442ed82002-11-03 10:24:00 +00001081
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001082 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
1083 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
wdenk0442ed82002-11-03 10:24:00 +00001084
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001085 lis r4, CONFIG_SYS_INIT_RAM_END@h
1086 ori r4, r4, CONFIG_SYS_INIT_RAM_END@l
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001087
1088 /*
1089 * Convert the size, in bytes, to the number of cache lines/blocks
1090 * to preallocate.
1091 */
1092 clrlwi. r5, r4, (32 - L1_CACHE_SHIFT)
1093 srwi r5, r4, L1_CACHE_SHIFT
1094 beq ..load_counter
1095 addi r5, r5, 0x0001
1096..load_counter:
1097 mtctr r5
1098
1099 /* Preallocate the computed number of cache blocks. */
1100..alloc_dcache_block:
1101 dcba r0, r3
1102 addi r3, r3, L1_CACHE_BYTES
1103 bdnz ..alloc_dcache_block
1104 sync
1105
1106 /*
1107 * Load the initial stack pointer and data area and convert the size,
1108 * in bytes, to the number of words to initialize to a known value.
1109 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001110 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
1111 ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001112
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001113 lis r4, (CONFIG_SYS_INIT_RAM_END >> 2)@h
1114 ori r4, r4, (CONFIG_SYS_INIT_RAM_END >> 2)@l
wdenk0442ed82002-11-03 10:24:00 +00001115 mtctr r4
1116
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001117 lis r2, CONFIG_SYS_INIT_RAM_ADDR@h
1118 ori r2, r2, CONFIG_SYS_INIT_RAM_END@l
wdenk0442ed82002-11-03 10:24:00 +00001119
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001120 lis r4, CONFIG_SYS_INIT_RAM_PATTERN@h
1121 ori r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l
wdenk0442ed82002-11-03 10:24:00 +00001122
1123..stackloop:
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001124 stwu r4, -4(r2)
wdenk0442ed82002-11-03 10:24:00 +00001125 bdnz ..stackloop
1126
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001127 /*
1128 * Make room for stack frame header and clear final stack frame so
1129 * that stack backtraces terminate cleanly.
1130 */
1131 stwu r0, -4(r1)
1132 stwu r0, -4(r1)
1133
wdenk0442ed82002-11-03 10:24:00 +00001134 /*
1135 * Set up a dummy frame to store reset vector as return address.
1136 * this causes stack underflow to reset board.
1137 */
1138 stwu r1, -8(r1) /* Save back chain and move SP */
1139 addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
1140 ori r0, r0, RESET_VECTOR@l
1141 stwu r1, -8(r1) /* Save back chain and move SP */
1142 stw r0, +12(r1) /* Save return addr (underflow vect) */
1143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001144#elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \
1145 (defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE))
wdenk0442ed82002-11-03 10:24:00 +00001146 /*
1147 * Stack in OCM.
1148 */
1149
1150 /* Set up Stack at top of OCM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001151 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@h
1152 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@l
wdenk0442ed82002-11-03 10:24:00 +00001153
1154 /* Set up a zeroized stack frame so that backtrace works right */
1155 li r0, 0
1156 stwu r0, -4(r1)
1157 stwu r0, -4(r1)
1158
1159 /*
1160 * Set up a dummy frame to store reset vector as return address.
1161 * this causes stack underflow to reset board.
1162 */
1163 stwu r1, -8(r1) /* Save back chain and move SP */
1164 lis r0, RESET_VECTOR@h /* Address of reset vector */
1165 ori r0, r0, RESET_VECTOR@l
1166 stwu r1, -8(r1) /* Save back chain and move SP */
1167 stw r0, +12(r1) /* Save return addr (underflow vect) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001168#endif /* CONFIG_SYS_INIT_DCACHE_CS */
wdenk0442ed82002-11-03 10:24:00 +00001169
Stefan Roesec440bfe2007-06-06 11:42:13 +02001170#ifdef CONFIG_NAND_SPL
Stefan Roese64852d02008-06-02 14:35:44 +02001171 bl nand_boot_common /* will not return */
Stefan Roesec440bfe2007-06-06 11:42:13 +02001172#else
wdenk0442ed82002-11-03 10:24:00 +00001173 GET_GOT /* initialize GOT access */
1174
Wolfgang Denkf901a832005-08-06 01:42:58 +02001175 bl cpu_init_f /* run low-level CPU init code (from Flash) */
wdenk0442ed82002-11-03 10:24:00 +00001176
1177 /* NEVER RETURNS! */
1178 bl board_init_f /* run first part of init code (from Flash) */
Stefan Roesec440bfe2007-06-06 11:42:13 +02001179#endif /* CONFIG_NAND_SPL */
wdenk0442ed82002-11-03 10:24:00 +00001180
wdenk12f34242003-09-02 22:48:03 +00001181#endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
1182 /*----------------------------------------------------------------------- */
wdenk0442ed82002-11-03 10:24:00 +00001183
1184
Stefan Roese887e2ec2006-09-07 11:51:23 +02001185#ifndef CONFIG_NAND_SPL
wdenk0442ed82002-11-03 10:24:00 +00001186/*
1187 * This code finishes saving the registers to the exception frame
1188 * and jumps to the appropriate handler for the exception.
1189 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1190 */
1191 .globl transfer_to_handler
1192transfer_to_handler:
1193 stw r22,_NIP(r21)
1194 lis r22,MSR_POW@h
1195 andc r23,r23,r22
1196 stw r23,_MSR(r21)
1197 SAVE_GPR(7, r21)
1198 SAVE_4GPRS(8, r21)
1199 SAVE_8GPRS(12, r21)
1200 SAVE_8GPRS(24, r21)
wdenk0442ed82002-11-03 10:24:00 +00001201 mflr r23
1202 andi. r24,r23,0x3f00 /* get vector offset */
1203 stw r24,TRAP(r21)
1204 li r22,0
1205 stw r22,RESULT(r21)
1206 mtspr SPRG2,r22 /* r1 is now kernel sp */
wdenk0442ed82002-11-03 10:24:00 +00001207 lwz r24,0(r23) /* virtual address of handler */
1208 lwz r23,4(r23) /* where to go when done */
1209 mtspr SRR0,r24
1210 mtspr SRR1,r20
1211 mtlr r23
1212 SYNC
1213 rfi /* jump to handler, enable MMU */
1214
1215int_return:
1216 mfmsr r28 /* Disable interrupts */
1217 li r4,0
1218 ori r4,r4,MSR_EE
1219 andc r28,r28,r4
1220 SYNC /* Some chip revs need this... */
1221 mtmsr r28
1222 SYNC
1223 lwz r2,_CTR(r1)
1224 lwz r0,_LINK(r1)
1225 mtctr r2
1226 mtlr r0
1227 lwz r2,_XER(r1)
1228 lwz r0,_CCR(r1)
1229 mtspr XER,r2
1230 mtcrf 0xFF,r0
1231 REST_10GPRS(3, r1)
1232 REST_10GPRS(13, r1)
1233 REST_8GPRS(23, r1)
1234 REST_GPR(31, r1)
1235 lwz r2,_NIP(r1) /* Restore environment */
1236 lwz r0,_MSR(r1)
1237 mtspr SRR0,r2
1238 mtspr SRR1,r0
1239 lwz r0,GPR0(r1)
1240 lwz r2,GPR2(r1)
1241 lwz r1,GPR1(r1)
1242 SYNC
1243 rfi
1244
1245crit_return:
1246 mfmsr r28 /* Disable interrupts */
1247 li r4,0
1248 ori r4,r4,MSR_EE
1249 andc r28,r28,r4
1250 SYNC /* Some chip revs need this... */
1251 mtmsr r28
1252 SYNC
1253 lwz r2,_CTR(r1)
1254 lwz r0,_LINK(r1)
1255 mtctr r2
1256 mtlr r0
1257 lwz r2,_XER(r1)
1258 lwz r0,_CCR(r1)
1259 mtspr XER,r2
1260 mtcrf 0xFF,r0
1261 REST_10GPRS(3, r1)
1262 REST_10GPRS(13, r1)
1263 REST_8GPRS(23, r1)
1264 REST_GPR(31, r1)
1265 lwz r2,_NIP(r1) /* Restore environment */
1266 lwz r0,_MSR(r1)
Matthias Fuchs58ea1422009-07-22 17:27:56 +02001267 mtspr SPRN_CSRR0,r2
1268 mtspr SPRN_CSRR1,r0
wdenk0442ed82002-11-03 10:24:00 +00001269 lwz r0,GPR0(r1)
1270 lwz r2,GPR2(r1)
1271 lwz r1,GPR1(r1)
1272 SYNC
1273 rfci
1274
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001275#ifdef CONFIG_440
1276mck_return:
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001277 mfmsr r28 /* Disable interrupts */
1278 li r4,0
1279 ori r4,r4,MSR_EE
1280 andc r28,r28,r4
1281 SYNC /* Some chip revs need this... */
1282 mtmsr r28
1283 SYNC
1284 lwz r2,_CTR(r1)
1285 lwz r0,_LINK(r1)
1286 mtctr r2
1287 mtlr r0
1288 lwz r2,_XER(r1)
1289 lwz r0,_CCR(r1)
1290 mtspr XER,r2
1291 mtcrf 0xFF,r0
1292 REST_10GPRS(3, r1)
1293 REST_10GPRS(13, r1)
1294 REST_8GPRS(23, r1)
1295 REST_GPR(31, r1)
1296 lwz r2,_NIP(r1) /* Restore environment */
1297 lwz r0,_MSR(r1)
Matthias Fuchs58ea1422009-07-22 17:27:56 +02001298 mtspr SPRN_MCSRR0,r2
1299 mtspr SPRN_MCSRR1,r0
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001300 lwz r0,GPR0(r1)
1301 lwz r2,GPR2(r1)
1302 lwz r1,GPR1(r1)
1303 SYNC
1304 rfmci
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001305#endif /* CONFIG_440 */
1306
1307
wdenk0442ed82002-11-03 10:24:00 +00001308 .globl get_pvr
1309get_pvr:
1310 mfspr r3, PVR
1311 blr
1312
wdenk0442ed82002-11-03 10:24:00 +00001313/*------------------------------------------------------------------------------- */
wdenk0442ed82002-11-03 10:24:00 +00001314/* Function: out16 */
1315/* Description: Output 16 bits */
1316/*------------------------------------------------------------------------------- */
1317 .globl out16
1318out16:
1319 sth r4,0x0000(r3)
1320 blr
1321
1322/*------------------------------------------------------------------------------- */
1323/* Function: out16r */
1324/* Description: Byte reverse and output 16 bits */
1325/*------------------------------------------------------------------------------- */
1326 .globl out16r
1327out16r:
1328 sthbrx r4,r0,r3
1329 blr
1330
1331/*------------------------------------------------------------------------------- */
wdenk0442ed82002-11-03 10:24:00 +00001332/* Function: out32r */
1333/* Description: Byte reverse and output 32 bits */
1334/*------------------------------------------------------------------------------- */
1335 .globl out32r
1336out32r:
1337 stwbrx r4,r0,r3
1338 blr
1339
1340/*------------------------------------------------------------------------------- */
1341/* Function: in16 */
1342/* Description: Input 16 bits */
1343/*------------------------------------------------------------------------------- */
1344 .globl in16
1345in16:
1346 lhz r3,0x0000(r3)
1347 blr
1348
1349/*------------------------------------------------------------------------------- */
1350/* Function: in16r */
1351/* Description: Input 16 bits and byte reverse */
1352/*------------------------------------------------------------------------------- */
1353 .globl in16r
1354in16r:
1355 lhbrx r3,r0,r3
1356 blr
1357
1358/*------------------------------------------------------------------------------- */
wdenk0442ed82002-11-03 10:24:00 +00001359/* Function: in32r */
1360/* Description: Input 32 bits and byte reverse */
1361/*------------------------------------------------------------------------------- */
1362 .globl in32r
1363in32r:
1364 lwbrx r3,r0,r3
1365 blr
1366
wdenk0442ed82002-11-03 10:24:00 +00001367/*
1368 * void relocate_code (addr_sp, gd, addr_moni)
1369 *
1370 * This "function" does not return, instead it continues in RAM
1371 * after relocating the monitor code.
1372 *
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001373 * r3 = Relocated stack pointer
1374 * r4 = Relocated global data pointer
1375 * r5 = Relocated text pointer
wdenk0442ed82002-11-03 10:24:00 +00001376 */
1377 .globl relocate_code
1378relocate_code:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001379#if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS)
Stefan Roese9b94ac62007-10-31 17:55:58 +01001380 /*
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001381 * We need to flush the initial global data (gd_t) before the dcache
1382 * will be invalidated.
Stefan Roese9b94ac62007-10-31 17:55:58 +01001383 */
1384
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001385 /* Save registers */
1386 mr r9, r3
1387 mr r10, r4
1388 mr r11, r5
Stefan Roese9b94ac62007-10-31 17:55:58 +01001389
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001390 /* Flush initial global data range */
1391 mr r3, r4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001392 addi r4, r4, CONFIG_SYS_GBL_DATA_SIZE@l
Stefan Roese9b94ac62007-10-31 17:55:58 +01001393 bl flush_dcache_range
1394
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001395#if defined(CONFIG_SYS_INIT_DCACHE_CS)
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001396 /*
1397 * Undo the earlier data cache set-up for the primordial stack and
1398 * data area. First, invalidate the data cache and then disable data
1399 * cacheability for that area. Finally, restore the EBC values, if
1400 * any.
1401 */
1402
1403 /* Invalidate the primordial stack and data area in cache */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001404 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
1405 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001406
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001407 lis r4, CONFIG_SYS_INIT_RAM_END@h
1408 ori r4, r4, CONFIG_SYS_INIT_RAM_END@l
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001409 add r4, r4, r3
1410
1411 bl invalidate_dcache_range
1412
1413 /* Disable cacheability for the region */
1414 mfdccr r3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001415 lis r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
1416 ori r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001417 and r3, r3, r4
1418 mtdccr r3
1419
1420 /* Restore the EBC parameters */
1421 li r3, PBxAP
Stefan Roesed1c3b272009-09-09 16:25:29 +02001422 mtdcr EBC0_CFGADDR, r3
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001423 lis r3, PBxAP_VAL@h
1424 ori r3, r3, PBxAP_VAL@l
Stefan Roesed1c3b272009-09-09 16:25:29 +02001425 mtdcr EBC0_CFGDATA, r3
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001426
1427 li r3, PBxCR
Stefan Roesed1c3b272009-09-09 16:25:29 +02001428 mtdcr EBC0_CFGADDR, r3
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001429 lis r3, PBxCR_VAL@h
1430 ori r3, r3, PBxCR_VAL@l
Stefan Roesed1c3b272009-09-09 16:25:29 +02001431 mtdcr EBC0_CFGDATA, r3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001432#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001433
1434 /* Restore registers */
1435 mr r3, r9
1436 mr r4, r10
1437 mr r5, r11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001438#endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */
Stefan Roesee02c5212008-01-09 10:23:16 +01001439
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001440#ifdef CONFIG_SYS_INIT_RAM_DCACHE
Stefan Roesee02c5212008-01-09 10:23:16 +01001441 /*
1442 * Unlock the previously locked d-cache
1443 */
1444 msync
1445 isync
1446 /* set TFLOOR/NFLOOR to 0 again */
1447 lis r6,0x0001
1448 ori r6,r6,0xf800
Matthias Fuchs58ea1422009-07-22 17:27:56 +02001449 mtspr SPRN_DVLIM,r6
Stefan Roesee02c5212008-01-09 10:23:16 +01001450 lis r6,0x0000
1451 ori r6,r6,0x0000
Matthias Fuchs58ea1422009-07-22 17:27:56 +02001452 mtspr SPRN_DNV0,r6
1453 mtspr SPRN_DNV1,r6
1454 mtspr SPRN_DNV2,r6
1455 mtspr SPRN_DNV3,r6
1456 mtspr SPRN_DTV0,r6
1457 mtspr SPRN_DTV1,r6
1458 mtspr SPRN_DTV2,r6
1459 mtspr SPRN_DTV3,r6
Stefan Roesee02c5212008-01-09 10:23:16 +01001460 msync
1461 isync
Stefan Roesef3cac532010-08-31 11:27:14 +02001462
1463 /* Invalidate data cache, now no longer our stack */
1464 dccci 0,0
1465 sync
1466 isync
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001467#endif /* CONFIG_SYS_INIT_RAM_DCACHE */
Stefan Roesee02c5212008-01-09 10:23:16 +01001468
Stefan Roesea4c8d132006-06-02 16:18:04 +02001469 /*
1470 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
1471 * to speed up the boot process. Now this cache needs to be disabled.
1472 */
Stefan Roese4978e602010-05-27 16:45:20 +02001473#if defined(CONFIG_440)
Stefan Roese25fb4ea2008-11-20 11:46:20 +01001474 /* Clear all potential pending exceptions */
Matthias Fuchs58ea1422009-07-22 17:27:56 +02001475 mfspr r1,SPRN_MCSR
1476 mtspr SPRN_MCSR,r1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001477 addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */
Stefan Roesec157d8e2005-08-01 16:41:48 +02001478 tlbre r0,r1,0x0002 /* Read contents */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001479 ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
Wolfgang Denkf901a832005-08-06 01:42:58 +02001480 tlbwe r0,r1,0x0002 /* Save it out */
Stefan Roesea4c8d132006-06-02 16:18:04 +02001481 sync
Stefan Roesec157d8e2005-08-01 16:41:48 +02001482 isync
Stefan Roese4978e602010-05-27 16:45:20 +02001483#endif /* defined(CONFIG_440) */
wdenk0442ed82002-11-03 10:24:00 +00001484 mr r1, r3 /* Set new stack pointer */
1485 mr r9, r4 /* Save copy of Init Data pointer */
1486 mr r10, r5 /* Save copy of Destination Address */
1487
Joakim Tjernlund0f8aa152010-01-19 14:41:56 +01001488 GET_GOT
wdenk0442ed82002-11-03 10:24:00 +00001489 mr r3, r5 /* Destination Address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001490 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
1491 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
wdenk3b57fe02003-05-30 12:48:29 +00001492 lwz r5, GOT(__init_end)
1493 sub r5, r5, r4
Stefan Roese9b94ac62007-10-31 17:55:58 +01001494 li r6, L1_CACHE_BYTES /* Cache Line Size */
wdenk0442ed82002-11-03 10:24:00 +00001495
1496 /*
1497 * Fix GOT pointer:
1498 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001499 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
wdenk0442ed82002-11-03 10:24:00 +00001500 *
1501 * Offset:
1502 */
1503 sub r15, r10, r4
1504
1505 /* First our own GOT */
Joakim Tjernlund0f8aa152010-01-19 14:41:56 +01001506 add r12, r12, r15
Grant Ericksonc821b5f2008-05-22 14:44:14 -07001507 /* then the one used by the C code */
wdenk0442ed82002-11-03 10:24:00 +00001508 add r30, r30, r15
1509
1510 /*
1511 * Now relocate code
1512 */
1513
1514 cmplw cr1,r3,r4
1515 addi r0,r5,3
1516 srwi. r0,r0,2
1517 beq cr1,4f /* In place copy is not necessary */
1518 beq 7f /* Protect against 0 count */
1519 mtctr r0
1520 bge cr1,2f
1521
1522 la r8,-4(r4)
1523 la r7,-4(r3)
15241: lwzu r0,4(r8)
1525 stwu r0,4(r7)
1526 bdnz 1b
1527 b 4f
1528
15292: slwi r0,r0,2
1530 add r8,r4,r0
1531 add r7,r3,r0
15323: lwzu r0,-4(r8)
1533 stwu r0,-4(r7)
1534 bdnz 3b
1535
1536/*
1537 * Now flush the cache: note that we must start from a cache aligned
1538 * address. Otherwise we might miss one cache line.
1539 */
15404: cmpwi r6,0
1541 add r5,r3,r5
1542 beq 7f /* Always flush prefetch queue in any case */
1543 subi r0,r6,1
1544 andc r3,r3,r0
1545 mr r4,r3
15465: dcbst 0,r4
1547 add r4,r4,r6
1548 cmplw r4,r5
1549 blt 5b
1550 sync /* Wait for all dcbst to complete on bus */
1551 mr r4,r3
15526: icbi 0,r4
1553 add r4,r4,r6
1554 cmplw r4,r5
1555 blt 6b
15567: sync /* Wait for all icbi to complete on bus */
1557 isync
1558
1559/*
1560 * We are done. Do not return, instead branch to second part of board
1561 * initialization, now running from RAM.
1562 */
1563
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001564 addi r0, r10, in_ram - _start + _START_OFFSET
wdenk0442ed82002-11-03 10:24:00 +00001565 mtlr r0
1566 blr /* NEVER RETURNS! */
1567
1568in_ram:
1569
1570 /*
Joakim Tjernlund0f8aa152010-01-19 14:41:56 +01001571 * Relocation Function, r12 point to got2+0x8000
wdenk0442ed82002-11-03 10:24:00 +00001572 *
1573 * Adjust got2 pointers, no need to check for 0, this code
1574 * already puts a few entries in the table.
1575 */
1576 li r0,__got2_entries@sectoff@l
1577 la r3,GOT(_GOT2_TABLE_)
1578 lwz r11,GOT(_GOT2_TABLE_)
1579 mtctr r0
1580 sub r11,r3,r11
1581 addi r3,r3,-4
15821: lwzu r0,4(r3)
Joakim Tjernlundafc3ba02009-10-08 02:03:51 +02001583 cmpwi r0,0
1584 beq- 2f
wdenk0442ed82002-11-03 10:24:00 +00001585 add r0,r0,r11
1586 stw r0,0(r3)
Joakim Tjernlundafc3ba02009-10-08 02:03:51 +020015872: bdnz 1b
wdenk0442ed82002-11-03 10:24:00 +00001588
1589 /*
1590 * Now adjust the fixups and the pointers to the fixups
1591 * in case we need to move ourselves again.
1592 */
Joakim Tjernlundafc3ba02009-10-08 02:03:51 +02001593 li r0,__fixup_entries@sectoff@l
wdenk0442ed82002-11-03 10:24:00 +00001594 lwz r3,GOT(_FIXUP_TABLE_)
1595 cmpwi r0,0
1596 mtctr r0
1597 addi r3,r3,-4
1598 beq 4f
15993: lwzu r4,4(r3)
1600 lwzux r0,r4,r11
1601 add r0,r0,r11
1602 stw r10,0(r3)
1603 stw r0,0(r4)
1604 bdnz 3b
16054:
1606clear_bss:
1607 /*
1608 * Now clear BSS segment
1609 */
wdenk5d232d02003-05-22 22:52:13 +00001610 lwz r3,GOT(__bss_start)
wdenk0442ed82002-11-03 10:24:00 +00001611 lwz r4,GOT(_end)
1612
1613 cmplw 0, r3, r4
Anatolij Gustschin42ed33f2007-12-05 17:43:20 +01001614 beq 7f
wdenk0442ed82002-11-03 10:24:00 +00001615
1616 li r0, 0
Anatolij Gustschin42ed33f2007-12-05 17:43:20 +01001617
1618 andi. r5, r4, 3
1619 beq 6f
1620 sub r4, r4, r5
1621 mtctr r5
1622 mr r5, r4
16235: stb r0, 0(r5)
1624 addi r5, r5, 1
1625 bdnz 5b
16266:
wdenk0442ed82002-11-03 10:24:00 +00001627 stw r0, 0(r3)
1628 addi r3, r3, 4
1629 cmplw 0, r3, r4
Anatolij Gustschin42ed33f2007-12-05 17:43:20 +01001630 bne 6b
wdenk0442ed82002-11-03 10:24:00 +00001631
Anatolij Gustschin42ed33f2007-12-05 17:43:20 +010016327:
wdenk0442ed82002-11-03 10:24:00 +00001633 mr r3, r9 /* Init Data pointer */
1634 mr r4, r10 /* Destination Address */
1635 bl board_init_r
1636
wdenk0442ed82002-11-03 10:24:00 +00001637 /*
1638 * Copy exception vector code to low memory
1639 *
1640 * r3: dest_addr
1641 * r7: source address, r8: end address, r9: target address
1642 */
1643 .globl trap_init
1644trap_init:
Joakim Tjernlund0f8aa152010-01-19 14:41:56 +01001645 mflr r4 /* save link register */
1646 GET_GOT
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001647 lwz r7, GOT(_start_of_vectors)
wdenk0442ed82002-11-03 10:24:00 +00001648 lwz r8, GOT(_end_of_vectors)
1649
wdenk682011f2003-06-03 23:54:09 +00001650 li r9, 0x100 /* reset vector always at 0x100 */
wdenk0442ed82002-11-03 10:24:00 +00001651
1652 cmplw 0, r7, r8
1653 bgelr /* return if r7>=r8 - just in case */
wdenk0442ed82002-11-03 10:24:00 +000016541:
1655 lwz r0, 0(r7)
1656 stw r0, 0(r9)
1657 addi r7, r7, 4
1658 addi r9, r9, 4
1659 cmplw 0, r7, r8
1660 bne 1b
1661
1662 /*
1663 * relocate `hdlr' and `int_return' entries
1664 */
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001665 li r7, .L_MachineCheck - _start + _START_OFFSET
1666 li r8, Alignment - _start + _START_OFFSET
wdenk0442ed82002-11-03 10:24:00 +000016672:
1668 bl trap_reloc
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001669 addi r7, r7, 0x100 /* next exception vector */
wdenk0442ed82002-11-03 10:24:00 +00001670 cmplw 0, r7, r8
1671 blt 2b
1672
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001673 li r7, .L_Alignment - _start + _START_OFFSET
wdenk0442ed82002-11-03 10:24:00 +00001674 bl trap_reloc
1675
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001676 li r7, .L_ProgramCheck - _start + _START_OFFSET
wdenk0442ed82002-11-03 10:24:00 +00001677 bl trap_reloc
1678
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001679#ifdef CONFIG_440
1680 li r7, .L_FPUnavailable - _start + _START_OFFSET
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001681 bl trap_reloc
wdenk0442ed82002-11-03 10:24:00 +00001682
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001683 li r7, .L_Decrementer - _start + _START_OFFSET
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001684 bl trap_reloc
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001685
1686 li r7, .L_APU - _start + _START_OFFSET
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001687 bl trap_reloc
Stefan Roesedf8a24c2007-06-19 16:42:31 +02001688
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001689 li r7, .L_InstructionTLBError - _start + _START_OFFSET
1690 bl trap_reloc
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001691
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001692 li r7, .L_DataTLBError - _start + _START_OFFSET
1693 bl trap_reloc
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001694#else /* CONFIG_440 */
1695 li r7, .L_PIT - _start + _START_OFFSET
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001696 bl trap_reloc
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001697
1698 li r7, .L_InstructionTLBMiss - _start + _START_OFFSET
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001699 bl trap_reloc
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001700
1701 li r7, .L_DataTLBMiss - _start + _START_OFFSET
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001702 bl trap_reloc
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001703#endif /* CONFIG_440 */
1704
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001705 li r7, .L_DebugBreakpoint - _start + _START_OFFSET
1706 bl trap_reloc
wdenk0442ed82002-11-03 10:24:00 +00001707
Stefan Roese887e2ec2006-09-07 11:51:23 +02001708#if !defined(CONFIG_440)
Stefan Roese9a7b4082006-03-13 09:42:28 +01001709 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1710 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1711 mtmsr r7 /* change MSR */
1712#else
Stefan Roese887e2ec2006-09-07 11:51:23 +02001713 bl __440_msr_set
1714 b __440_msr_continue
Stefan Roese9a7b4082006-03-13 09:42:28 +01001715
Stefan Roese887e2ec2006-09-07 11:51:23 +02001716__440_msr_set:
Stefan Roese9a7b4082006-03-13 09:42:28 +01001717 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1718 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
Matthias Fuchs58ea1422009-07-22 17:27:56 +02001719 mtspr SPRN_SRR1,r7
Stefan Roese9a7b4082006-03-13 09:42:28 +01001720 mflr r7
Matthias Fuchs58ea1422009-07-22 17:27:56 +02001721 mtspr SPRN_SRR0,r7
Stefan Roese9a7b4082006-03-13 09:42:28 +01001722 rfi
Stefan Roese887e2ec2006-09-07 11:51:23 +02001723__440_msr_continue:
Stefan Roese9a7b4082006-03-13 09:42:28 +01001724#endif
1725
wdenk0442ed82002-11-03 10:24:00 +00001726 mtlr r4 /* restore link register */
1727 blr
1728
Stefan Roesecf959c72007-06-01 15:27:11 +02001729#if defined(CONFIG_440)
1730/*----------------------------------------------------------------------------+
1731| dcbz_area.
1732+----------------------------------------------------------------------------*/
1733 function_prolog(dcbz_area)
1734 rlwinm. r5,r4,0,27,31
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001735 rlwinm r5,r4,27,5,31
1736 beq ..d_ra2
1737 addi r5,r5,0x0001
1738..d_ra2:mtctr r5
1739..d_ag2:dcbz r0,r3
1740 addi r3,r3,32
1741 bdnz ..d_ag2
Stefan Roesecf959c72007-06-01 15:27:11 +02001742 sync
1743 blr
1744 function_epilog(dcbz_area)
Stefan Roesecf959c72007-06-01 15:27:11 +02001745#endif /* CONFIG_440 */
Stefan Roese887e2ec2006-09-07 11:51:23 +02001746#endif /* CONFIG_NAND_SPL */
stroeseb867d702003-05-23 11:18:02 +00001747
Stefan Roesecf959c72007-06-01 15:27:11 +02001748/*------------------------------------------------------------------------------- */
1749/* Function: in8 */
1750/* Description: Input 8 bits */
1751/*------------------------------------------------------------------------------- */
1752 .globl in8
1753in8:
1754 lbz r3,0x0000(r3)
1755 blr
1756
1757/*------------------------------------------------------------------------------- */
1758/* Function: out8 */
1759/* Description: Output 8 bits */
1760/*------------------------------------------------------------------------------- */
1761 .globl out8
1762out8:
1763 stb r4,0x0000(r3)
1764 blr
1765
1766/*------------------------------------------------------------------------------- */
1767/* Function: out32 */
1768/* Description: Output 32 bits */
1769/*------------------------------------------------------------------------------- */
1770 .globl out32
1771out32:
1772 stw r4,0x0000(r3)
1773 blr
1774
1775/*------------------------------------------------------------------------------- */
1776/* Function: in32 */
1777/* Description: Input 32 bits */
1778/*------------------------------------------------------------------------------- */
1779 .globl in32
1780in32:
1781 lwz 3,0x0000(3)
1782 blr
stroeseb867d702003-05-23 11:18:02 +00001783
1784/**************************************************************************/
Wolfgang Denkf901a832005-08-06 01:42:58 +02001785/* PPC405EP specific stuff */
stroeseb867d702003-05-23 11:18:02 +00001786/**************************************************************************/
1787#ifdef CONFIG_405EP
1788ppc405ep_init:
stroeseb828dda2003-12-09 14:54:43 +00001789
Stefan Roesec157d8e2005-08-01 16:41:48 +02001790#ifdef CONFIG_BUBINGA
stroeseb828dda2003-12-09 14:54:43 +00001791 /*
1792 * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
1793 * function) to support FPGA and NVRAM accesses below.
1794 */
1795
1796 lis r3,GPIO0_OSRH@h /* config GPIO output select */
1797 ori r3,r3,GPIO0_OSRH@l
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001798 lis r4,CONFIG_SYS_GPIO0_OSRH@h
1799 ori r4,r4,CONFIG_SYS_GPIO0_OSRH@l
stroeseb828dda2003-12-09 14:54:43 +00001800 stw r4,0(r3)
1801 lis r3,GPIO0_OSRL@h
1802 ori r3,r3,GPIO0_OSRL@l
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001803 lis r4,CONFIG_SYS_GPIO0_OSRL@h
1804 ori r4,r4,CONFIG_SYS_GPIO0_OSRL@l
stroeseb828dda2003-12-09 14:54:43 +00001805 stw r4,0(r3)
1806
1807 lis r3,GPIO0_ISR1H@h /* config GPIO input select */
1808 ori r3,r3,GPIO0_ISR1H@l
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001809 lis r4,CONFIG_SYS_GPIO0_ISR1H@h
1810 ori r4,r4,CONFIG_SYS_GPIO0_ISR1H@l
stroeseb828dda2003-12-09 14:54:43 +00001811 stw r4,0(r3)
1812 lis r3,GPIO0_ISR1L@h
1813 ori r3,r3,GPIO0_ISR1L@l
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001814 lis r4,CONFIG_SYS_GPIO0_ISR1L@h
1815 ori r4,r4,CONFIG_SYS_GPIO0_ISR1L@l
stroeseb828dda2003-12-09 14:54:43 +00001816 stw r4,0(r3)
1817
1818 lis r3,GPIO0_TSRH@h /* config GPIO three-state select */
1819 ori r3,r3,GPIO0_TSRH@l
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001820 lis r4,CONFIG_SYS_GPIO0_TSRH@h
1821 ori r4,r4,CONFIG_SYS_GPIO0_TSRH@l
stroeseb828dda2003-12-09 14:54:43 +00001822 stw r4,0(r3)
1823 lis r3,GPIO0_TSRL@h
1824 ori r3,r3,GPIO0_TSRL@l
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001825 lis r4,CONFIG_SYS_GPIO0_TSRL@h
1826 ori r4,r4,CONFIG_SYS_GPIO0_TSRL@l
stroeseb828dda2003-12-09 14:54:43 +00001827 stw r4,0(r3)
1828
1829 lis r3,GPIO0_TCR@h /* config GPIO driver output enables */
1830 ori r3,r3,GPIO0_TCR@l
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001831 lis r4,CONFIG_SYS_GPIO0_TCR@h
1832 ori r4,r4,CONFIG_SYS_GPIO0_TCR@l
stroeseb828dda2003-12-09 14:54:43 +00001833 stw r4,0(r3)
1834
Stefan Roesed1c3b272009-09-09 16:25:29 +02001835 li r3,PB1AP /* program EBC bank 1 for RTC access */
1836 mtdcr EBC0_CFGADDR,r3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001837 lis r3,CONFIG_SYS_EBC_PB1AP@h
1838 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
Stefan Roesed1c3b272009-09-09 16:25:29 +02001839 mtdcr EBC0_CFGDATA,r3
1840 li r3,PB1CR
1841 mtdcr EBC0_CFGADDR,r3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001842 lis r3,CONFIG_SYS_EBC_PB1CR@h
1843 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
Stefan Roesed1c3b272009-09-09 16:25:29 +02001844 mtdcr EBC0_CFGDATA,r3
stroeseb828dda2003-12-09 14:54:43 +00001845
Stefan Roesed1c3b272009-09-09 16:25:29 +02001846 li r3,PB1AP /* program EBC bank 1 for RTC access */
1847 mtdcr EBC0_CFGADDR,r3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001848 lis r3,CONFIG_SYS_EBC_PB1AP@h
1849 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
Stefan Roesed1c3b272009-09-09 16:25:29 +02001850 mtdcr EBC0_CFGDATA,r3
1851 li r3,PB1CR
1852 mtdcr EBC0_CFGADDR,r3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001853 lis r3,CONFIG_SYS_EBC_PB1CR@h
1854 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
Stefan Roesed1c3b272009-09-09 16:25:29 +02001855 mtdcr EBC0_CFGDATA,r3
stroeseb828dda2003-12-09 14:54:43 +00001856
Stefan Roesed1c3b272009-09-09 16:25:29 +02001857 li r3,PB4AP /* program EBC bank 4 for FPGA access */
1858 mtdcr EBC0_CFGADDR,r3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001859 lis r3,CONFIG_SYS_EBC_PB4AP@h
1860 ori r3,r3,CONFIG_SYS_EBC_PB4AP@l
Stefan Roesed1c3b272009-09-09 16:25:29 +02001861 mtdcr EBC0_CFGDATA,r3
1862 li r3,PB4CR
1863 mtdcr EBC0_CFGADDR,r3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001864 lis r3,CONFIG_SYS_EBC_PB4CR@h
1865 ori r3,r3,CONFIG_SYS_EBC_PB4CR@l
Stefan Roesed1c3b272009-09-09 16:25:29 +02001866 mtdcr EBC0_CFGDATA,r3
stroeseb828dda2003-12-09 14:54:43 +00001867#endif
1868
wdenk8bde7f72003-06-27 21:31:46 +00001869 /*
1870 !-----------------------------------------------------------------------
1871 ! Check to see if chip is in bypass mode.
1872 ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1873 ! CPU reset Otherwise, skip this step and keep going.
Wolfgang Denkf901a832005-08-06 01:42:58 +02001874 ! Note: Running BIOS in bypass mode is not supported since PLB speed
1875 ! will not be fast enough for the SDRAM (min 66MHz)
wdenk8bde7f72003-06-27 21:31:46 +00001876 !-----------------------------------------------------------------------
stroeseb867d702003-05-23 11:18:02 +00001877 */
Wolfgang Denkf901a832005-08-06 01:42:58 +02001878 mfdcr r5, CPC0_PLLMR1
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001879 rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
Wolfgang Denkf901a832005-08-06 01:42:58 +02001880 cmpi cr0,0,r4,0x1
stroeseb867d702003-05-23 11:18:02 +00001881
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001882 beq pll_done /* if SSCS =b'1' then PLL has */
1883 /* already been set */
1884 /* and CPU has been reset */
1885 /* so skip to next section */
stroeseb867d702003-05-23 11:18:02 +00001886
Stefan Roesec157d8e2005-08-01 16:41:48 +02001887#ifdef CONFIG_BUBINGA
stroeseb867d702003-05-23 11:18:02 +00001888 /*
wdenk8bde7f72003-06-27 21:31:46 +00001889 !-----------------------------------------------------------------------
1890 ! Read NVRAM to get value to write in PLLMR.
1891 ! If value has not been correctly saved, write default value
1892 ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1893 ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1894 !
1895 ! WARNING: This code assumes the first three words in the nvram_t
Wolfgang Denkf901a832005-08-06 01:42:58 +02001896 ! structure in openbios.h. Changing the beginning of
1897 ! the structure will break this code.
wdenk8bde7f72003-06-27 21:31:46 +00001898 !
1899 !-----------------------------------------------------------------------
stroeseb867d702003-05-23 11:18:02 +00001900 */
Wolfgang Denkf901a832005-08-06 01:42:58 +02001901 addis r3,0,NVRAM_BASE@h
1902 addi r3,r3,NVRAM_BASE@l
stroeseb867d702003-05-23 11:18:02 +00001903
Wolfgang Denkf901a832005-08-06 01:42:58 +02001904 lwz r4, 0(r3)
1905 addis r5,0,NVRVFY1@h
1906 addi r5,r5,NVRVFY1@l
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001907 cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
Wolfgang Denkf901a832005-08-06 01:42:58 +02001908 bne ..no_pllset
1909 addi r3,r3,4
1910 lwz r4, 0(r3)
1911 addis r5,0,NVRVFY2@h
1912 addi r5,r5,NVRVFY2@l
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001913 cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
Wolfgang Denkf901a832005-08-06 01:42:58 +02001914 bne ..no_pllset
1915 addi r3,r3,8 /* Skip over conf_size */
1916 lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
1917 lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
1918 rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
1919 cmpi cr0,0,r5,1 /* See if PLL is locked */
1920 beq pll_write
stroeseb867d702003-05-23 11:18:02 +00001921..no_pllset:
Stefan Roesec157d8e2005-08-01 16:41:48 +02001922#endif /* CONFIG_BUBINGA */
stroeseb867d702003-05-23 11:18:02 +00001923
John Otkend4024bb2007-07-26 17:49:11 +02001924#ifdef CONFIG_TAIHU
1925 mfdcr r4, CPC0_BOOT
1926 andi. r5, r4, CPC0_BOOT_SEP@l
1927 bne strap_1 /* serial eeprom present */
1928 addis r5,0,CPLD_REG0_ADDR@h
1929 ori r5,r5,CPLD_REG0_ADDR@l
1930 andi. r5, r5, 0x10
1931 bne _pci_66mhz
1932#endif /* CONFIG_TAIHU */
1933
Stefan Roese779e9752007-08-14 14:44:41 +02001934#if defined(CONFIG_ZEUS)
1935 mfdcr r4, CPC0_BOOT
1936 andi. r5, r4, CPC0_BOOT_SEP@l
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001937 bne strap_1 /* serial eeprom present */
Stefan Roese779e9752007-08-14 14:44:41 +02001938 lis r3,0x0000
1939 addi r3,r3,0x3030
1940 lis r4,0x8042
1941 addi r4,r4,0x223e
1942 b 1f
1943strap_1:
1944 mfdcr r3, CPC0_PLLMR0
1945 mfdcr r4, CPC0_PLLMR1
1946 b 1f
1947#endif
1948
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001949 addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
1950 ori r3,r3,PLLMR0_DEFAULT@l /* */
1951 addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
1952 ori r4,r4,PLLMR1_DEFAULT@l /* */
stroeseb867d702003-05-23 11:18:02 +00001953
John Otkend4024bb2007-07-26 17:49:11 +02001954#ifdef CONFIG_TAIHU
1955 b 1f
1956_pci_66mhz:
1957 addis r3,0,PLLMR0_DEFAULT_PCI66@h
1958 ori r3,r3,PLLMR0_DEFAULT_PCI66@l
1959 addis r4,0,PLLMR1_DEFAULT_PCI66@h
1960 ori r4,r4,PLLMR1_DEFAULT_PCI66@l
1961 b 1f
1962strap_1:
1963 mfdcr r3, CPC0_PLLMR0
1964 mfdcr r4, CPC0_PLLMR1
John Otkend4024bb2007-07-26 17:49:11 +02001965#endif /* CONFIG_TAIHU */
1966
Stefan Roese779e9752007-08-14 14:44:41 +020019671:
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001968 b pll_write /* Write the CPC0_PLLMR with new value */
stroeseb867d702003-05-23 11:18:02 +00001969
1970pll_done:
wdenk8bde7f72003-06-27 21:31:46 +00001971 /*
1972 !-----------------------------------------------------------------------
1973 ! Clear Soft Reset Register
1974 ! This is needed to enable PCI if not booting from serial EPROM
1975 !-----------------------------------------------------------------------
stroeseb867d702003-05-23 11:18:02 +00001976 */
Wolfgang Denkf901a832005-08-06 01:42:58 +02001977 addi r3, 0, 0x0
1978 mtdcr CPC0_SRR, r3
stroeseb867d702003-05-23 11:18:02 +00001979
Wolfgang Denkf901a832005-08-06 01:42:58 +02001980 addis r3,0,0x0010
1981 mtctr r3
stroeseb867d702003-05-23 11:18:02 +00001982pci_wait:
Wolfgang Denkf901a832005-08-06 01:42:58 +02001983 bdnz pci_wait
stroeseb867d702003-05-23 11:18:02 +00001984
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001985 blr /* return to main code */
stroeseb867d702003-05-23 11:18:02 +00001986
1987/*
1988!-----------------------------------------------------------------------------
Wolfgang Denkf901a832005-08-06 01:42:58 +02001989! Function: pll_write
1990! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
1991! That is:
1992! 1. Pll is first disabled (de-activated by putting in bypass mode)
1993! 2. PLL is reset
1994! 3. Clock dividers are set while PLL is held in reset and bypassed
1995! 4. PLL Reset is cleared
1996! 5. Wait 100us for PLL to lock
1997! 6. A core reset is performed
stroeseb867d702003-05-23 11:18:02 +00001998! Input: r3 = Value to write to CPC0_PLLMR0
1999! Input: r4 = Value to write to CPC0_PLLMR1
2000! Output r3 = none
2001!-----------------------------------------------------------------------------
2002*/
Matthias Fuchs0580e482009-07-06 16:27:33 +02002003 .globl pll_write
stroeseb867d702003-05-23 11:18:02 +00002004pll_write:
wdenk8bde7f72003-06-27 21:31:46 +00002005 mfdcr r5, CPC0_UCR
2006 andis. r5,r5,0xFFFF
Wolfgang Denk53677ef2008-05-20 16:00:29 +02002007 ori r5,r5,0x0101 /* Stop the UART clocks */
2008 mtdcr CPC0_UCR,r5 /* Before changing PLL */
stroeseb867d702003-05-23 11:18:02 +00002009
wdenk8bde7f72003-06-27 21:31:46 +00002010 mfdcr r5, CPC0_PLLMR1
Wolfgang Denk53677ef2008-05-20 16:00:29 +02002011 rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
Wolfgang Denkf901a832005-08-06 01:42:58 +02002012 mtdcr CPC0_PLLMR1,r5
Wolfgang Denk53677ef2008-05-20 16:00:29 +02002013 oris r5,r5,0x4000 /* Set PLL Reset */
Wolfgang Denkf901a832005-08-06 01:42:58 +02002014 mtdcr CPC0_PLLMR1,r5
stroeseb867d702003-05-23 11:18:02 +00002015
Wolfgang Denk53677ef2008-05-20 16:00:29 +02002016 mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
2017 rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
2018 oris r5,r5,0x4000 /* Set PLL Reset */
2019 mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
2020 rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
Wolfgang Denkf901a832005-08-06 01:42:58 +02002021 mtdcr CPC0_PLLMR1,r5
stroeseb867d702003-05-23 11:18:02 +00002022
2023 /*
wdenk8bde7f72003-06-27 21:31:46 +00002024 ! Wait min of 100us for PLL to lock.
2025 ! See CMOS 27E databook for more info.
2026 ! At 200MHz, that means waiting 20,000 instructions
stroeseb867d702003-05-23 11:18:02 +00002027 */
Wolfgang Denkf901a832005-08-06 01:42:58 +02002028 addi r3,0,20000 /* 2000 = 0x4e20 */
2029 mtctr r3
stroeseb867d702003-05-23 11:18:02 +00002030pll_wait:
Wolfgang Denkf901a832005-08-06 01:42:58 +02002031 bdnz pll_wait
stroeseb867d702003-05-23 11:18:02 +00002032
Wolfgang Denkf901a832005-08-06 01:42:58 +02002033 oris r5,r5,0x8000 /* Enable PLL */
2034 mtdcr CPC0_PLLMR1,r5 /* Engage */
stroeseb867d702003-05-23 11:18:02 +00002035
wdenk8bde7f72003-06-27 21:31:46 +00002036 /*
2037 * Reset CPU to guarantee timings are OK
2038 * Not sure if this is needed...
2039 */
2040 addis r3,0,0x1000
Matthias Fuchs58ea1422009-07-22 17:27:56 +02002041 mtspr SPRN_DBCR0,r3 /* This will cause a CPU core reset, and */
Wolfgang Denk53677ef2008-05-20 16:00:29 +02002042 /* execution will continue from the poweron */
2043 /* vector of 0xfffffffc */
stroeseb867d702003-05-23 11:18:02 +00002044#endif /* CONFIG_405EP */
Stefan Roese4745aca2007-02-20 10:57:08 +01002045
2046#if defined(CONFIG_440)
Stefan Roese4745aca2007-02-20 10:57:08 +01002047/*----------------------------------------------------------------------------+
2048| mttlb3.
2049+----------------------------------------------------------------------------*/
2050 function_prolog(mttlb3)
2051 TLBWE(4,3,2)
2052 blr
2053 function_epilog(mttlb3)
2054
2055/*----------------------------------------------------------------------------+
2056| mftlb3.
2057+----------------------------------------------------------------------------*/
2058 function_prolog(mftlb3)
Wolfgang Denk74357112007-02-27 14:26:04 +01002059 TLBRE(3,3,2)
Stefan Roese4745aca2007-02-20 10:57:08 +01002060 blr
2061 function_epilog(mftlb3)
2062
2063/*----------------------------------------------------------------------------+
2064| mttlb2.
2065+----------------------------------------------------------------------------*/
2066 function_prolog(mttlb2)
2067 TLBWE(4,3,1)
2068 blr
2069 function_epilog(mttlb2)
2070
2071/*----------------------------------------------------------------------------+
2072| mftlb2.
2073+----------------------------------------------------------------------------*/
2074 function_prolog(mftlb2)
Wolfgang Denk74357112007-02-27 14:26:04 +01002075 TLBRE(3,3,1)
Stefan Roese4745aca2007-02-20 10:57:08 +01002076 blr
2077 function_epilog(mftlb2)
2078
2079/*----------------------------------------------------------------------------+
2080| mttlb1.
2081+----------------------------------------------------------------------------*/
2082 function_prolog(mttlb1)
2083 TLBWE(4,3,0)
2084 blr
2085 function_epilog(mttlb1)
2086
2087/*----------------------------------------------------------------------------+
2088| mftlb1.
2089+----------------------------------------------------------------------------*/
2090 function_prolog(mftlb1)
Wolfgang Denk74357112007-02-27 14:26:04 +01002091 TLBRE(3,3,0)
Stefan Roese4745aca2007-02-20 10:57:08 +01002092 blr
2093 function_epilog(mftlb1)
2094#endif /* CONFIG_440 */
Stefan Roese64852d02008-06-02 14:35:44 +02002095
2096#if defined(CONFIG_NAND_SPL)
2097/*
2098 * void nand_boot_relocate(dst, src, bytes)
2099 *
2100 * r3 = Destination address to copy code to (in SDRAM)
2101 * r4 = Source address to copy code from
2102 * r5 = size to copy in bytes
2103 */
2104nand_boot_relocate:
2105 mr r6,r3
2106 mr r7,r4
2107 mflr r8
2108
2109 /*
2110 * Copy SPL from icache into SDRAM
2111 */
2112 subi r3,r3,4
2113 subi r4,r4,4
2114 srwi r5,r5,2
2115 mtctr r5
2116..spl_loop:
2117 lwzu r0,4(r4)
2118 stwu r0,4(r3)
2119 bdnz ..spl_loop
2120
2121 /*
2122 * Calculate "corrected" link register, so that we "continue"
2123 * in execution in destination range
2124 */
2125 sub r3,r7,r6 /* r3 = src - dst */
2126 sub r8,r8,r3 /* r8 = link-reg - (src - dst) */
2127 mtlr r8
2128 blr
2129
2130nand_boot_common:
2131 /*
2132 * First initialize SDRAM. It has to be available *before* calling
2133 * nand_boot().
2134 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02002135 lis r3,CONFIG_SYS_SDRAM_BASE@h
2136 ori r3,r3,CONFIG_SYS_SDRAM_BASE@l
Stefan Roese64852d02008-06-02 14:35:44 +02002137 bl initdram
2138
2139 /*
2140 * Now copy the 4k SPL code into SDRAM and continue execution
2141 * from there.
2142 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02002143 lis r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h
2144 ori r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l
2145 lis r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h
2146 ori r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l
2147 lis r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h
2148 ori r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l
Stefan Roese64852d02008-06-02 14:35:44 +02002149 bl nand_boot_relocate
2150
2151 /*
2152 * We're running from SDRAM now!!!
2153 *
2154 * It is necessary for 4xx systems to relocate from running at
2155 * the original location (0xfffffxxx) to somewhere else (SDRAM
2156 * preferably). This is because CS0 needs to be reconfigured for
2157 * NAND access. And we can't reconfigure this CS when currently
2158 * "running" from it.
2159 */
2160
2161 /*
2162 * Finally call nand_boot() to load main NAND U-Boot image from
2163 * NAND and jump to it.
2164 */
2165 bl nand_boot /* will not return */
2166#endif /* CONFIG_NAND_SPL */