blob: c517e4a89f86ce63512e4e852bbd8a985897fd49 [file] [log] [blame]
Simon Glass6f92ed82015-08-04 12:33:55 -06001/*
2 * (C) Copyright 2015 Google, Inc
3 * Written by Simon Glass <sjg@chromium.org>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <asm/global_data.h>
9#include <asm/msr-index.h>
10#include <asm/processor-flags.h>
11
12 /*
13 * rdi - 32-bit code segment selector
14 * rsi - target address
15 * rdx - table address (0 if none)
16 */
17.code64
18.globl cpu_call32
19cpu_call32:
20 cli
21
22 /* Save table pointer */
23 mov %edx, %ebx
24
25 /*
26 * Debugging option, this outputs characters to the console UART
27 * mov $0x3f8,%edx
28 * mov $'a',%al
29 * out %al,(%dx)
30 */
31
32 pushf
33 push %rdi /* 32-bit code segment */
34 lea compat(%rip), %rax
35 push %rax
36 .byte 0x48 /* REX prefix to force 64-bit far return */
37 retf
38.code32
39compat:
40 /*
41 * We are now in compatibility mode with a default operand size of
42 * 32 bits. First disable paging.
43 */
44 movl %cr0, %eax
45 andl $~X86_CR0_PG, %eax
46 movl %eax, %cr0
47
48 /* Invalidate TLB */
49 xorl %eax, %eax
50 movl %eax, %cr3
51
52 /* Disable Long mode in EFER (Extended Feature Enable Register) */
53 movl $MSR_EFER, %ecx
54 rdmsr
55 btr $_EFER_LME, %eax
56 wrmsr
57
58 /* Set up table pointer for _x86boot_start */
59 mov %ebx, %ecx
60
61 /* Jump to the required target */
62 pushl %edi /* 32-bit code segment */
63 pushl %esi /* 32-bit target address */
64 retf