| Zhi-zhou Zhang | 32afad7 | 2012-10-16 15:02:08 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2003 |
| 3 | * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #include <common.h> |
| 25 | #include <command.h> |
| 26 | #include <netdev.h> |
| 27 | #include <asm/mipsregs.h> |
| 28 | #include <asm/cacheops.h> |
| 29 | #include <asm/reboot.h> |
| 30 | |
| 31 | #define cache_op(op, addr) \ |
| 32 | __asm__ __volatile__( \ |
| 33 | " .set push\n" \ |
| 34 | " .set noreorder\n" \ |
| 35 | " .set mips64\n" \ |
| 36 | " cache %0, %1\n" \ |
| 37 | " .set pop\n" \ |
| 38 | : \ |
| 39 | : "i" (op), "R" (*(unsigned char *)(addr))) |
| 40 | |
| 41 | void __attribute__((weak)) _machine_restart(void) |
| 42 | { |
| 43 | fprintf(stderr, "*** reset failed ***\n"); |
| 44 | |
| 45 | while (1) |
| 46 | /* NOP */; |
| 47 | } |
| 48 | |
| 49 | int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
| 50 | { |
| 51 | _machine_restart(); |
| 52 | |
| 53 | return 0; |
| 54 | } |
| 55 | |
| 56 | void flush_cache(ulong start_addr, ulong size) |
| 57 | { |
| 58 | unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; |
| 59 | unsigned long addr = start_addr & ~(lsize - 1); |
| 60 | unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); |
| 61 | |
| 62 | /* aend will be miscalculated when size is zero, so we return here */ |
| 63 | if (size == 0) |
| 64 | return; |
| 65 | |
| 66 | while (1) { |
| 67 | cache_op(HIT_WRITEBACK_INV_D, addr); |
| 68 | cache_op(HIT_INVALIDATE_I, addr); |
| 69 | if (addr == aend) |
| 70 | break; |
| 71 | addr += lsize; |
| 72 | } |
| 73 | } |
| 74 | |
| 75 | void flush_dcache_range(ulong start_addr, ulong stop) |
| 76 | { |
| 77 | unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; |
| 78 | unsigned long addr = start_addr & ~(lsize - 1); |
| 79 | unsigned long aend = (stop - 1) & ~(lsize - 1); |
| 80 | |
| 81 | while (1) { |
| 82 | cache_op(HIT_WRITEBACK_INV_D, addr); |
| 83 | if (addr == aend) |
| 84 | break; |
| 85 | addr += lsize; |
| 86 | } |
| 87 | } |
| 88 | |
| 89 | void invalidate_dcache_range(ulong start_addr, ulong stop) |
| 90 | { |
| 91 | unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; |
| 92 | unsigned long addr = start_addr & ~(lsize - 1); |
| 93 | unsigned long aend = (stop - 1) & ~(lsize - 1); |
| 94 | |
| 95 | while (1) { |
| 96 | cache_op(HIT_INVALIDATE_D, addr); |
| 97 | if (addr == aend) |
| 98 | break; |
| 99 | addr += lsize; |
| 100 | } |
| 101 | } |
| 102 | |
| 103 | void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1) |
| 104 | { |
| 105 | write_c0_entrylo0(low0); |
| 106 | write_c0_pagemask(pagemask); |
| 107 | write_c0_entrylo1(low1); |
| 108 | write_c0_entryhi(hi); |
| 109 | write_c0_index(index); |
| 110 | tlb_write_indexed(); |
| 111 | } |