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Dave Liu19580e62007-09-18 12:37:57 +08001/*
2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Dave Liu19580e62007-09-18 12:37:57 +08006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
Dave Liu19580e62007-09-18 12:37:57 +080011/*
12 * High Level Configuration Options
13 */
14#define CONFIG_E300 1 /* E300 family */
Peter Tyser2c7920a2009-05-22 17:23:25 -050015#define CONFIG_MPC837x 1 /* MPC837x CPU specific */
Dave Liu19580e62007-09-18 12:37:57 +080016#define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */
17
Wolfgang Denk2ae18242010-10-06 09:05:45 +020018#define CONFIG_SYS_TEXT_BASE 0xFE000000
19
Dave Liu19580e62007-09-18 12:37:57 +080020/*
21 * System Clock Setup
22 */
23#ifdef CONFIG_PCISLAVE
24#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
25#else
26#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
27#endif
28
29#ifndef CONFIG_SYS_CLK_FREQ
30#define CONFIG_SYS_CLK_FREQ 66000000
31#endif
32
33/*
34 * Hardware Reset Configuration Word
35 * if CLKIN is 66MHz, then
36 * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz
37 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020038#define CONFIG_SYS_HRCW_LOW (\
Dave Liu19580e62007-09-18 12:37:57 +080039 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
40 HRCWL_DDR_TO_SCB_CLK_1X1 |\
41 HRCWL_SVCOD_DIV_2 |\
42 HRCWL_CSB_TO_CLKIN_6X1 |\
43 HRCWL_CORE_TO_CSB_1_5X1)
44
45#ifdef CONFIG_PCISLAVE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020046#define CONFIG_SYS_HRCW_HIGH (\
Dave Liu19580e62007-09-18 12:37:57 +080047 HRCWH_PCI_AGENT |\
48 HRCWH_PCI1_ARBITER_DISABLE |\
49 HRCWH_CORE_ENABLE |\
50 HRCWH_FROM_0XFFF00100 |\
51 HRCWH_BOOTSEQ_DISABLE |\
52 HRCWH_SW_WATCHDOG_DISABLE |\
53 HRCWH_ROM_LOC_LOCAL_16BIT |\
54 HRCWH_RL_EXT_LEGACY |\
55 HRCWH_TSEC1M_IN_RGMII |\
56 HRCWH_TSEC2M_IN_RGMII |\
57 HRCWH_BIG_ENDIAN |\
58 HRCWH_LDP_CLEAR)
59#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#define CONFIG_SYS_HRCW_HIGH (\
Dave Liu19580e62007-09-18 12:37:57 +080061 HRCWH_PCI_HOST |\
62 HRCWH_PCI1_ARBITER_ENABLE |\
63 HRCWH_CORE_ENABLE |\
64 HRCWH_FROM_0X00000100 |\
65 HRCWH_BOOTSEQ_DISABLE |\
66 HRCWH_SW_WATCHDOG_DISABLE |\
67 HRCWH_ROM_LOC_LOCAL_16BIT |\
68 HRCWH_RL_EXT_LEGACY |\
69 HRCWH_TSEC1M_IN_RGMII |\
70 HRCWH_TSEC2M_IN_RGMII |\
71 HRCWH_BIG_ENDIAN |\
72 HRCWH_LDP_CLEAR)
73#endif
74
Dave Liubd4458c2008-03-04 16:59:22 +080075/* Arbiter Configuration Register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
Joe Hershberger8d858082011-10-11 23:57:18 -050077#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
Dave Liubd4458c2008-03-04 16:59:22 +080078
79/* System Priority Control Register */
Joe Hershberger8d858082011-10-11 23:57:18 -050080#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */
Dave Liubd4458c2008-03-04 16:59:22 +080081
Dave Liu19580e62007-09-18 12:37:57 +080082/*
Dave Liubd4458c2008-03-04 16:59:22 +080083 * IP blocks clock configuration
Dave Liu19580e62007-09-18 12:37:57 +080084 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */
86#define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */
Joe Hershberger8d858082011-10-11 23:57:18 -050087#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */
Dave Liu19580e62007-09-18 12:37:57 +080088
89/*
90 * System IO Config
91 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#define CONFIG_SYS_SICRH 0x00000000
93#define CONFIG_SYS_SICRL 0x00000000
Dave Liu19580e62007-09-18 12:37:57 +080094
95/*
96 * Output Buffer Impedance
97 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_OBIR 0x31100000
Dave Liu19580e62007-09-18 12:37:57 +080099
100#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
101#define CONFIG_BOARD_EARLY_INIT_R
Anton Vorontsovc78c6782009-06-10 00:25:31 +0400102#define CONFIG_HWCONFIG
Dave Liu19580e62007-09-18 12:37:57 +0800103
104/*
105 * IMMR new address
106 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_IMMR 0xE0000000
Dave Liu19580e62007-09-18 12:37:57 +0800108
109/*
110 * DDR Setup
111 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
113#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
114#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
115#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
116#define CONFIG_SYS_83XX_DDR_USES_CS0
Joe Hershberger2fef4022011-10-11 23:57:29 -0500117#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \
118 | DDRCDR_ODT \
119 | DDRCDR_Q_DRN)
120 /* 0x80080001 */ /* ODT 150ohm on SoC */
Dave Liu19580e62007-09-18 12:37:57 +0800121
122#undef CONFIG_DDR_ECC /* support DDR ECC function */
123#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
124
125#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
126#define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
127
128#if defined(CONFIG_SPD_EEPROM)
129#define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */
130#else
131/*
132 * Manually set up DDR parameters
Dave Liu7e74d632008-01-10 23:07:23 +0800133 * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
Dave Liu19580e62007-09-18 12:37:57 +0800134 * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
135 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_DDR_SIZE 512 /* MB */
137#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
Joe Hershberger8d858082011-10-11 23:57:18 -0500138#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
Joe Hershberger2fef4022011-10-11 23:57:29 -0500139 | CSCONFIG_ODT_RD_NEVER /* ODT_RD to none */ \
140 | CSCONFIG_ODT_WR_ONLY_CURRENT /* ODT_WR to CSn */ \
141 | CSCONFIG_ROW_BIT_14 \
142 | CSCONFIG_COL_BIT_10)
143 /* 0x80010202 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_DDR_TIMING_3 0x00000000
Joe Hershberger8d858082011-10-11 23:57:18 -0500145#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
146 | (0 << TIMING_CFG0_WRT_SHIFT) \
147 | (0 << TIMING_CFG0_RRT_SHIFT) \
148 | (0 << TIMING_CFG0_WWT_SHIFT) \
149 | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
150 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
151 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
152 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
Dave Liu19580e62007-09-18 12:37:57 +0800153 /* 0x00620802 */
Joe Hershberger8d858082011-10-11 23:57:18 -0500154#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
155 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
156 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
157 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
158 | (13 << TIMING_CFG1_REFREC_SHIFT) \
159 | (3 << TIMING_CFG1_WRREC_SHIFT) \
160 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
161 | (2 << TIMING_CFG1_WRTORD_SHIFT))
Dave Liu19580e62007-09-18 12:37:57 +0800162 /* 0x3935d322 */
Joe Hershberger8d858082011-10-11 23:57:18 -0500163#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
164 | (6 << TIMING_CFG2_CPO_SHIFT) \
165 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
166 | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
167 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
168 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
169 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
Dave Liu7e74d632008-01-10 23:07:23 +0800170 /* 0x131088c8 */
Joe Hershberger8d858082011-10-11 23:57:18 -0500171#define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \
172 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
Dave Liu19580e62007-09-18 12:37:57 +0800173 /* 0x03E00100 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
175#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
Joe Hershberger8d858082011-10-11 23:57:18 -0500176#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
177 | (0x1432 << SDRAM_MODE_SD_SHIFT))
Dave Liu7e74d632008-01-10 23:07:23 +0800178 /* ODT 150ohm CL=3, AL=1 on SDRAM */
Joe Hershberger8d858082011-10-11 23:57:18 -0500179#define CONFIG_SYS_DDR_MODE2 0x00000000
Dave Liu19580e62007-09-18 12:37:57 +0800180#endif
181
182/*
183 * Memory test
184 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
186#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
187#define CONFIG_SYS_MEMTEST_END 0x00140000
Dave Liu19580e62007-09-18 12:37:57 +0800188
189/*
190 * The reserved memory
191 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200192#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Dave Liu19580e62007-09-18 12:37:57 +0800193
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
195#define CONFIG_SYS_RAMBOOT
Dave Liu19580e62007-09-18 12:37:57 +0800196#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#undef CONFIG_SYS_RAMBOOT
Dave Liu19580e62007-09-18 12:37:57 +0800198#endif
199
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
Kevin Hao16c8c172016-07-08 11:25:14 +0800201#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
Joe Hershberger8d858082011-10-11 23:57:18 -0500202#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
Dave Liu19580e62007-09-18 12:37:57 +0800203
204/*
205 * Initial RAM Base Address Setup
206 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_INIT_RAM_LOCK 1
208#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200209#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
Joe Hershberger8d858082011-10-11 23:57:18 -0500210#define CONFIG_SYS_GBL_DATA_OFFSET \
211 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Dave Liu19580e62007-09-18 12:37:57 +0800212
213/*
214 * Local Bus Configuration & Clock Setup
215 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500216#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
217#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_LBC_LBCR 0x00000000
Becky Bruce0914f482010-06-17 11:37:18 -0500219#define CONFIG_FSL_ELBC 1
Dave Liu19580e62007-09-18 12:37:57 +0800220
221/*
222 * FLASH on the Local Bus
223 */
Joe Hershberger8d858082011-10-11 23:57:18 -0500224#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200225#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Joe Hershberger8d858082011-10-11 23:57:18 -0500226#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
227#define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
228#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
Dave Liu19580e62007-09-18 12:37:57 +0800229
Joe Hershberger8d858082011-10-11 23:57:18 -0500230 /* Window base at flash base */
231#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500232#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
Dave Liu19580e62007-09-18 12:37:57 +0800233
Joe Hershberger8d858082011-10-11 23:57:18 -0500234#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500235 | BR_PS_16 /* 16 bit port */ \
236 | BR_MS_GPCM /* MSEL = GPCM */ \
237 | BR_V) /* valid */
238#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
Dave Liuded08312008-01-10 23:08:26 +0800239 | OR_UPM_XAM \
240 | OR_GPCM_CSNT \
Anton Vorontsovf9023af2008-05-29 18:14:56 +0400241 | OR_GPCM_ACS_DIV2 \
Dave Liuded08312008-01-10 23:08:26 +0800242 | OR_GPCM_XACS \
243 | OR_GPCM_SCY_15 \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500244 | OR_GPCM_TRLX_SET \
245 | OR_GPCM_EHTR_SET \
Joe Hershberger8d858082011-10-11 23:57:18 -0500246 | OR_GPCM_EAD)
Dave Liuded08312008-01-10 23:08:26 +0800247 /* 0xFE000FF7 */
Dave Liu19580e62007-09-18 12:37:57 +0800248
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
250#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
Dave Liu19580e62007-09-18 12:37:57 +0800251
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#undef CONFIG_SYS_FLASH_CHECKSUM
253#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
254#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Dave Liu19580e62007-09-18 12:37:57 +0800255
256/*
257 * BCSR on the Local Bus
258 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_BCSR 0xF8000000
Joe Hershberger8d858082011-10-11 23:57:18 -0500260 /* Access window base at BCSR base */
261#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500262#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
Dave Liu19580e62007-09-18 12:37:57 +0800263
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500264#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
265 | BR_PS_8 \
266 | BR_MS_GPCM \
267 | BR_V)
268 /* 0xF8000801 */
269#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
270 | OR_GPCM_XAM \
271 | OR_GPCM_CSNT \
272 | OR_GPCM_XACS \
273 | OR_GPCM_SCY_15 \
274 | OR_GPCM_TRLX_SET \
275 | OR_GPCM_EHTR_SET \
276 | OR_GPCM_EAD)
277 /* 0xFFFFE9F7 */
Dave Liu19580e62007-09-18 12:37:57 +0800278
279/*
280 * NAND Flash on the Local Bus
281 */
Anton Vorontsovb3379f32008-10-08 20:52:54 +0400282#define CONFIG_CMD_NAND 1
Anton Vorontsovb3379f32008-10-08 20:52:54 +0400283#define CONFIG_SYS_MAX_NAND_DEVICE 1
Joe Hershberger8d858082011-10-11 23:57:18 -0500284#define CONFIG_NAND_FSL_ELBC 1
Anton Vorontsovb3379f32008-10-08 20:52:54 +0400285
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500286#define CONFIG_SYS_NAND_BASE 0xE0600000
Joe Hershberger8d858082011-10-11 23:57:18 -0500287#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500288 | BR_DECC_CHK_GEN /* Use HW ECC */ \
Joe Hershberger8d858082011-10-11 23:57:18 -0500289 | BR_PS_8 /* 8 bit port */ \
Dave Liu19580e62007-09-18 12:37:57 +0800290 | BR_MS_FCM /* MSEL = FCM */ \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500291 | BR_V) /* valid */
292#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \
Anton Vorontsovb3379f32008-10-08 20:52:54 +0400293 | OR_FCM_BCTLD \
Dave Liu19580e62007-09-18 12:37:57 +0800294 | OR_FCM_CST \
295 | OR_FCM_CHT \
296 | OR_FCM_SCY_1 \
Anton Vorontsovb3379f32008-10-08 20:52:54 +0400297 | OR_FCM_RST \
Dave Liu19580e62007-09-18 12:37:57 +0800298 | OR_FCM_TRLX \
Joe Hershberger8d858082011-10-11 23:57:18 -0500299 | OR_FCM_EHTR)
Anton Vorontsovb3379f32008-10-08 20:52:54 +0400300 /* 0xFFFF919E */
Dave Liu19580e62007-09-18 12:37:57 +0800301
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500303#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
Dave Liu19580e62007-09-18 12:37:57 +0800304
305/*
306 * Serial Port
307 */
308#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309#define CONFIG_SYS_NS16550_SERIAL
310#define CONFIG_SYS_NS16550_REG_SIZE 1
311#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Dave Liu19580e62007-09-18 12:37:57 +0800312
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hershberger8d858082011-10-11 23:57:18 -0500314 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
Dave Liu19580e62007-09-18 12:37:57 +0800315
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
317#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Dave Liu19580e62007-09-18 12:37:57 +0800318
Dave Liu19580e62007-09-18 12:37:57 +0800319/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200320#define CONFIG_SYS_I2C
321#define CONFIG_SYS_I2C_FSL
322#define CONFIG_SYS_FSL_I2C_SPEED 400000
323#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
324#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
325#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
Dave Liu19580e62007-09-18 12:37:57 +0800326
327/*
328 * Config on-board RTC
329 */
330#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Dave Liu19580e62007-09-18 12:37:57 +0800332
333/*
334 * General PCI
335 * Addresses are mapped 1-1.
336 */
Joe Hershberger8d858082011-10-11 23:57:18 -0500337#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
338#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
339#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
341#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
342#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
343#define CONFIG_SYS_PCI_IO_BASE 0x00000000
344#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
345#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
Dave Liu19580e62007-09-18 12:37:57 +0800346
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
348#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
349#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
Dave Liu19580e62007-09-18 12:37:57 +0800350
Anton Vorontsov8b345572009-01-08 04:26:19 +0300351#define CONFIG_SYS_PCIE1_BASE 0xA0000000
352#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
353#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
354#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
355#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
356#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
357#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
358#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
359#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
360
361#define CONFIG_SYS_PCIE2_BASE 0xC0000000
362#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
363#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
364#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
365#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
366#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
367#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
368#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
369#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
370
Dave Liu19580e62007-09-18 12:37:57 +0800371#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000372#define CONFIG_PCI_INDIRECT_BRIDGE
Anton Vorontsov00f7bba2008-10-02 19:17:33 +0400373#ifndef __ASSEMBLY__
374extern int board_pci_host_broken(void);
375#endif
Kim Phillipsbe9b56d2009-07-23 14:09:38 -0500376#define CONFIG_PCIE
Dave Liu19580e62007-09-18 12:37:57 +0800377#define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */
378
Anton Vorontsov3bf1be32008-10-14 22:58:53 +0400379#define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */
Nikhil Badola6c3c5752014-10-20 16:31:01 +0530380#define CONFIG_USB_EHCI
381#define CONFIG_USB_EHCI_FSL
382#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Anton Vorontsov3bf1be32008-10-14 22:58:53 +0400383
Dave Liu19580e62007-09-18 12:37:57 +0800384#undef CONFIG_EEPRO100
385#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
Dave Liu19580e62007-09-18 12:37:57 +0800387#endif /* CONFIG_PCI */
388
Dave Liu19580e62007-09-18 12:37:57 +0800389/*
390 * TSEC
391 */
392#define CONFIG_TSEC_ENET /* TSEC ethernet support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200393#define CONFIG_SYS_TSEC1_OFFSET 0x24000
Joe Hershberger8d858082011-10-11 23:57:18 -0500394#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200395#define CONFIG_SYS_TSEC2_OFFSET 0x25000
Joe Hershberger8d858082011-10-11 23:57:18 -0500396#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
Dave Liu19580e62007-09-18 12:37:57 +0800397
398/*
399 * TSEC ethernet configuration
400 */
401#define CONFIG_MII 1 /* MII PHY management */
402#define CONFIG_TSEC1 1
403#define CONFIG_TSEC1_NAME "eTSEC0"
404#define CONFIG_TSEC2 1
405#define CONFIG_TSEC2_NAME "eTSEC1"
406#define TSEC1_PHY_ADDR 2
407#define TSEC2_PHY_ADDR 3
Anton Vorontsov1da83a62008-10-02 18:32:25 +0400408#define TSEC1_PHY_ADDR_SGMII 8
409#define TSEC2_PHY_ADDR_SGMII 4
Dave Liu19580e62007-09-18 12:37:57 +0800410#define TSEC1_PHYIDX 0
411#define TSEC2_PHYIDX 0
412#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
413#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
414
415/* Options are: TSEC[0-1] */
416#define CONFIG_ETHPRIME "eTSEC1"
417
Dave Liu6f8c85e2008-03-26 22:56:36 +0800418/* SERDES */
419#define CONFIG_FSL_SERDES
420#define CONFIG_FSL_SERDES1 0xe3000
421#define CONFIG_FSL_SERDES2 0xe3100
422
Dave Liu19580e62007-09-18 12:37:57 +0800423/*
Dave Liu2eeb3e42008-03-26 22:57:19 +0800424 * SATA
425 */
426#define CONFIG_LIBATA
427#define CONFIG_FSL_SATA
428
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200429#define CONFIG_SYS_SATA_MAX_DEVICE 2
Dave Liu2eeb3e42008-03-26 22:57:19 +0800430#define CONFIG_SATA1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200431#define CONFIG_SYS_SATA1_OFFSET 0x18000
Joe Hershberger8d858082011-10-11 23:57:18 -0500432#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
433#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
Dave Liu2eeb3e42008-03-26 22:57:19 +0800434#define CONFIG_SATA2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200435#define CONFIG_SYS_SATA2_OFFSET 0x19000
Joe Hershberger8d858082011-10-11 23:57:18 -0500436#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
437#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
Dave Liu2eeb3e42008-03-26 22:57:19 +0800438
439#ifdef CONFIG_FSL_SATA
440#define CONFIG_LBA48
441#define CONFIG_CMD_SATA
442#define CONFIG_DOS_PARTITION
Dave Liu2eeb3e42008-03-26 22:57:19 +0800443#endif
444
445/*
Dave Liu19580e62007-09-18 12:37:57 +0800446 * Environment
447 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200448#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200449 #define CONFIG_ENV_IS_IN_FLASH 1
Joe Hershberger8d858082011-10-11 23:57:18 -0500450 #define CONFIG_ENV_ADDR \
451 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200452 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
453 #define CONFIG_ENV_SIZE 0x2000
Dave Liu19580e62007-09-18 12:37:57 +0800454#else
Joe Hershberger8d858082011-10-11 23:57:18 -0500455 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200456 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200457 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200458 #define CONFIG_ENV_SIZE 0x2000
Dave Liu19580e62007-09-18 12:37:57 +0800459#endif
460
461#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200462#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Dave Liu19580e62007-09-18 12:37:57 +0800463
464/*
465 * BOOTP options
466 */
467#define CONFIG_BOOTP_BOOTFILESIZE
468#define CONFIG_BOOTP_BOOTPATH
469#define CONFIG_BOOTP_GATEWAY
470#define CONFIG_BOOTP_HOSTNAME
471
Dave Liu19580e62007-09-18 12:37:57 +0800472/*
473 * Command line configuration.
474 */
Dave Liu19580e62007-09-18 12:37:57 +0800475#define CONFIG_CMD_DATE
476
477#if defined(CONFIG_PCI)
478 #define CONFIG_CMD_PCI
479#endif
480
Dave Liu19580e62007-09-18 12:37:57 +0800481#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Kim Phillipsa059e902010-04-15 17:36:05 -0500482#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Dave Liu19580e62007-09-18 12:37:57 +0800483
484#undef CONFIG_WATCHDOG /* watchdog disabled */
485
Andy Fleminge1ac3872008-10-30 16:50:14 -0500486#define CONFIG_MMC 1
487
488#ifdef CONFIG_MMC
489#define CONFIG_FSL_ESDHC
Chenhui Zhaoa6da8b82011-01-04 17:23:05 +0800490#define CONFIG_FSL_ESDHC_PIN_MUX
Andy Fleminge1ac3872008-10-30 16:50:14 -0500491#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
Andy Fleminge1ac3872008-10-30 16:50:14 -0500492#define CONFIG_GENERIC_MMC
Andy Fleminge1ac3872008-10-30 16:50:14 -0500493#define CONFIG_DOS_PARTITION
494#endif
495
Dave Liu19580e62007-09-18 12:37:57 +0800496/*
497 * Miscellaneous configurable options
498 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200499#define CONFIG_SYS_LONGHELP /* undef to save memory */
500#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Dave Liu19580e62007-09-18 12:37:57 +0800501
502#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200503 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Dave Liu19580e62007-09-18 12:37:57 +0800504#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200505 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Dave Liu19580e62007-09-18 12:37:57 +0800506#endif
507
Joe Hershberger8d858082011-10-11 23:57:18 -0500508 /* Print Buffer Size */
509#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
510#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
511 /* Boot Argument Buffer Size */
512#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Dave Liu19580e62007-09-18 12:37:57 +0800513
514/*
515 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700516 * have to be in the first 256 MB of memory, since this is
Dave Liu19580e62007-09-18 12:37:57 +0800517 * the maximum mapped by the Linux kernel during initialization.
518 */
Joe Hershberger8d858082011-10-11 23:57:18 -0500519#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
Kevin Hao63865272016-07-08 11:25:15 +0800520#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Dave Liu19580e62007-09-18 12:37:57 +0800521
522/*
523 * Core HID Setup
524 */
Kim Phillips1a2e2032010-04-20 19:37:54 -0500525#define CONFIG_SYS_HID0_INIT 0x000000000
526#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
527 HID0_ENABLE_INSTRUCTION_CACHE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200528#define CONFIG_SYS_HID2 HID2_HBE
Dave Liu19580e62007-09-18 12:37:57 +0800529
530/*
Dave Liu19580e62007-09-18 12:37:57 +0800531 * MMU Setup
532 */
Becky Bruce31d82672008-05-08 19:02:12 -0500533#define CONFIG_HIGH_BATS 1 /* High BATs supported */
Dave Liu19580e62007-09-18 12:37:57 +0800534
535/* DDR: cache cacheable */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200536#define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE
537#define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
Dave Liu19580e62007-09-18 12:37:57 +0800538
Joe Hershberger8d858082011-10-11 23:57:18 -0500539#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500540 | BATL_PP_RW \
Joe Hershberger8d858082011-10-11 23:57:18 -0500541 | BATL_MEMCOHERENCE)
542#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \
543 | BATU_BL_256M \
544 | BATU_VS \
545 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200546#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
547#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
Dave Liu19580e62007-09-18 12:37:57 +0800548
Joe Hershberger8d858082011-10-11 23:57:18 -0500549#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500550 | BATL_PP_RW \
Joe Hershberger8d858082011-10-11 23:57:18 -0500551 | BATL_MEMCOHERENCE)
552#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \
553 | BATU_BL_256M \
554 | BATU_VS \
555 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200556#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
557#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
Dave Liu19580e62007-09-18 12:37:57 +0800558
559/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
Joe Hershberger8d858082011-10-11 23:57:18 -0500560#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500561 | BATL_PP_RW \
Joe Hershberger8d858082011-10-11 23:57:18 -0500562 | BATL_CACHEINHIBIT \
563 | BATL_GUARDEDSTORAGE)
564#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \
565 | BATU_BL_8M \
566 | BATU_VS \
567 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200568#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
569#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
Dave Liu19580e62007-09-18 12:37:57 +0800570
571/* BCSR: cache-inhibit and guarded */
Joe Hershberger8d858082011-10-11 23:57:18 -0500572#define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500573 | BATL_PP_RW \
Joe Hershberger8d858082011-10-11 23:57:18 -0500574 | BATL_CACHEINHIBIT \
575 | BATL_GUARDEDSTORAGE)
576#define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR \
577 | BATU_BL_128K \
578 | BATU_VS \
579 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200580#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
581#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
Dave Liu19580e62007-09-18 12:37:57 +0800582
583/* FLASH: icache cacheable, but dcache-inhibit and guarded */
Joe Hershberger8d858082011-10-11 23:57:18 -0500584#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500585 | BATL_PP_RW \
Joe Hershberger8d858082011-10-11 23:57:18 -0500586 | BATL_MEMCOHERENCE)
587#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \
588 | BATU_BL_32M \
589 | BATU_VS \
590 | BATU_VP)
591#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500592 | BATL_PP_RW \
Joe Hershberger8d858082011-10-11 23:57:18 -0500593 | BATL_CACHEINHIBIT \
594 | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200595#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
Dave Liu19580e62007-09-18 12:37:57 +0800596
597/* Stack in dcache: cacheable, no memory coherence */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500598#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
Joe Hershberger8d858082011-10-11 23:57:18 -0500599#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
600 | BATU_BL_128K \
601 | BATU_VS \
602 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200603#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
604#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
Dave Liu19580e62007-09-18 12:37:57 +0800605
606#ifdef CONFIG_PCI
607/* PCI MEM space: cacheable */
Joe Hershberger8d858082011-10-11 23:57:18 -0500608#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500609 | BATL_PP_RW \
Joe Hershberger8d858082011-10-11 23:57:18 -0500610 | BATL_MEMCOHERENCE)
611#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \
612 | BATU_BL_256M \
613 | BATU_VS \
614 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200615#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
616#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
Dave Liu19580e62007-09-18 12:37:57 +0800617/* PCI MMIO space: cache-inhibit and guarded */
Joe Hershberger8d858082011-10-11 23:57:18 -0500618#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500619 | BATL_PP_RW \
Joe Hershberger8d858082011-10-11 23:57:18 -0500620 | BATL_CACHEINHIBIT \
621 | BATL_GUARDEDSTORAGE)
622#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \
623 | BATU_BL_256M \
624 | BATU_VS \
625 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200626#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
627#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Dave Liu19580e62007-09-18 12:37:57 +0800628#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200629#define CONFIG_SYS_IBAT6L (0)
630#define CONFIG_SYS_IBAT6U (0)
631#define CONFIG_SYS_IBAT7L (0)
632#define CONFIG_SYS_IBAT7U (0)
633#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
634#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
635#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
636#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Dave Liu19580e62007-09-18 12:37:57 +0800637#endif
638
Dave Liu19580e62007-09-18 12:37:57 +0800639#if defined(CONFIG_CMD_KGDB)
640#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
Dave Liu19580e62007-09-18 12:37:57 +0800641#endif
642
643/*
644 * Environment Configuration
645 */
646
647#define CONFIG_ENV_OVERWRITE
648
649#if defined(CONFIG_TSEC_ENET)
650#define CONFIG_HAS_ETH0
Dave Liu19580e62007-09-18 12:37:57 +0800651#define CONFIG_HAS_ETH1
Dave Liu19580e62007-09-18 12:37:57 +0800652#endif
653
654#define CONFIG_BAUDRATE 115200
655
Kim Phillips79f516b2009-08-21 16:34:38 -0500656#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
Dave Liu19580e62007-09-18 12:37:57 +0800657
Dave Liu19580e62007-09-18 12:37:57 +0800658#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
659
660#define CONFIG_EXTRA_ENV_SETTINGS \
Joe Hershberger8d858082011-10-11 23:57:18 -0500661 "netdev=eth0\0" \
662 "consoledev=ttyS0\0" \
663 "ramdiskaddr=1000000\0" \
664 "ramdiskfile=ramfs.83xx\0" \
665 "fdtaddr=780000\0" \
666 "fdtfile=mpc8379_mds.dtb\0" \
667 ""
Dave Liu19580e62007-09-18 12:37:57 +0800668
669#define CONFIG_NFSBOOTCOMMAND \
Joe Hershberger8d858082011-10-11 23:57:18 -0500670 "setenv bootargs root=/dev/nfs rw " \
671 "nfsroot=$serverip:$rootpath " \
672 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
673 "$netdev:off " \
674 "console=$consoledev,$baudrate $othbootargs;" \
675 "tftp $loadaddr $bootfile;" \
676 "tftp $fdtaddr $fdtfile;" \
677 "bootm $loadaddr - $fdtaddr"
Dave Liu19580e62007-09-18 12:37:57 +0800678
679#define CONFIG_RAMBOOTCOMMAND \
Joe Hershberger8d858082011-10-11 23:57:18 -0500680 "setenv bootargs root=/dev/ram rw " \
681 "console=$consoledev,$baudrate $othbootargs;" \
682 "tftp $ramdiskaddr $ramdiskfile;" \
683 "tftp $loadaddr $bootfile;" \
684 "tftp $fdtaddr $fdtfile;" \
685 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Dave Liu19580e62007-09-18 12:37:57 +0800686
Dave Liu19580e62007-09-18 12:37:57 +0800687#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
688
689#endif /* __CONFIG_H */