Graeme Russ | d47ab0e | 2011-12-23 16:51:29 +1100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2011 |
| 3 | * Graeme Russ, <graeme.russ@gmail.com> |
| 4 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
Graeme Russ | d47ab0e | 2011-12-23 16:51:29 +1100 | [diff] [blame] | 6 | */ |
| 7 | #include <common.h> |
Simon Glass | f697d52 | 2013-02-28 19:26:15 +0000 | [diff] [blame] | 8 | #include <fdtdec.h> |
Gabe Black | 8313315 | 2012-11-03 11:41:23 +0000 | [diff] [blame] | 9 | #include <spi.h> |
Bin Meng | 3b621cc | 2015-01-22 11:29:41 +0800 | [diff] [blame] | 10 | #include <asm/errno.h> |
Simon Glass | db55bd7 | 2015-01-01 16:18:11 -0700 | [diff] [blame] | 11 | #include <asm/mtrr.h> |
Simon Glass | 86cfb6b | 2013-03-05 14:39:54 +0000 | [diff] [blame] | 12 | #include <asm/sections.h> |
Graeme Russ | d47ab0e | 2011-12-23 16:51:29 +1100 | [diff] [blame] | 13 | |
| 14 | DECLARE_GLOBAL_DATA_PTR; |
| 15 | |
Simon Glass | 5e98947 | 2013-02-28 19:26:10 +0000 | [diff] [blame] | 16 | /* Get the top of usable RAM */ |
| 17 | __weak ulong board_get_usable_ram_top(ulong total_size) |
Graeme Russ | a1d57b7 | 2011-12-23 21:14:22 +1100 | [diff] [blame] | 18 | { |
Simon Glass | 5e98947 | 2013-02-28 19:26:10 +0000 | [diff] [blame] | 19 | return gd->ram_size; |
| 20 | } |
| 21 | |
| 22 | int calculate_relocation_address(void) |
| 23 | { |
| 24 | const ulong uboot_size = (uintptr_t)&__bss_end - |
| 25 | (uintptr_t)&__text_start; |
| 26 | ulong total_size; |
Graeme Russ | a1d57b7 | 2011-12-23 21:14:22 +1100 | [diff] [blame] | 27 | ulong dest_addr; |
Simon Glass | f697d52 | 2013-02-28 19:26:15 +0000 | [diff] [blame] | 28 | ulong fdt_size = 0; |
Graeme Russ | a1d57b7 | 2011-12-23 21:14:22 +1100 | [diff] [blame] | 29 | |
Simon Glass | f697d52 | 2013-02-28 19:26:15 +0000 | [diff] [blame] | 30 | #if defined(CONFIG_OF_SEPARATE) && defined(CONFIG_OF_CONTROL) |
| 31 | if (gd->fdt_blob) |
| 32 | fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32); |
| 33 | #endif |
Simon Glass | 5e98947 | 2013-02-28 19:26:10 +0000 | [diff] [blame] | 34 | total_size = ALIGN(uboot_size, 1 << 12) + CONFIG_SYS_MALLOC_LEN + |
Simon Glass | f697d52 | 2013-02-28 19:26:15 +0000 | [diff] [blame] | 35 | CONFIG_SYS_STACK_SIZE + fdt_size; |
Simon Glass | 5e98947 | 2013-02-28 19:26:10 +0000 | [diff] [blame] | 36 | |
Simon Glass | f697d52 | 2013-02-28 19:26:15 +0000 | [diff] [blame] | 37 | dest_addr = board_get_usable_ram_top(total_size); |
Graeme Russ | a1d57b7 | 2011-12-23 21:14:22 +1100 | [diff] [blame] | 38 | /* |
| 39 | * NOTE: All destination address are rounded down to 16-byte |
| 40 | * boundary to satisfy various worst-case alignment |
| 41 | * requirements |
| 42 | */ |
Simon Glass | f697d52 | 2013-02-28 19:26:15 +0000 | [diff] [blame] | 43 | dest_addr &= ~15; |
Graeme Russ | a1d57b7 | 2011-12-23 21:14:22 +1100 | [diff] [blame] | 44 | |
Simon Glass | f697d52 | 2013-02-28 19:26:15 +0000 | [diff] [blame] | 45 | #if defined(CONFIG_OF_SEPARATE) && defined(CONFIG_OF_CONTROL) |
| 46 | /* |
| 47 | * If the device tree is sitting immediate above our image then we |
| 48 | * must relocate it. If it is embedded in the data section, then it |
| 49 | * will be relocated with other data. |
| 50 | */ |
| 51 | if (gd->fdt_blob) { |
| 52 | dest_addr -= fdt_size; |
Simon Glass | 1938f4a | 2013-03-11 06:49:53 +0000 | [diff] [blame] | 53 | gd->new_fdt = (void *)dest_addr; |
Simon Glass | f697d52 | 2013-02-28 19:26:15 +0000 | [diff] [blame] | 54 | dest_addr &= ~15; |
| 55 | } |
| 56 | #endif |
Simon Glass | 5e98947 | 2013-02-28 19:26:10 +0000 | [diff] [blame] | 57 | /* U-Boot is below the FDT */ |
| 58 | dest_addr -= uboot_size; |
| 59 | dest_addr &= ~((1 << 12) - 1); |
Graeme Russ | a1d57b7 | 2011-12-23 21:14:22 +1100 | [diff] [blame] | 60 | gd->relocaddr = dest_addr; |
Simon Glass | 5e98947 | 2013-02-28 19:26:10 +0000 | [diff] [blame] | 61 | gd->reloc_off = dest_addr - (uintptr_t)&__text_start; |
Graeme Russ | a1d57b7 | 2011-12-23 21:14:22 +1100 | [diff] [blame] | 62 | |
Gabe Black | 32f9873 | 2012-11-03 11:41:24 +0000 | [diff] [blame] | 63 | /* Stack is at the bottom, so it can grow down */ |
| 64 | gd->start_addr_sp = dest_addr - CONFIG_SYS_MALLOC_LEN; |
| 65 | |
Graeme Russ | a1d57b7 | 2011-12-23 21:14:22 +1100 | [diff] [blame] | 66 | return 0; |
| 67 | } |
| 68 | |
Graeme Russ | a1d57b7 | 2011-12-23 21:14:22 +1100 | [diff] [blame] | 69 | int init_cache_f_r(void) |
| 70 | { |
Simon Glass | db55bd7 | 2015-01-01 16:18:11 -0700 | [diff] [blame] | 71 | #if defined(CONFIG_X86_RESET_VECTOR) & !defined(CONFIG_HAVE_FSP) |
| 72 | int ret; |
| 73 | |
| 74 | ret = mtrr_commit(false); |
Bin Meng | 3b621cc | 2015-01-22 11:29:41 +0800 | [diff] [blame] | 75 | /* If MTRR MSR is not implemented by the processor, just ignore it */ |
| 76 | if (ret && ret != -ENOSYS) |
Simon Glass | db55bd7 | 2015-01-01 16:18:11 -0700 | [diff] [blame] | 77 | return ret; |
| 78 | #endif |
Graeme Russ | a1d57b7 | 2011-12-23 21:14:22 +1100 | [diff] [blame] | 79 | /* Initialise the CPU cache(s) */ |
| 80 | return init_cache(); |
| 81 | } |
| 82 | |
Graeme Russ | d47ab0e | 2011-12-23 16:51:29 +1100 | [diff] [blame] | 83 | bd_t bd_data; |
| 84 | |
| 85 | int init_bd_struct_r(void) |
| 86 | { |
| 87 | gd->bd = &bd_data; |
| 88 | memset(gd->bd, 0, sizeof(bd_t)); |
| 89 | |
| 90 | return 0; |
| 91 | } |