blob: 3a4815499faa13e30267eadb07f10213f02d603f [file] [log] [blame]
Joe Hamman8ac27322007-08-09 15:10:53 -05001/*
2 * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
3 * Copyright 2007 Embedded Specialties, Inc.
4 * Joe Hamman joe.hamman@embeddedspecialties.com
5 *
6 * Copyright 2004 Freescale Semiconductor.
7 * Jeff Brown
8 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
9 *
10 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
11 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020012 * SPDX-License-Identifier: GPL-2.0+
Joe Hamman8ac27322007-08-09 15:10:53 -050013 */
14
15#include <common.h>
16#include <command.h>
17#include <pci.h>
18#include <asm/processor.h>
19#include <asm/immap_86xx.h>
Kumar Galac8514622009-04-02 13:22:48 -050020#include <asm/fsl_pci.h>
Kumar Gala9bd4e592008-08-26 15:01:37 -050021#include <asm/fsl_ddr_sdram.h>
Kumar Gala5d27e022010-12-15 04:55:20 -060022#include <asm/fsl_serdes.h>
Jon Loeliger13f54332008-02-18 14:01:56 -060023#include <libfdt.h>
24#include <fdt_support.h>
Joe Hamman8ac27322007-08-09 15:10:53 -050025
Joe Hamman8ac27322007-08-09 15:10:53 -050026long int fixed_sdram (void);
27
28int board_early_init_f (void)
29{
30 return 0;
31}
32
33int checkboard (void)
34{
35 puts ("Board: Wind River SBC8641D\n");
36
Joe Hamman8ac27322007-08-09 15:10:53 -050037 return 0;
38}
39
Becky Bruce9973e3c2008-06-09 16:03:40 -050040phys_size_t initdram (int board_type)
Joe Hamman8ac27322007-08-09 15:10:53 -050041{
42 long dram_size = 0;
43
44#if defined(CONFIG_SPD_EEPROM)
Kumar Gala9bd4e592008-08-26 15:01:37 -050045 dram_size = fsl_ddr_sdram();
Joe Hamman8ac27322007-08-09 15:10:53 -050046#else
47 dram_size = fixed_sdram ();
48#endif
49
Wolfgang Denk21cd5812011-07-25 10:13:53 +020050 debug (" DDR: ");
Joe Hamman8ac27322007-08-09 15:10:53 -050051 return dram_size;
52}
53
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020054#if defined(CONFIG_SYS_DRAM_TEST)
Joe Hamman8ac27322007-08-09 15:10:53 -050055int testdram (void)
56{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
58 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
Joe Hamman8ac27322007-08-09 15:10:53 -050059 uint *p;
60
61 puts ("SDRAM test phase 1:\n");
62 for (p = pstart; p < pend; p++)
63 *p = 0xaaaaaaaa;
64
65 for (p = pstart; p < pend; p++) {
66 if (*p != 0xaaaaaaaa) {
67 printf ("SDRAM test fails at: %08x\n", (uint) p);
68 return 1;
69 }
70 }
71
72 puts ("SDRAM test phase 2:\n");
73 for (p = pstart; p < pend; p++)
74 *p = 0x55555555;
75
76 for (p = pstart; p < pend; p++) {
77 if (*p != 0x55555555) {
78 printf ("SDRAM test fails at: %08x\n", (uint) p);
79 return 1;
80 }
81 }
82
83 puts ("SDRAM test passed.\n");
84 return 0;
85}
86#endif
87
88#if !defined(CONFIG_SPD_EEPROM)
89/*
90 * Fixed sdram init -- doesn't use serial presence detect.
91 */
92long int fixed_sdram (void)
93{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#if !defined(CONFIG_SYS_RAMBOOT)
95 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
Joe Hamman8ac27322007-08-09 15:10:53 -050096 volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
97
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
99 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
100 ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS;
101 ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS;
102 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
103 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
104 ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG;
105 ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG;
106 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
107 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
108 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
109 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
Peter Tysere7ee23e2009-07-17 10:14:45 -0500110 ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
Peter Tysere7ee23e2009-07-17 10:14:45 -0500112 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
114 ddr->sdram_mode_cntl = CONFIG_SYS_DDR_MODE_CTL;
115 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
116 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
117 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
Joe Hamman8ac27322007-08-09 15:10:53 -0500118
119 asm ("sync;isync");
120
121 udelay (500);
122
Peter Tysere7ee23e2009-07-17 10:14:45 -0500123 ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B;
Joe Hamman8ac27322007-08-09 15:10:53 -0500124 asm ("sync; isync");
125
126 udelay (500);
127 ddr = &immap->im_ddr2;
128
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129 ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS;
130 ddr->cs1_bnds = CONFIG_SYS_DDR2_CS1_BNDS;
131 ddr->cs2_bnds = CONFIG_SYS_DDR2_CS2_BNDS;
132 ddr->cs3_bnds = CONFIG_SYS_DDR2_CS3_BNDS;
133 ddr->cs0_config = CONFIG_SYS_DDR2_CS0_CONFIG;
134 ddr->cs1_config = CONFIG_SYS_DDR2_CS1_CONFIG;
135 ddr->cs2_config = CONFIG_SYS_DDR2_CS2_CONFIG;
136 ddr->cs3_config = CONFIG_SYS_DDR2_CS3_CONFIG;
137 ddr->timing_cfg_3 = CONFIG_SYS_DDR2_EXT_REFRESH;
138 ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0;
139 ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1;
140 ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2;
Peter Tysere7ee23e2009-07-17 10:14:45 -0500141 ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142 ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
Peter Tysere7ee23e2009-07-17 10:14:45 -0500143 ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144 ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
145 ddr->sdram_mode_cntl = CONFIG_SYS_DDR2_MODE_CTL;
146 ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
147 ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT;
148 ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL;
Joe Hamman8ac27322007-08-09 15:10:53 -0500149
150 asm ("sync;isync");
151
152 udelay (500);
153
Peter Tysere7ee23e2009-07-17 10:14:45 -0500154 ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B;
Joe Hamman8ac27322007-08-09 15:10:53 -0500155 asm ("sync; isync");
156
157 udelay (500);
158#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
Joe Hamman8ac27322007-08-09 15:10:53 -0500160}
161#endif /* !defined(CONFIG_SPD_EEPROM) */
162
163#if defined(CONFIG_PCI)
164/*
165 * Initialize PCI Devices, report devices found.
166 */
167
Joe Hammancca34962007-08-11 06:54:58 -0500168void pci_init_board(void)
Joe Hamman8ac27322007-08-09 15:10:53 -0500169{
Kumar Galac51136e2010-12-17 10:26:44 -0600170 fsl_pcie_init_board(0);
Joe Hamman8ac27322007-08-09 15:10:53 -0500171}
Kumar Galac51136e2010-12-17 10:26:44 -0600172#endif /* CONFIG_PCI */
Joe Hamman8ac27322007-08-09 15:10:53 -0500173
Jon Loeliger13f54332008-02-18 14:01:56 -0600174
175#if defined(CONFIG_OF_BOARD_SETUP)
Kumar Galac2083e02008-10-22 14:38:55 -0500176void ft_board_setup (void *blob, bd_t *bd)
Joe Hamman8ac27322007-08-09 15:10:53 -0500177{
Jon Loeliger13f54332008-02-18 14:01:56 -0600178 ft_cpu_setup(blob, bd);
Joe Hamman8ac27322007-08-09 15:10:53 -0500179
Kumar Gala6525d512010-07-08 22:37:44 -0500180 FT_FSL_PCI_SETUP;
Joe Hamman8ac27322007-08-09 15:10:53 -0500181}
182#endif
183
184void sbc8641d_reset_board (void)
185{
186 puts ("Resetting board....\n");
187}
188
189/*
190 * get_board_sys_clk
191 * Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ
192 */
193
194unsigned long get_board_sys_clk (ulong dummy)
195{
196 int i;
197 ulong val = 0;
198
199 i = 5;
200 i &= 0x07;
201
202 switch (i) {
203 case 0:
204 val = 33000000;
205 break;
206 case 1:
207 val = 40000000;
208 break;
209 case 2:
210 val = 50000000;
211 break;
212 case 3:
213 val = 66000000;
214 break;
215 case 4:
216 val = 83000000;
217 break;
218 case 5:
219 val = 100000000;
220 break;
221 case 6:
222 val = 134000000;
223 break;
224 case 7:
225 val = 166000000;
226 break;
227 }
228
229 return val;
230}
Peter Tyser4ef630d2009-02-05 11:25:25 -0600231
232void board_reset(void)
233{
234#ifdef CONFIG_SYS_RESET_ADDRESS
235 ulong addr = CONFIG_SYS_RESET_ADDRESS;
236
237 /* flush and disable I/D cache */
238 __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
239 __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
240 __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
241 __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
242 __asm__ __volatile__ ("sync");
243 __asm__ __volatile__ ("mtspr 1008, 4");
244 __asm__ __volatile__ ("isync");
245 __asm__ __volatile__ ("sync");
246 __asm__ __volatile__ ("mtspr 1008, 5");
247 __asm__ __volatile__ ("isync");
248 __asm__ __volatile__ ("sync");
249
250 /*
251 * SRR0 has system reset vector, SRR1 has default MSR value
252 * rfi restores MSR from SRR1 and sets the PC to the SRR0 value
253 */
254 __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
255 __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
256 __asm__ __volatile__ ("mtspr 27, 4");
257 __asm__ __volatile__ ("rfi");
258#endif
259}