blob: e76a04b26253f48f608e87542037e13ec32f38dd [file] [log] [blame]
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +00001/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +00005 */
6
7/*
8 * BSC9132 QDS board configuration file
9 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14#ifdef CONFIG_BSC9132QDS
15#define CONFIG_BSC9132
16#endif
17
18#define CONFIG_MISC_INIT_R
19
20#ifdef CONFIG_SDCARD
21#define CONFIG_RAMBOOT_SDCARD
22#define CONFIG_SYS_RAMBOOT
23#define CONFIG_SYS_EXTRA_ENV_RELOC
24#define CONFIG_SYS_TEXT_BASE 0x11000000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053025#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000026#endif
27#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 1
28#ifdef CONFIG_SPIFLASH
29#define CONFIG_RAMBOOT_SPIFLASH
30#define CONFIG_SYS_RAMBOOT
31#define CONFIG_SYS_EXTRA_ENV_RELOC
32#define CONFIG_SYS_TEXT_BASE 0x11000000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053033#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000034#endif
Aneesh Bansalbea3cbb2014-03-12 22:00:18 +053035#ifdef CONFIG_NAND_SECBOOT
36#define CONFIG_RAMBOOT_NAND
37#define CONFIG_SYS_RAMBOOT
38#define CONFIG_SYS_EXTRA_ENV_RELOC
39#define CONFIG_SYS_TEXT_BASE 0x11000000
40#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
41#endif
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000042
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +053043#ifdef CONFIG_NAND
44#define CONFIG_SPL
45#define CONFIG_SPL_INIT_MINIMAL
46#define CONFIG_SPL_SERIAL_SUPPORT
47#define CONFIG_SPL_NAND_SUPPORT
Prabhakar Kushwahafbe76ae2013-12-11 12:42:11 +053048#define CONFIG_SPL_NAND_BOOT
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +053049#define CONFIG_SPL_FLUSH_IMAGE
50#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
51
52#define CONFIG_SYS_TEXT_BASE 0x00201000
53#define CONFIG_SPL_TEXT_BASE 0xFFFFE000
54#define CONFIG_SPL_MAX_SIZE 8192
55#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
56#define CONFIG_SPL_RELOC_STACK 0x00100000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053057#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +053058#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
59#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
60#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
61#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
62#endif
63
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000064#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053065#define CONFIG_SYS_TEXT_BASE 0x8ff40000
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000066#endif
67
68#ifndef CONFIG_RESET_VECTOR_ADDRESS
69#define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc
70#endif
71
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +053072#ifdef CONFIG_SPL_BUILD
73#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
74#else
75#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000076#endif
77
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000078/* High Level Configuration Options */
79#define CONFIG_BOOKE /* BOOKE */
80#define CONFIG_E500 /* BOOKE e500 family */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000081#define CONFIG_FSL_IFC /* Enable IFC Support */
82#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
83
84#define CONFIG_PCI /* Enable PCI/PCIE */
85#if defined(CONFIG_PCI)
86#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
87#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
Gabor Juhos842033e2013-05-30 07:06:12 +000088#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000089#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
90#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
91
92#define CONFIG_CMD_NET
93#define CONFIG_CMD_PCI
94
95#define CONFIG_E1000 /* E1000 pci Ethernet card*/
96
97/*
98 * PCI Windows
99 * Memory space is mapped 1-1, but I/O space must start from 0.
100 */
101/* controller 1, Slot 1, tgtid 1, Base address a000 */
102#define CONFIG_SYS_PCIE1_NAME "PCIe Slot"
103#define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
104#define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
105#define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
106#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
107#define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000
108#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
109#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
110#define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000
111
112#define CONFIG_PCI_PNP /* do pci plug-and-play */
113
114#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
115#define CONFIG_DOS_PARTITION
116#endif
117
118#define CONFIG_FSL_LAW /* Use common FSL init code */
119#define CONFIG_ENV_OVERWRITE
120#define CONFIG_TSEC_ENET /* ethernet */
121
122#if defined(CONFIG_SYS_CLK_100_DDR_100)
123#define CONFIG_SYS_CLK_FREQ 100000000
124#define CONFIG_DDR_CLK_FREQ 100000000
125#elif defined(CONFIG_SYS_CLK_100_DDR_133)
126#define CONFIG_SYS_CLK_FREQ 100000000
127#define CONFIG_DDR_CLK_FREQ 133000000
128#endif
129
130#define CONFIG_MP
131
132#define CONFIG_HWCONFIG
133/*
134 * These can be toggled for performance analysis, otherwise use default.
135 */
136#define CONFIG_L2_CACHE /* toggle L2 cache */
137#define CONFIG_BTB /* enable branch predition */
138
139#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
140#define CONFIG_SYS_MEMTEST_END 0x01ffffff
141
142/* DDR Setup */
York Sun5614e712013-09-30 09:22:09 -0700143#define CONFIG_SYS_FSL_DDR3
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000144#define CONFIG_SYS_SPD_BUS_NUM 0
145#define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */
146#define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */
147#define CONFIG_FSL_DDR_INTERACTIVE
148
149#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
150
151#define CONFIG_SYS_SDRAM_SIZE (1024)
152#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
153#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
154
155#define CONFIG_DIMM_SLOTS_PER_CTLR 1
156
157/* DDR3 Controller Settings */
158#define CONFIG_CHIP_SELECTS_PER_CTRL 1
159#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
160#define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302
161#define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302
162#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
163#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
164#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
165#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
166#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
167#define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F
168
169#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
170#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
171#define CONFIG_SYS_DDR_RCW_1 0x00000000
172#define CONFIG_SYS_DDR_RCW_2 0x00000000
173#define CONFIG_SYS_DDR_CONTROL_800 0x470C0000
174#define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050
175#define CONFIG_SYS_DDR_TIMING_4_800 0x00220001
176#define CONFIG_SYS_DDR_TIMING_5_800 0x03402400
177
178#define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008
179#define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010
180#define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001
181#define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400
182
183#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
184#define CONFIG_SYS_DDR_TIMING_0_800 0x00330004
185#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846
186#define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF
187#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
188#define CONFIG_SYS_DDR_MODE_1_800 0x40461520
189#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
190#define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000
191#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608
192
193#define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000
194#define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104
195#define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45
196#define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114
197#define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000
198#define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50
199#define CONFIG_SYS_DDR_MODE_2_1333 0x00100000
200#define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513
201#define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607
202
203/*FIXME: the following params are constant w.r.t diff freq
204combinations. this should be removed later
205*/
206#if CONFIG_DDR_CLK_FREQ == 100000000
207#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
208#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800
209#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
210#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
211#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
212#elif CONFIG_DDR_CLK_FREQ == 133000000
213#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333
214#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333
215#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333
216#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333
217#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333
218#else
219#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
220#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800
221#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
222#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
223#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
224#endif
225
226
227/* relocated CCSRBAR */
228#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
229#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
230
231#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
232
Priyanka Jain64501c62013-07-02 09:21:04 +0530233/* DSP CCSRBAR */
234#define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
235#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
236
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000237/*
238 * IFC Definitions
239 */
240/* NOR Flash on IFC */
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +0530241
242#ifdef CONFIG_SPL_BUILD
243#define CONFIG_SYS_NO_FLASH
244#endif
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000245#define CONFIG_SYS_FLASH_BASE 0x88000000
246#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */
247
248#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
249
250#define CONFIG_SYS_NOR_CSPR 0x88000101
251#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
252#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5)
253/* NOR Flash Timing Params */
254
255#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \
256 | FTIM0_NOR_TEADC(0x03) \
257 | FTIM0_NOR_TAVDS(0x00) \
258 | FTIM0_NOR_TEAHC(0x0f))
259#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \
260 | FTIM1_NOR_TRAD_NOR(0x09) \
261 | FTIM1_NOR_TSEQRAD_NOR(0x09))
262#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \
263 | FTIM2_NOR_TCH(0x4) \
264 | FTIM2_NOR_TWPH(0x7) \
265 | FTIM2_NOR_TWP(0x1e))
266#define CONFIG_SYS_NOR_FTIM3 0x0
267
268#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
269#define CONFIG_SYS_FLASH_QUIET_TEST
270#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
271#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
272
273#undef CONFIG_SYS_FLASH_CHECKSUM
274#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
275#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
276
277/* CFI for NOR Flash */
278#define CONFIG_FLASH_CFI_DRIVER
279#define CONFIG_SYS_FLASH_CFI
280#define CONFIG_SYS_FLASH_EMPTY_INFO
281#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
282
283/* NAND Flash on IFC */
284#define CONFIG_SYS_NAND_BASE 0xff800000
285#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
286
287#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
288 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
289 | CSPR_MSEL_NAND /* MSEL = NAND */ \
290 | CSPR_V)
291#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
292
293#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
294 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
295 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
296 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \
297 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
298 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
299 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
300
301/* NAND Flash Timing Params */
302#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \
303 | FTIM0_NAND_TWP(0x05) \
304 | FTIM0_NAND_TWCHT(0x02) \
305 | FTIM0_NAND_TWH(0x04))
306#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \
307 | FTIM1_NAND_TWBE(0x1e) \
308 | FTIM1_NAND_TRR(0x07) \
309 | FTIM1_NAND_TRP(0x05))
310#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \
311 | FTIM2_NAND_TREH(0x04) \
312 | FTIM2_NAND_TWHRE(0x11))
313#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
314
315#define CONFIG_SYS_NAND_DDR_LAW 11
316
317/* NAND */
318#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
319#define CONFIG_SYS_MAX_NAND_DEVICE 1
320#define CONFIG_MTD_NAND_VERIFY_WRITE
321#define CONFIG_CMD_NAND
322
323#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
324
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +0530325#ifndef CONFIG_SPL_BUILD
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000326#define CONFIG_FSL_QIXIS
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +0530327#endif
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000328#ifdef CONFIG_FSL_QIXIS
329#define CONFIG_SYS_FPGA_BASE 0xffb00000
330#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
331#define QIXIS_BASE CONFIG_SYS_FPGA_BASE
332#define QIXIS_LBMAP_SWITCH 9
333#define QIXIS_LBMAP_MASK 0x07
334#define QIXIS_LBMAP_SHIFT 0
335#define QIXIS_LBMAP_DFLTBANK 0x00
336#define QIXIS_LBMAP_ALTBANK 0x04
337#define QIXIS_RST_CTL_RESET 0x83
338#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
339#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
340#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
341
342#define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE
343
344#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \
345 | CSPR_PORT_SIZE_8 \
346 | CSPR_MSEL_GPCM \
347 | CSPR_V)
348#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
349#define CONFIG_SYS_CSOR2 0x0
350/* CPLD Timing parameters for IFC CS3 */
351#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
352 FTIM0_GPCM_TEADC(0x0e) | \
353 FTIM0_GPCM_TEAHC(0x0e))
354#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
355 FTIM1_GPCM_TRAD(0x1f))
356#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
357 FTIM2_GPCM_TCH(0x0) | \
358 FTIM2_GPCM_TWP(0x1f))
359#define CONFIG_SYS_CS2_FTIM3 0x0
360#endif
361
362/* Set up IFC registers for boot location NOR/NAND */
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +0530363#if defined(CONFIG_NAND)
364#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
365#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
366#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
367#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
368#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
369#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
370#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
371#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
372#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
373#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
374#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
375#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
376#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
377#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
378#else
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000379#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
380#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
381#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
382#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
383#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
384#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
385#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
386#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
387#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
388#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
389#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
390#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
391#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
392#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +0530393#endif
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000394
395#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
396#define CONFIG_BOARD_EARLY_INIT_R
397
398#define CONFIG_SYS_INIT_RAM_LOCK
399#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
400#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
401
402#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
403 - GENERATED_GBL_DATA_SIZE)
404#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
405
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530406#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000407#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
408
409/* Serial Port */
410#define CONFIG_CONS_INDEX 1
411#undef CONFIG_SERIAL_SOFTWARE_FIFO
412#define CONFIG_SYS_NS16550
413#define CONFIG_SYS_NS16550_SERIAL
414#define CONFIG_SYS_NS16550_REG_SIZE 1
415#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +0530416#ifdef CONFIG_SPL_BUILD
417#define CONFIG_NS16550_MIN_FUNCTIONS
418#endif
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000419
420#define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */
421#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
422
423#define CONFIG_SYS_BAUDRATE_TABLE \
424 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
425
426#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
427#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
428#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700)
429#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800)
430
431/* Use the HUSH parser */
432#define CONFIG_SYS_HUSH_PARSER /* hush parser */
433#ifdef CONFIG_SYS_HUSH_PARSER
434#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
435#endif
436
437/*
438 * Pass open firmware flat tree
439 */
440#define CONFIG_OF_LIBFDT
441#define CONFIG_OF_BOARD_SETUP
442#define CONFIG_OF_STDOUT_VIA_ALIAS
443
444/* new uImage format support */
445#define CONFIG_FIT
446#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
447
Heiko Schocher00f792e2012-10-24 13:48:22 +0200448#define CONFIG_SYS_I2C
449#define CONFIG_SYS_I2C_FSL
450#define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/
451#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
452#define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/
453#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
454#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
455#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000456
457/* I2C EEPROM */
458#define CONFIG_ID_EEPROM
459#ifdef CONFIG_ID_EEPROM
460#define CONFIG_SYS_I2C_EEPROM_NXID
461#endif
462#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
463#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
464#define CONFIG_SYS_EEPROM_BUS_NUM 0
465
466/* enable read and write access to EEPROM */
467#define CONFIG_CMD_EEPROM
468#define CONFIG_SYS_I2C_MULTI_EEPROMS
469#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
470#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
471#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
472
473/* I2C FPGA */
474#define CONFIG_I2C_FPGA
475#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
476
477#define CONFIG_RTC_DS3231
478#define CONFIG_SYS_I2C_RTC_ADDR 0x68
479
480/*
481 * SPI interface will not be available in case of NAND boot SPI CS0 will be
482 * used for SLIC
483 */
484/* eSPI - Enhanced SPI */
485#define CONFIG_FSL_ESPI /* SPI */
486#ifdef CONFIG_FSL_ESPI
487#define CONFIG_SPI_FLASH
488#define CONFIG_SPI_FLASH_SPANSION
489#define CONFIG_CMD_SF
490#define CONFIG_SF_DEFAULT_SPEED 10000000
491#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
492#endif
493
494#if defined(CONFIG_TSEC_ENET)
495
496#define CONFIG_MII /* MII PHY management */
497#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
498#define CONFIG_TSEC1 1
499#define CONFIG_TSEC1_NAME "eTSEC1"
500#define CONFIG_TSEC2 1
501#define CONFIG_TSEC2_NAME "eTSEC2"
502
503#define TSEC1_PHY_ADDR 0
504#define TSEC2_PHY_ADDR 1
505
506#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
507#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
508
509#define TSEC1_PHYIDX 0
510#define TSEC2_PHYIDX 0
511
512#define CONFIG_ETHPRIME "eTSEC1"
513
514#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
515
516/* TBI PHY configuration for SGMII mode */
517#define CONFIG_TSEC_TBICR_SETTINGS ( \
518 TBICR_PHY_RESET \
519 | TBICR_ANEG_ENABLE \
520 | TBICR_FULL_DUPLEX \
521 | TBICR_SPEED1_SET \
522 )
523
524#endif /* CONFIG_TSEC_ENET */
525
526#define CONFIG_MMC
527#ifdef CONFIG_MMC
528#define CONFIG_CMD_MMC
529#define CONFIG_DOS_PARTITION
530#define CONFIG_FSL_ESDHC
531#define CONFIG_GENERIC_MMC
532#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
533#endif
534
535#define CONFIG_USB_EHCI /* USB */
536#ifdef CONFIG_USB_EHCI
537#define CONFIG_CMD_USB
538#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
539#define CONFIG_USB_EHCI_FSL
540#define CONFIG_USB_STORAGE
541#define CONFIG_HAS_FSL_DR_USB
542#endif
543
544/*
545 * Environment
546 */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000547#if defined(CONFIG_RAMBOOT_SDCARD)
548#define CONFIG_ENV_IS_IN_MMC
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530549#define CONFIG_FSL_FIXED_MMC_LOCATION
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000550#define CONFIG_SYS_MMC_ENV_DEV 0
551#define CONFIG_ENV_SIZE 0x2000
552#elif defined(CONFIG_RAMBOOT_SPIFLASH)
553#define CONFIG_ENV_IS_IN_SPI_FLASH
554#define CONFIG_ENV_SPI_BUS 0
555#define CONFIG_ENV_SPI_CS 0
556#define CONFIG_ENV_SPI_MAX_HZ 10000000
557#define CONFIG_ENV_SPI_MODE 0
558#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
559#define CONFIG_ENV_SECT_SIZE 0x10000
560#define CONFIG_ENV_SIZE 0x2000
Aneesh Bansalbea3cbb2014-03-12 22:00:18 +0530561#elif defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +0530562#define CONFIG_ENV_IS_IN_NAND
563#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530564#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +0530565#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
566#elif defined(CONFIG_SYS_RAMBOOT)
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000567#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
568#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
569#define CONFIG_ENV_SIZE 0x2000
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000570#else
571#define CONFIG_ENV_IS_IN_FLASH
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000572#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000573#define CONFIG_ENV_SIZE 0x2000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530574#define CONFIG_ENV_SECT_SIZE 0x20000
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000575#endif
576
577#define CONFIG_LOADS_ECHO /* echo on for serial download */
578#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
579
580/*
581 * Command line configuration.
582 */
583#include <config_cmd_default.h>
584
585#define CONFIG_CMD_DATE
586#define CONFIG_CMD_DHCP
587#define CONFIG_CMD_ELF
588#define CONFIG_CMD_ERRATA
589#define CONFIG_CMD_I2C
590#define CONFIG_CMD_IRQ
591#define CONFIG_CMD_MII
592#define CONFIG_CMD_PING
593#define CONFIG_CMD_SETEXPR
594#define CONFIG_CMD_REGINFO
595
596#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
597#define CONFIG_CMD_EXT2
598#define CONFIG_CMD_FAT
599#define CONFIG_DOS_PARTITION
600#endif
601
602/*
603 * Miscellaneous configurable options
604 */
605#define CONFIG_SYS_LONGHELP /* undef to save memory */
606#define CONFIG_CMDLINE_EDITING /* Command-line editing */
607#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
608#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000609
610#if defined(CONFIG_CMD_KGDB)
611#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
612#else
613#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
614#endif
615#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
616 /* Print Buffer Size */
617#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
618#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000619
620
621/*
622 * For booting Linux, the board info and command line data
623 * have to be in the first 64 MB of memory, since this is
624 * the maximum mapped by the Linux kernel during initialization.
625 */
626#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
627#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
628
629#if defined(CONFIG_CMD_KGDB)
630#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000631#endif
632
633/*
634 * Environment Configuration
635 */
636
637#if defined(CONFIG_TSEC_ENET)
638#define CONFIG_HAS_ETH0
639#define CONFIG_HAS_ETH1
640#endif
641
642#define CONFIG_HOSTNAME BSC9132qds
643#define CONFIG_ROOTPATH "/opt/nfsroot"
644#define CONFIG_BOOTFILE "uImage"
645#define CONFIG_UBOOTPATH "u-boot.bin"
646
647#define CONFIG_BAUDRATE 115200
648
649#ifdef CONFIG_SDCARD
650#define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
651#else
652#define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0"
653#endif
654
655#define CONFIG_EXTRA_ENV_SETTINGS \
656 "netdev=eth0\0" \
657 "uboot=" CONFIG_UBOOTPATH "\0" \
658 "loadaddr=1000000\0" \
659 "bootfile=uImage\0" \
660 "consoledev=ttyS0\0" \
661 "ramdiskaddr=2000000\0" \
662 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
663 "fdtaddr=c00000\0" \
664 "fdtfile=bsc9132qds.dtb\0" \
665 "bdev=sda1\0" \
666 CONFIG_DEF_HWCONFIG\
667 "othbootargs=mem=880M ramdisk_size=600000 " \
668 "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \
669 "isolcpus=0\0" \
670 "usbext2boot=setenv bootargs root=/dev/ram rw " \
671 "console=$consoledev,$baudrate $othbootargs; " \
672 "usb start;" \
673 "ext2load usb 0:4 $loadaddr $bootfile;" \
674 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
675 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
676 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
677 "debug_halt_off=mw ff7e0e30 0xf0000000;"
678
679#define CONFIG_NFSBOOTCOMMAND \
680 "setenv bootargs root=/dev/nfs rw " \
681 "nfsroot=$serverip:$rootpath " \
682 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
683 "console=$consoledev,$baudrate $othbootargs;" \
684 "tftp $loadaddr $bootfile;" \
685 "tftp $fdtaddr $fdtfile;" \
686 "bootm $loadaddr - $fdtaddr"
687
688#define CONFIG_HDBOOT \
689 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
690 "console=$consoledev,$baudrate $othbootargs;" \
691 "usb start;" \
692 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
693 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
694 "bootm $loadaddr - $fdtaddr"
695
696#define CONFIG_RAMBOOTCOMMAND \
697 "setenv bootargs root=/dev/ram rw " \
698 "console=$consoledev,$baudrate $othbootargs; " \
699 "tftp $ramdiskaddr $ramdiskfile;" \
700 "tftp $loadaddr $bootfile;" \
701 "tftp $fdtaddr $fdtfile;" \
702 "bootm $loadaddr $ramdiskaddr $fdtaddr"
703
704#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
705
Aneesh Bansalf978f7c2014-03-12 00:07:27 +0530706#include <asm/fsl_secure_boot.h>
707
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000708#endif /* __CONFIG_H */