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Stefan Roese899620c2006-08-15 14:22:35 +02001/*
2 * (C) Copyright 2006
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de
4 *
Stefan Roese5bc528f2006-10-07 11:35:25 +02005 * (C) Copyright 2006
6 * Stefan Roese, DENX Software Engineering, sr@denx.de.
7 *
Stefan Roese899620c2006-08-15 14:22:35 +02008 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
Stefan Roese899620c2006-08-15 14:22:35 +020028
29#if (CONFIG_COMMANDS & CFG_CMD_NAND)
30
Stefan Roese5bc528f2006-10-07 11:35:25 +020031#include <asm/processor.h>
Stefan Roese899620c2006-08-15 14:22:35 +020032#include <nand.h>
33
Stefan Roese899620c2006-08-15 14:22:35 +020034struct alpr_ndfc_regs {
Stefan Roese1c2ce222006-11-27 14:12:17 +010035 u8 cmd[4];
36 u8 addr_wait;
37 u8 term;
38 u8 dummy;
39 u8 dummy2;
40 u8 data;
Stefan Roese899620c2006-08-15 14:22:35 +020041};
42
43static u8 hwctl;
Stefan Roese5bc528f2006-10-07 11:35:25 +020044static struct alpr_ndfc_regs *alpr_ndfc = NULL;
Stefan Roese899620c2006-08-15 14:22:35 +020045
Stefan Roese1c2ce222006-11-27 14:12:17 +010046#define readb(addr) (u8)(*(volatile u8 *)(addr))
47#define writeb(d,addr) *(volatile u8 *)(addr) = ((u8)(d))
Stefan Roese899620c2006-08-15 14:22:35 +020048
Stefan Roese899620c2006-08-15 14:22:35 +020049/*
50 * The ALPR has a NAND Flash Controller (NDFC) that handles all accesses to
51 * the NAND devices. The NDFC has command, address and data registers that
52 * when accessed will set up the NAND flash pins appropriately. We'll use the
53 * hwcontrol function to save the configuration in a global variable.
54 * We can then use this information in the read and write functions to
55 * determine which NDFC register to access.
56 *
Stefan Roese5bc528f2006-10-07 11:35:25 +020057 * There are 2 NAND devices on the board, a Hynix HY27US08561A (1 GByte).
Stefan Roese899620c2006-08-15 14:22:35 +020058 */
Stefan Roese5bc528f2006-10-07 11:35:25 +020059static void alpr_nand_hwcontrol(struct mtd_info *mtd, int cmd)
Stefan Roese899620c2006-08-15 14:22:35 +020060{
Stefan Roese899620c2006-08-15 14:22:35 +020061 switch (cmd) {
62 case NAND_CTL_SETCLE:
63 hwctl |= 0x1;
64 break;
65 case NAND_CTL_CLRCLE:
66 hwctl &= ~0x1;
67 break;
68 case NAND_CTL_SETALE:
69 hwctl |= 0x2;
70 break;
71 case NAND_CTL_CLRALE:
72 hwctl &= ~0x2;
73 break;
74 case NAND_CTL_SETNCE:
75 break;
76 case NAND_CTL_CLRNCE:
Stefan Roese5bc528f2006-10-07 11:35:25 +020077 writeb(0x00, &(alpr_ndfc->term));
Stefan Roese899620c2006-08-15 14:22:35 +020078 break;
79 }
80}
81
Stefan Roese5bc528f2006-10-07 11:35:25 +020082static void alpr_nand_write_byte(struct mtd_info *mtd, u_char byte)
Stefan Roese899620c2006-08-15 14:22:35 +020083{
Stefan Roese5bc528f2006-10-07 11:35:25 +020084 struct nand_chip *nand = mtd->priv;
85
Stefan Roese899620c2006-08-15 14:22:35 +020086 if (hwctl & 0x1)
Stefan Roese5bc528f2006-10-07 11:35:25 +020087 /*
88 * IO_ADDR_W used as CMD[i] reg to support multiple NAND
89 * chips.
90 */
91 writeb(byte, nand->IO_ADDR_W);
Stefan Roese899620c2006-08-15 14:22:35 +020092 else if (hwctl & 0x2) {
Stefan Roese5bc528f2006-10-07 11:35:25 +020093 writeb(byte, &(alpr_ndfc->addr_wait));
Stefan Roese899620c2006-08-15 14:22:35 +020094 } else
Stefan Roese5bc528f2006-10-07 11:35:25 +020095 writeb(byte, &(alpr_ndfc->data));
Stefan Roese899620c2006-08-15 14:22:35 +020096}
97
Stefan Roese5bc528f2006-10-07 11:35:25 +020098static u_char alpr_nand_read_byte(struct mtd_info *mtd)
Stefan Roese899620c2006-08-15 14:22:35 +020099{
Stefan Roese5bc528f2006-10-07 11:35:25 +0200100 return readb(&(alpr_ndfc->data));
Stefan Roese899620c2006-08-15 14:22:35 +0200101}
102
Stefan Roese5bc528f2006-10-07 11:35:25 +0200103static void alpr_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
Stefan Roese899620c2006-08-15 14:22:35 +0200104{
Stefan Roese5bc528f2006-10-07 11:35:25 +0200105 struct nand_chip *nand = mtd->priv;
Stefan Roese899620c2006-08-15 14:22:35 +0200106 int i;
107
Stefan Roese899620c2006-08-15 14:22:35 +0200108 for (i = 0; i < len; i++) {
109 if (hwctl & 0x1)
Stefan Roese5bc528f2006-10-07 11:35:25 +0200110 /*
111 * IO_ADDR_W used as CMD[i] reg to support multiple NAND
112 * chips.
113 */
114 writeb(buf[i], nand->IO_ADDR_W);
115 else if (hwctl & 0x2)
116 writeb(buf[i], &(alpr_ndfc->addr_wait));
117 else
118 writeb(buf[i], &(alpr_ndfc->data));
Stefan Roese899620c2006-08-15 14:22:35 +0200119 }
120}
121
Stefan Roese5bc528f2006-10-07 11:35:25 +0200122static void alpr_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
Stefan Roese899620c2006-08-15 14:22:35 +0200123{
124 int i;
125
126 for (i = 0; i < len; i++) {
Stefan Roese5bc528f2006-10-07 11:35:25 +0200127 buf[i] = readb(&(alpr_ndfc->data));
Stefan Roese899620c2006-08-15 14:22:35 +0200128 }
129}
130
Stefan Roese5bc528f2006-10-07 11:35:25 +0200131static int alpr_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
Stefan Roese899620c2006-08-15 14:22:35 +0200132{
133 int i;
134
135 for (i = 0; i < len; i++)
Stefan Roese5bc528f2006-10-07 11:35:25 +0200136 if (buf[i] != readb(&(alpr_ndfc->data)))
Stefan Roese899620c2006-08-15 14:22:35 +0200137 return i;
138
139 return 0;
140}
141
Stefan Roese5bc528f2006-10-07 11:35:25 +0200142static int alpr_nand_dev_ready(struct mtd_info *mtd)
Stefan Roese899620c2006-08-15 14:22:35 +0200143{
Stefan Roese899620c2006-08-15 14:22:35 +0200144 volatile u_char val;
145
Stefan Roese899620c2006-08-15 14:22:35 +0200146 /*
147 * Blocking read to wait for NAND to be ready
148 */
Stefan Roese5bc528f2006-10-07 11:35:25 +0200149 val = readb(&(alpr_ndfc->addr_wait));
Stefan Roese899620c2006-08-15 14:22:35 +0200150
151 /*
152 * Return always true
153 */
154 return 1;
Stefan Roese899620c2006-08-15 14:22:35 +0200155}
156
Stefan Roesef16c1da2007-01-06 15:56:13 +0100157int board_nand_init(struct nand_chip *nand)
Stefan Roese899620c2006-08-15 14:22:35 +0200158{
159 alpr_ndfc = (struct alpr_ndfc_regs *)CFG_NAND_BASE;
160
161 nand->eccmode = NAND_ECC_SOFT;
162
Stefan Roese899620c2006-08-15 14:22:35 +0200163 /* Reference hardware control function */
Stefan Roese5bc528f2006-10-07 11:35:25 +0200164 nand->hwcontrol = alpr_nand_hwcontrol;
Stefan Roese899620c2006-08-15 14:22:35 +0200165 /* Set command delay time */
Stefan Roese5bc528f2006-10-07 11:35:25 +0200166 nand->write_byte = alpr_nand_write_byte;
167 nand->read_byte = alpr_nand_read_byte;
168 nand->write_buf = alpr_nand_write_buf;
169 nand->read_buf = alpr_nand_read_buf;
170 nand->verify_buf = alpr_nand_verify_buf;
171 nand->dev_ready = alpr_nand_dev_ready;
Stefan Roesef16c1da2007-01-06 15:56:13 +0100172
173 return 0;
Stefan Roese899620c2006-08-15 14:22:35 +0200174}
175#endif