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Stefan Roesec157d8e2005-08-01 16:41:48 +02001/*
Stefan Roese5a5958b2007-10-15 11:29:33 +02002 * (C) Copyright 2006-2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
Stefan Roesec157d8e2005-08-01 16:41:48 +02004 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
Stefan Roeseb36df562010-09-09 19:18:00 +020025#include <asm/ppc4xx.h>
Stefan Roesec157d8e2005-08-01 16:41:48 +020026#include <asm/processor.h>
Stefan Roese5a5958b2007-10-15 11:29:33 +020027#include <asm/io.h>
Stefan Roesec157d8e2005-08-01 16:41:48 +020028#include <spd_sdram.h>
Ira Snyder4adb3022008-04-29 11:18:54 -070029#include <libfdt.h>
30#include <fdt_support.h>
Stefan Roesec157d8e2005-08-01 16:41:48 +020031
Wolfgang Denkd87080b2006-03-31 18:32:53 +020032DECLARE_GLOBAL_DATA_PTR;
33
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020034extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
Stefan Roese84286382005-08-11 18:03:14 +020035
Stefan Roesec85b5832009-10-19 14:14:08 +020036static inline u32 get_async_pci_freq(void)
37{
38 if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) &
39 CONFIG_SYS_BCSR5_PCI66EN)
40 return 66666666;
41 else
42 return 33333333;
43}
44
Stefan Roesec157d8e2005-08-01 16:41:48 +020045int board_early_init_f(void)
46{
47 register uint reg;
48
49 /*--------------------------------------------------------------------
50 * Setup the external bus controller/chip selects
51 *-------------------------------------------------------------------*/
Stefan Roesed1c3b272009-09-09 16:25:29 +020052 mtdcr(EBC0_CFGADDR, EBC0_CFG);
53 reg = mfdcr(EBC0_CFGDATA);
54 mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */
Stefan Roesec157d8e2005-08-01 16:41:48 +020055
Stefan Roesec157d8e2005-08-01 16:41:48 +020056 /*--------------------------------------------------------------------
Stefan Roesec157d8e2005-08-01 16:41:48 +020057 * Setup the GPIO pins
58 *-------------------------------------------------------------------*/
59 /*CPLD cs */
Stefan Roese81a31702005-12-15 09:43:12 +010060 /*setup Address lines for flash size 64Meg. */
61 out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000);
62 out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000);
63 out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000);
Stefan Roesec157d8e2005-08-01 16:41:48 +020064
65 /*setup emac */
66 out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
67 out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
68 out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
69 out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
70 out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
71
72 /*UART1 */
73 out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
74 out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
75 out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
76
Stefan Roesee1902902005-10-28 12:21:06 +020077 /* external interrupts IRQ0...3 */
Wolfgang Denkb9b24802006-05-30 17:45:30 +020078 out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000);
79 out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x0000ff00);
Stefan Roesee1902902005-10-28 12:21:06 +020080 out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
81
Stefan Roese700200c2007-01-30 17:04:19 +010082#ifdef CONFIG_440EP
Stefan Roesec157d8e2005-08-01 16:41:48 +020083 /*setup USB 2.0 */
84 out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
85 out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
86 out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
87 out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
88 out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
Stefan Roese700200c2007-01-30 17:04:19 +010089#endif
Stefan Roesec157d8e2005-08-01 16:41:48 +020090
91 /*--------------------------------------------------------------------
Stefan Roeseef04a0a2005-11-03 08:31:33 +010092 * Setup the interrupt controller polarities, triggers, etc.
93 *-------------------------------------------------------------------*/
Stefan Roese952e7762009-09-24 09:55:50 +020094 mtdcr(UIC0SR, 0xffffffff); /* clear all */
95 mtdcr(UIC0ER, 0x00000000); /* disable all */
96 mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */
97 mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
98 mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
99 mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
100 mtdcr(UIC0SR, 0xffffffff); /* clear all */
Stefan Roeseef04a0a2005-11-03 08:31:33 +0100101
Stefan Roese952e7762009-09-24 09:55:50 +0200102 mtdcr(UIC1SR, 0xffffffff); /* clear all */
103 mtdcr(UIC1ER, 0x00000000); /* disable all */
104 mtdcr(UIC1CR, 0x00000000); /* all non-critical */
105 mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
106 mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
107 mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
108 mtdcr(UIC1SR, 0xffffffff); /* clear all */
Stefan Roeseef04a0a2005-11-03 08:31:33 +0100109
110 /*--------------------------------------------------------------------
Stefan Roesec157d8e2005-08-01 16:41:48 +0200111 * Setup other serial configuration
112 *-------------------------------------------------------------------*/
Stefan Roesed1c3b272009-09-09 16:25:29 +0200113 mfsdr(SDR0_PCI0, reg);
114 mtsdr(SDR0_PCI0, 0x80000000 | reg); /* PCI arbiter enabled */
115 mtsdr(SDR0_PFC0, 0x00003e00); /* Pin function */
116 mtsdr(SDR0_PFC1, 0x00048000); /* Pin function: UART0 has 4 pins */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200117
Stefan Roesec85b5832009-10-19 14:14:08 +0200118 /* Check and reconfigure the PCI sync clock if necessary */
119 ppc4xx_pci_sync_clock_config(get_async_pci_freq());
120
Stefan Roesec157d8e2005-08-01 16:41:48 +0200121 /*clear tmrclk divisor */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122 *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x04) = 0x00;
Stefan Roesec157d8e2005-08-01 16:41:48 +0200123
124 /*enable ethernet */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125 *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x08) = 0xf0;
Stefan Roesec157d8e2005-08-01 16:41:48 +0200126
Stefan Roese700200c2007-01-30 17:04:19 +0100127#ifdef CONFIG_440EP
Stefan Roesec157d8e2005-08-01 16:41:48 +0200128 /*enable usb 1.1 fs device and remove usb 2.0 reset */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129 *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x09) = 0x00;
Stefan Roese700200c2007-01-30 17:04:19 +0100130#endif
Stefan Roesec157d8e2005-08-01 16:41:48 +0200131
132 /*get rid of flash write protect */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133 *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x07) = 0x00;
Stefan Roesec157d8e2005-08-01 16:41:48 +0200134
135 return 0;
136}
137
Stefan Roese84286382005-08-11 18:03:14 +0200138int misc_init_r (void)
139{
Stefan Roese84286382005-08-11 18:03:14 +0200140 uint pbcr;
141 int size_val = 0;
142
143 /* Re-do sizing to get full correct info */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200144 mtdcr(EBC0_CFGADDR, PB0CR);
145 pbcr = mfdcr(EBC0_CFGDATA);
Stefan Roese84286382005-08-11 18:03:14 +0200146 switch (gd->bd->bi_flashsize) {
147 case 1 << 20:
148 size_val = 0;
149 break;
150 case 2 << 20:
151 size_val = 1;
152 break;
153 case 4 << 20:
154 size_val = 2;
155 break;
156 case 8 << 20:
157 size_val = 3;
158 break;
159 case 16 << 20:
160 size_val = 4;
161 break;
162 case 32 << 20:
163 size_val = 5;
164 break;
165 case 64 << 20:
166 size_val = 6;
167 break;
168 case 128 << 20:
169 size_val = 7;
170 break;
171 }
172 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
Stefan Roesed1c3b272009-09-09 16:25:29 +0200173 mtdcr(EBC0_CFGADDR, PB0CR);
174 mtdcr(EBC0_CFGDATA, pbcr);
Stefan Roese84286382005-08-11 18:03:14 +0200175
Stefan Roesef190c112005-11-05 15:50:16 +0100176 /* adjust flash start and offset */
177 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
178 gd->bd->bi_flashoffset = 0;
179
Stefan Roese84286382005-08-11 18:03:14 +0200180 /* Monitor protection ON by default */
181 (void)flash_protect(FLAG_PROTECT_SET,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182 -CONFIG_SYS_MONITOR_LEN,
Stefan Roese84286382005-08-11 18:03:14 +0200183 0xffffffff,
184 &flash_info[0]);
185
186 return 0;
187}
188
Stefan Roesec157d8e2005-08-01 16:41:48 +0200189int checkboard(void)
190{
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +0000191 char buf[64];
192 int i = getenv_f("serial#", buf, sizeof(buf));
Stefan Roese36adff32007-01-13 07:59:19 +0100193 u8 rev;
Stefan Roesec85b5832009-10-19 14:14:08 +0200194 u32 clock = get_async_pci_freq();
Stefan Roesec157d8e2005-08-01 16:41:48 +0200195
Stefan Roese700200c2007-01-30 17:04:19 +0100196#ifdef CONFIG_440EP
Stefan Roese93b17ec2005-10-03 15:27:50 +0200197 printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");
Stefan Roese700200c2007-01-30 17:04:19 +0100198#else
199 printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
200#endif
Stefan Roese36adff32007-01-13 07:59:19 +0100201
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202 rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
Stefan Roesec85b5832009-10-19 14:14:08 +0200203 printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000);
Stefan Roese36adff32007-01-13 07:59:19 +0100204
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +0000205 if (i > 0) {
Stefan Roese93b17ec2005-10-03 15:27:50 +0200206 puts(", serial# ");
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +0000207 puts(buf);
Stefan Roese93b17ec2005-10-03 15:27:50 +0200208 }
209 putc('\n');
210
Stefan Roesec85b5832009-10-19 14:14:08 +0200211 /*
212 * Reconfiguration of the PCI sync clock is already done,
213 * now check again if everything is in range:
214 */
215 if (ppc4xx_pci_sync_clock_config(clock)) {
216 printf("ERROR: PCI clocking incorrect (async=%d "
217 "sync=%ld)!\n", clock, get_PCI_freq());
218 }
219
Stefan Roesec157d8e2005-08-01 16:41:48 +0200220 return (0);
221}
222
223/*************************************************************************
Stefan Roesebbeff302008-06-02 17:37:28 +0200224 * initdram -- doesn't use serial presence detect.
Stefan Roesec157d8e2005-08-01 16:41:48 +0200225 *
226 * Assumes: 256 MB, ECC, non-registered
227 * PLB @ 133 MHz
228 *
229 ************************************************************************/
Stefan Roese81a31702005-12-15 09:43:12 +0100230#define NUM_TRIES 64
231#define NUM_READS 10
232
233void sdram_tr1_set(int ram_address, int* tr1_value)
234{
235 int i;
236 int j, k;
237 volatile unsigned int* ram_pointer = (unsigned int*)ram_address;
238 int first_good = -1, last_bad = 0x1ff;
239
240 unsigned long test[NUM_TRIES] = {
241 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
242 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
243 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
244 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
245 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
246 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
247 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
248 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
249 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
250 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
251 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
252 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
253 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
254 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
255 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
256 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
257
258 /* go through all possible SDRAM0_TR1[RDCT] values */
259 for (i=0; i<=0x1ff; i++) {
260 /* set the current value for TR1 */
Stefan Roese95b602b2009-09-24 13:59:57 +0200261 mtsdram(SDRAM0_TR1, (0x80800800 | i));
Stefan Roese81a31702005-12-15 09:43:12 +0100262
263 /* write values */
264 for (j=0; j<NUM_TRIES; j++) {
265 ram_pointer[j] = test[j];
266
267 /* clear any cache at ram location */
268 __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
269 }
270
271 /* read values back */
272 for (j=0; j<NUM_TRIES; j++) {
273 for (k=0; k<NUM_READS; k++) {
274 /* clear any cache at ram location */
275 __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
276
277 if (ram_pointer[j] != test[j])
278 break;
279 }
280
281 /* read error */
282 if (k != NUM_READS) {
283 break;
284 }
285 }
286
287 /* we have a SDRAM0_TR1[RDCT] that is part of the window */
288 if (j == NUM_TRIES) {
289 if (first_good == -1)
290 first_good = i; /* found beginning of window */
291 } else { /* bad read */
292 /* if we have not had a good read then don't care */
293 if(first_good != -1) {
294 /* first failure after a good read */
295 last_bad = i-1;
296 break;
297 }
298 }
299 }
300
301 /* return the current value for TR1 */
302 *tr1_value = (first_good + last_bad) / 2;
303}
304
Becky Bruce9973e3c2008-06-09 16:03:40 -0500305phys_size_t initdram(int board)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200306{
307 register uint reg;
Stefan Roese81a31702005-12-15 09:43:12 +0100308 int tr1_bank1, tr1_bank2;
Stefan Roesec157d8e2005-08-01 16:41:48 +0200309
310 /*--------------------------------------------------------------------
311 * Setup some default
312 *------------------------------------------------------------------*/
Stefan Roese95b602b2009-09-24 13:59:57 +0200313 mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
314 mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
315 mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
316 mtsdram(SDRAM0_CLKTR, 0x40000000); /* ?? */
317 mtsdram(SDRAM0_WDDCTR, 0x40000000); /* ?? */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200318
319 /*clear this first, if the DDR is enabled by a debugger
Stefan Roese81a31702005-12-15 09:43:12 +0100320 then you can not make changes. */
Stefan Roese95b602b2009-09-24 13:59:57 +0200321 mtsdram(SDRAM0_CFG0, 0x00000000); /* Disable EEC */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200322
323 /*--------------------------------------------------------------------
324 * Setup for board-specific specific mem
325 *------------------------------------------------------------------*/
326 /*
327 * Following for CAS Latency = 2.5 @ 133 MHz PLB
328 */
Stefan Roese95b602b2009-09-24 13:59:57 +0200329 mtsdram(SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
330 mtsdram(SDRAM0_B1CR, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200331
Stefan Roese95b602b2009-09-24 13:59:57 +0200332 mtsdram(SDRAM0_TR0, 0x410a4012); /* ?? */
333 mtsdram(SDRAM0_RTR, 0x04080000); /* ?? */
334 mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */
335 mtsdram(SDRAM0_CFG0, 0x30000000); /* Disable EEC */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200336 udelay(400); /* Delay 200 usecs (min) */
337
338 /*--------------------------------------------------------------------
339 * Enable the controller, then wait for DCEN to complete
340 *------------------------------------------------------------------*/
Stefan Roese95b602b2009-09-24 13:59:57 +0200341 mtsdram(SDRAM0_CFG0, 0x80000000); /* Enable */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200342
343 for (;;) {
Stefan Roese95b602b2009-09-24 13:59:57 +0200344 mfsdram(SDRAM0_MCSTS, reg);
Stefan Roesec157d8e2005-08-01 16:41:48 +0200345 if (reg & 0x80000000)
346 break;
347 }
Stefan Roese81a31702005-12-15 09:43:12 +0100348
349 sdram_tr1_set(0x00000000, &tr1_bank1);
350 sdram_tr1_set(0x08000000, &tr1_bank2);
Stefan Roese95b602b2009-09-24 13:59:57 +0200351 mtsdram(SDRAM0_TR1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800));
Stefan Roesec157d8e2005-08-01 16:41:48 +0200352
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353 return CONFIG_SYS_SDRAM_BANKS * (CONFIG_SYS_KBYTES_SDRAM * 1024); /* return bytes */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200354}
355
Stefan Roesec157d8e2005-08-01 16:41:48 +0200356/*************************************************************************
Stefan Roesec157d8e2005-08-01 16:41:48 +0200357 * hw_watchdog_reset
358 *
359 * This routine is called to reset (keep alive) the watchdog timer
360 *
361 ************************************************************************/
362#if defined(CONFIG_HW_WATCHDOG)
363void hw_watchdog_reset(void)
364{
365
366}
367#endif
Stefan Roesef3443862006-10-07 11:30:52 +0200368
369void board_reset(void)
370{
371 /* give reset to BCSR */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372 *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x06) = 0x09;
Stefan Roesef3443862006-10-07 11:30:52 +0200373}