Gregory CLEMENT | dd1033e | 2018-12-14 16:16:47 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| 2 | /* |
| 3 | * Copyright (c) 2018 Microsemi Corporation |
| 4 | */ |
| 5 | |
| 6 | #include <common.h> |
Simon Glass | 691d719 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 7 | #include <init.h> |
Gregory CLEMENT | dd1033e | 2018-12-14 16:16:47 +0100 | [diff] [blame] | 8 | |
| 9 | #include <asm/io.h> |
| 10 | #include <asm/types.h> |
Lars Povlsen | 7048bb1 | 2020-02-06 10:45:40 +0100 | [diff] [blame] | 11 | #include <asm/mipsregs.h> |
Gregory CLEMENT | dd1033e | 2018-12-14 16:16:47 +0100 | [diff] [blame] | 12 | |
| 13 | #include <mach/tlb.h> |
| 14 | #include <mach/ddr.h> |
| 15 | |
| 16 | DECLARE_GLOBAL_DATA_PTR; |
| 17 | |
| 18 | #if CONFIG_SYS_SDRAM_SIZE <= SZ_64M |
| 19 | #define MSCC_RAM_TLB_SIZE SZ_64M |
| 20 | #define MSCC_ATTRIB2 MMU_REGIO_INVAL |
| 21 | #elif CONFIG_SYS_SDRAM_SIZE <= SZ_128M |
| 22 | #define MSCC_RAM_TLB_SIZE SZ_64M |
| 23 | #define MSCC_ATTRIB2 MMU_REGIO_RW |
| 24 | #elif CONFIG_SYS_SDRAM_SIZE <= SZ_256M |
| 25 | #define MSCC_RAM_TLB_SIZE SZ_256M |
| 26 | #define MSCC_ATTRIB2 MMU_REGIO_INVAL |
| 27 | #elif CONFIG_SYS_SDRAM_SIZE <= SZ_512M |
| 28 | #define MSCC_RAM_TLB_SIZE SZ_256M |
| 29 | #define MSCC_ATTRIB2 MMU_REGIO_RW |
| 30 | #else |
| 31 | #define MSCC_RAM_TLB_SIZE SZ_512M |
| 32 | #define MSCC_ATTRIB2 MMU_REGIO_RW |
| 33 | #endif |
| 34 | |
| 35 | /* NOTE: lowlevel_init() function does not have access to the |
| 36 | * stack. Thus, all called functions must be inlined, and (any) local |
| 37 | * variables must be kept in registers. |
| 38 | */ |
| 39 | void vcoreiii_tlb_init(void) |
| 40 | { |
| 41 | register int tlbix = 0; |
| 42 | |
| 43 | /* |
| 44 | * Unlike most of the MIPS based SoCs, the IO register address |
| 45 | * are not in KSEG0. The mainline linux kernel built in legacy |
| 46 | * mode needs to access some of the registers very early in |
| 47 | * the boot and make the assumption that the bootloader has |
| 48 | * already configured them, so we have to match this |
| 49 | * expectation. |
| 50 | */ |
| 51 | create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW, |
| 52 | MMU_REGIO_RW); |
Gregory CLEMENT | 6bd8231 | 2018-12-14 16:16:48 +0100 | [diff] [blame] | 53 | #ifdef CONFIG_SOC_LUTON |
| 54 | create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW, |
| 55 | MMU_REGIO_RW); |
| 56 | #endif |
Gregory CLEMENT | dd1033e | 2018-12-14 16:16:47 +0100 | [diff] [blame] | 57 | |
Gregory CLEMENT | dd1033e | 2018-12-14 16:16:47 +0100 | [diff] [blame] | 58 | /* |
| 59 | * If U-Boot is located in NOR then we want to be able to use |
| 60 | * the data cache in order to boot in a decent duration |
| 61 | */ |
| 62 | create_tlb(tlbix++, MSCC_FLASH_TO, SZ_16M, MMU_REGIO_RO_C, |
| 63 | MMU_REGIO_RO_C); |
| 64 | create_tlb(tlbix++, MSCC_FLASH_TO + SZ_32M, SZ_16M, MMU_REGIO_RO_C, |
| 65 | MMU_REGIO_RO_C); |
| 66 | |
| 67 | /* |
| 68 | * Using cache for RAM also helps to improve boot time. Thanks |
| 69 | * to this the time to relocate U-Boot in RAM went from 2.092 |
| 70 | * secs to 0.104 secs. |
| 71 | */ |
| 72 | create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW, |
| 73 | MSCC_ATTRIB2); |
| 74 | |
Lars Povlsen | 7048bb1 | 2020-02-06 10:45:40 +0100 | [diff] [blame] | 75 | /* Enable mapping (using TLB) kuseg by clearing the bit ERL, |
| 76 | * which is set on reset. |
| 77 | */ |
| 78 | write_c0_status(read_c0_status() & ~ST0_ERL); |
Gregory CLEMENT | dd1033e | 2018-12-14 16:16:47 +0100 | [diff] [blame] | 79 | } |
| 80 | |
| 81 | int mach_cpu_init(void) |
| 82 | { |
| 83 | /* Speed up NOR flash access */ |
Gregory CLEMENT | 6bd8231 | 2018-12-14 16:16:48 +0100 | [diff] [blame] | 84 | #ifdef CONFIG_SOC_LUTON |
| 85 | writel(ICPU_PI_MST_CFG_TRISTATE_CTRL + |
| 86 | ICPU_PI_MST_CFG_CLK_DIV(4), BASE_CFG + ICPU_PI_MST_CFG); |
| 87 | |
| 88 | writel(ICPU_SPI_MST_CFG_FAST_READ_ENA + |
| 89 | ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) + |
| 90 | ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG); |
| 91 | #else |
Horatiu Vultur | 1895b87 | 2019-01-23 16:39:42 +0100 | [diff] [blame] | 92 | #if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_SERVAL) |
Gregory CLEMENT | dd1033e | 2018-12-14 16:16:47 +0100 | [diff] [blame] | 93 | writel(ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) + |
| 94 | ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG); |
Horatiu Vultur | e7a0de2 | 2019-01-12 18:56:56 +0100 | [diff] [blame] | 95 | #endif |
Horatiu Vultur | 0551251 | 2019-01-17 15:33:27 +0100 | [diff] [blame] | 96 | #if defined(CONFIG_SOC_JR2) || defined(CONFIG_SOC_SERVALT) |
Horatiu Vultur | e7a0de2 | 2019-01-12 18:56:56 +0100 | [diff] [blame] | 97 | writel(ICPU_SPI_MST_CFG_FAST_READ_ENA + |
| 98 | ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) + |
| 99 | ICPU_SPI_MST_CFG_CLK_DIV(14), BASE_CFG + ICPU_SPI_MST_CFG); |
| 100 | #endif |
Gregory CLEMENT | dd1033e | 2018-12-14 16:16:47 +0100 | [diff] [blame] | 101 | /* |
| 102 | * Legacy and mainline linux kernel expect that the |
| 103 | * interruption map was set as it was done by redboot. |
| 104 | */ |
| 105 | writel(~0, BASE_CFG + ICPU_DST_INTR_MAP(0)); |
| 106 | writel(0, BASE_CFG + ICPU_DST_INTR_MAP(1)); |
| 107 | writel(0, BASE_CFG + ICPU_DST_INTR_MAP(2)); |
| 108 | writel(0, BASE_CFG + ICPU_DST_INTR_MAP(3)); |
Gregory CLEMENT | 6bd8231 | 2018-12-14 16:16:48 +0100 | [diff] [blame] | 109 | #endif |
Gregory CLEMENT | dd1033e | 2018-12-14 16:16:47 +0100 | [diff] [blame] | 110 | return 0; |
| 111 | } |