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gerrit.cesnet.cz / github / trini / u-boot / f046ccd15c8bc9613bfd72916b761a127d36e5c6 / . / include / asm-ppc / immap_83xx.h
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Eran Libertyf046ccd2005-07-28 10:08:46 -0500[diff] [blame^]1/*
2 * MPC8349 Internal Memory Map
3 * Copyright (c) 2004 Freescale Semiconductor.
4 * Eran Liberty (liberty@freescale.com)
5 *
6 * based on:
7 * - MPC8260 Internal Memory Map
8 * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
9 * - MPC85xx Internal Memory Map
10 * Copyright(c) 2002,2003 Motorola Inc.
11 * Xianghua Xiao (x.xiao@motorola.com)
12 */
13#ifndef __IMMAP_8349__
14#define __IMMAP_8349__
15
16#include <asm/types.h>
17#include <asm/i2c.h>
18
19/*
20 * Local Access Window.
21 */
22typedef struct law8349 {
23 u32 bar; /* LBIU local access window base address register */
24#define LAWBAR_BAR 0xFFFFF000 /* Identifies the 20 most-significant address bits of the base of local access window n. The specified base address should be aligned to the window size, as defined by LBLAWARn[SIZE]. */
25#define LAWBAR_RES ~(LAWBAR_BAR)
26 u32 ar; /* LBIU local access window attribute register */
27/*
28 * This Macro were moved into mmu.h
29 */
30#if 0
31#define LAWAR_EN 0x80000000 /* 0 The local bus local access window n is disabled. 1 The local bus local access window n is enabled and other LBLAWAR0 and LBLAWBAR0 fields combine to identify an address range for this window. */
32#define LAWAR_SIZE 0x0000003F /* Identifies the size of the window from the starting address. Window size is 2^(SIZE+1) bytes. 000000–001010Reserved. Window is undefined. */
33#define LAWAR_SIZE_4K 0x0000000B
34#define LAWAR_SIZE_8K 0x0000000C
35#define LAWAR_SIZE_16K 0x0000000D
36#define LAWAR_SIZE_32K 0x0000000E
37#define LAWAR_SIZE_64K 0x0000000F
38#define LAWAR_SIZE_128K 0x00000010
39#define LAWAR_SIZE_256K 0x00000011
40#define LAWAR_SIZE_512K 0x00000012
41#define LAWAR_SIZE_1M 0x00000013
42#define LAWAR_SIZE_2M 0x00000014
43#define LAWAR_SIZE_4M 0x00000015
44#define LAWAR_SIZE_8M 0x00000016
45#define LAWAR_SIZE_16M 0x00000017
46#define LAWAR_SIZE_32M 0x00000018
47#define LAWAR_SIZE_64M 0x00000019
48#define LAWAR_SIZE_128M 0x0000001A
49#define LAWAR_SIZE_256M 0x0000001B
50#define LAWAR_SIZE_512M 0x0000001C
51#define LAWAR_SIZE_1G 0x0000001D
52#define LAWAR_SIZE_2G 0x0000001E
53#define LAWAR_RES ~(LAWAR_EN|LAWAR_SIZE)
54#endif
55
56} law8349_t;
57
58/*
59 * System configuration registers.
60 */
61typedef struct sysconf8349 {
62 u32 immrbar; /* Internal memory map base address register */
63 u8 res0[0x04];
64 u32 altcbar; /* Alternate configuration base address register */
65#define ALTCBAR_BASE_ADDR 0xFFF00000 /* Identifies the12 most significant address bits of an alternate base address used for boot sequencer configuration accesses. */
66#define ALTCBAR_RES ~(ALTCBAR_BASE_ADDR) /* Reserved. Write has no effect, read returns 0. */
67 u8 res1[0x14];
68 law8349_t lblaw[4]; /* LBIU local access window */
69 u8 res2[0x20];
70 law8349_t pcilaw[2]; /* PCI local access window */
71 u8 res3[0x30];
72 law8349_t ddrlaw[2]; /* DDR local access window */
73 u8 res4[0x50];
74 u32 sgprl; /* System General Purpose Register Low */
75 u32 sgprh; /* System General Purpose Register High */
76 u32 spridr; /* System Part and Revision ID Register */
77#define SPRIDR_PARTID 0xFFFF0000 /* Part Identification. */
78#define SPRIDR_REVID 0x0000FFFF /* Revision Identification. */
79 u8 res5[0x04];
80 u32 spcr; /* System Priority Configuration Register */
81#define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable. */
82#define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority. */
83#define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable. */
84#define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority. */
85#define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority. */
86#define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority. */
87#define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority. */
88#define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority. */
89#define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority. */
90#define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority. */
91#define SPCR_RES ~(SPCR_PCIHPE|SPCR_PCIPR|SPCR_TBEN|SPCR_COREPR|SPCR_TSEC1DP \
92 |SPCR_TSEC1BDP|SPCR_TSEC1EP|SPCR_TSEC2DP|SPCR_TSEC2BDP|SPCR_TSEC2EP)
93 u32 sicrl; /* System General Purpose Register Low */
94#define SICRL_LDP_A 0x80000000
95#define SICRL_USB0 0x40000000
96#define SICRL_USB1 0x20000000
97#define SICRL_UART 0x0C000000
98#define SICRL_GPIO1_A 0x02000000
99#define SICRL_GPIO1_B 0x01000000
100#define SICRL_GPIO1_C 0x00800000
101#define SICRL_GPIO1_D 0x00400000
102#define SICRL_GPIO1_E 0x00200000
103#define SICRL_GPIO1_F 0x00180000
104#define SICRL_GPIO1_G 0x00040000
105#define SICRL_GPIO1_H 0x00020000
106#define SICRL_GPIO1_I 0x00010000
107#define SICRL_GPIO1_J 0x00008000
108#define SICRL_GPIO1_K 0x00004000
109#define SICRL_GPIO1_L 0x00003000
110#define SICRL_RES ~(SICRL_LDP_A|SICRL_USB0|SICRL_USB1|SICRL_UART|SICRL_GPIO1_A \
111 |SICRL_GPIO1_B|SICRL_GPIO1_C|SICRL_GPIO1_D|SICRL_GPIO1_E \
112 |SICRL_GPIO1_F|SICRL_GPIO1_G|SICRL_GPIO1_H|SICRL_GPIO1_I \
113 |SICRL_GPIO1_J|SICRL_GPIO1_K|SICRL_GPIO1_L )
114 u32 sicrh; /* System General Purpose Register High */
115#define SICRH_DDR 0x80000000
116#define SICRH_TSEC1_A 0x10000000
117#define SICRH_TSEC1_B 0x08000000
118#define SICRH_TSEC1_C 0x04000000
119#define SICRH_TSEC1_D 0x02000000
120#define SICRH_TSEC1_E 0x01000000
121#define SICRH_TSEC1_F 0x00800000
122#define SICRH_TSEC2_A 0x00400000
123#define SICRH_TSEC2_B 0x00200000
124#define SICRH_TSEC2_C 0x00100000
125#define SICRH_TSEC2_D 0x00080000
126#define SICRH_TSEC2_E 0x00040000
127#define SICRH_TSEC2_F 0x00020000
128#define SICRH_TSEC2_G 0x00010000
129#define SICRH_TSEC2_H 0x00008000
130#define SICRH_GPIO2_A 0x00004000
131#define SICRH_GPIO2_B 0x00002000
132#define SICRH_GPIO2_C 0x00001000
133#define SICRH_GPIO2_D 0x00000800
134#define SICRH_GPIO2_E 0x00000400
135#define SICRH_GPIO2_F 0x00000200
136#define SICRH_GPIO2_G 0x00000180
137#define SICRH_GPIO2_H 0x00000060
138#define SICRH_TSOBI1 0x00000002
139#define SICRH_TSOBI2 0x00000001
140#define SICRh_RES ~(SICRH_DDR|SICRH_TSEC1_A|SICRH_TSEC1_B|SICRH_TSEC1_C \
141 |SICRH_TSEC1_D|SICRH_TSEC1_E|SICRH_TSEC1_F|SICRH_TSEC2_A \
142 |SICRH_TSEC2_B|SICRH_TSEC2_C|SICRH_TSEC2_D|SICRH_TSEC2_E \
143 |SICRH_TSEC2_F|SICRH_TSEC2_G|SICRH_TSEC2_H|SICRH_GPIO2_A \
144 |SICRH_GPIO2_B|SICRH_GPIO2_C|SICRH_GPIO2_D|SICRH_GPIO2_E \
145 |SICRH_GPIO2_F|SICRH_GPIO2_G|SICRH_GPIO2_H|SICRH_TSOBI1 \
146 |SICRH_TSOBI2)
147 u8 res6[0xE4];
148} sysconf8349_t;
149
150/*
151 * Watch Dog Timer (WDT) Registers
152 */
153typedef struct wdt8349 {
154 u8 res0[4];
155 u32 swcrr; /* System watchdog control register */
156 u32 swcnr; /* System watchdog count register */
157#define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field.
158#define SWCNR_RES ~(SWCNR_SWCN)
159 u8 res1[2];
160 u16 swsrr; /* System watchdog service register */
161 u8 res2[0xF0];
162} wdt8349_t;
163
164/*
165 * RTC/PIT Module Registers
166 */
167typedef struct rtclk8349 {
168 u32 cnr; /* control register */
169#define CNR_CLEN 0x00000080 /* Clock Enable Control Bit */
170#define CNR_CLIN 0x00000040 /* Input Clock Control Bit */
171#define CNR_AIM 0x00000002 /* Alarm Interrupt Mask Bit */
172#define CNR_SIM 0x00000001 /* Second Interrupt Mask Bit */
173#define CNR_RES ~(CNR_CLEN | CNR_CLIN | CNR_AIM | CNR_SIM)
174 u32 ldr; /* load register */
175 u32 psr; /* prescale register */
176 u32 ctr; /* register */
177 u32 evr; /* event register */
178#define RTEVR_SIF 0x00000001 /* Second Interrupt Flag Bit */
179#define RTEVR_AIF 0x00000002 /* Alarm Interrupt Flag Bit */
180#define RTEVR_RES ~(EVR_SIF | EVR_AIF)
181 u32 alr; /* alarm register */
182 u8 res0[0xE8];
183} rtclk8349_t;
184
185/*
186 * Global timper module
187 */
188
189typedef struct gtm8349 {
190 u8 cfr1; /* Timer1/2 Configuration */
191#define CFR1_PCAS 0x80 /* Pair Cascade mode */
192#define CFR1_BCM 0x40 /* Backward compatible mode */
193#define CFR1_STP2 0x20 /* Stop timer */
194#define CFR1_RST2 0x10 /* Reset timer */
195#define CFR1_GM2 0x08 /* Gate mode for pin 2 */
196#define CFR1_GM1 0x04 /* Gate mode for pin 1 */
197#define CFR1_STP1 0x02 /* Stop timer */
198#define CFR1_RST1 0x01 /* Reset timer */
199 u8 res0[3];
200 u8 cfr2; /* Timer3/4 Configuration */
201#define CFR2_PCAS 0x80 /* Pair Cascade mode */
202#define CFR2_SCAS 0x40 /* Super Cascade mode */
203#define CFR2_STP4 0x20 /* Stop timer */
204#define CFR2_RST4 0x10 /* Reset timer */
205#define CFR2_GM4 0x08 /* Gate mode for pin 4 */
206#define CFR2_GM3 0x04 /* Gate mode for pin 3 */
207#define CFR2_STP3 0x02 /* Stop timer */
208#define CFR2_RST3 0x01 /* Reset timer */
209 u8 res1[10];
210 u16 mdr1; /* Timer1 Mode Register */
211#define MDR_SPS 0xff00 /* Secondary Prescaler value */
212#define MDR_CE 0x00c0 /* Capture edge and enable interrupt */
213#define MDR_OM 0x0020 /* Output mode */
214#define MDR_ORI 0x0010 /* Output reference interrupt enable */
215#define MDR_FRR 0x0008 /* Free run/restart */
216#define MDR_ICLK 0x0006 /* Input clock source for the timer */
217#define MDR_GE 0x0001 /* Gate enable */
218 u16 mdr2; /* Timer2 Mode Register */
219 u16 rfr1; /* Timer1 Reference Register */
220 u16 rfr2; /* Timer2 Reference Register */
221 u16 cpr1; /* Timer1 Capture Register */
222 u16 cpr2; /* Timer2 Capture Register */
223 u16 cnr1; /* Timer1 Counter Register */
224 u16 cnr2; /* Timer2 Counter Register */
225 u16 mdr3; /* Timer3 Mode Register */
226 u16 mdr4; /* Timer4 Mode Register */
227 u16 rfr3; /* Timer3 Reference Register */
228 u16 rfr4; /* Timer4 Reference Register */
229 u16 cpr3; /* Timer3 Capture Register */
230 u16 cpr4; /* Timer4 Capture Register */
231 u16 cnr3; /* Timer3 Counter Register */
232 u16 cnr4; /* Timer4 Counter Register */
233 u16 evr1; /* Timer1 Event Register */
234 u16 evr2; /* Timer2 Event Register */
235 u16 evr3; /* Timer3 Event Register */
236 u16 evr4; /* Timer4 Event Register */
237#define GTEVR_REF 0x0002 /* Output reference event */
238#define GTEVR_CAP 0x0001 /* Counter Capture event */
239#define GTEVR_RES ~(EVR_CAP|EVR_REF)
240 u16 psr1; /* Timer1 Prescaler Register */
241 u16 psr2; /* Timer2 Prescaler Register */
242 u16 psr3; /* Timer3 Prescaler Register */
243 u16 psr4; /* Timer4 Prescaler Register */
244 u8 res[0xC0];
245} gtm8349_t;
246
247/*
248 * Integrated Programmable Interrupt Controller
249 */
250typedef struct ipic8349 {
251 u32 sicfr; /* System Global Interrupt Configuration Register (SICFR) */
252#define SICFR_HPI 0x7f000000 /* Highest Priority Interrupt */
253#define SICFR_MPSB 0x00400000 /* Mixed interrupts Priority Scheme for group B */
254#define SICFR_MPSA 0x00200000 /* Mixed interrupts Priority Scheme for group A */
255#define SICFR_IPSD 0x00080000 /* Internal interrupts Priority Scheme for group D */
256#define SICFR_IPSA 0x00010000 /* Internal interrupts Priority Scheme for group A */
257#define SICFR_HPIT 0x00000300 /* HPI priority position IPIC output interrupt Type */
258#define SICFR_RES ~(SICFR_HPI|SICFR_MPSB|SICFR_MPSA|SICFR_IPSD|SICFR_IPSA|SICFR_HPIT)
259 u32 sivcr; /* System Global Interrupt Vector Register (SIVCR) */
260#define SICVR_IVECX 0xfc000000 /* Interrupt vector (for CE compatibility purpose only not used in 8349 IPIC implementation) */
261#define SICVR_IVEC 0x0000007f /* Interrupt vector */
262#define SICVR_RES ~(SICVR_IVECX|SICVR_IVEC)
263 u32 sipnr_h; /* System Internal Interrupt Pending Register - High (SIPNR_H) */
264#define SIIH_TSEC1TX 0x80000000 /* TSEC1 Tx interrupt */
265#define SIIH_TSEC1RX 0x40000000 /* TSEC1 Rx interrupt */
266#define SIIH_TSEC1ER 0x20000000 /* TSEC1 Eror interrupt */
267#define SIIH_TSEC2TX 0x10000000 /* TSEC2 Tx interrupt */
268#define SIIH_TSEC2RX 0x08000000 /* TSEC2 Rx interrupt */
269#define SIIH_TSEC2ER 0x04000000 /* TSEC2 Eror interrupt */
270#define SIIH_USB2DR 0x02000000 /* USB2 DR interrupt */
271#define SIIH_USB2MPH 0x01000000 /* USB2 MPH interrupt */
272#define SIIH_UART1 0x00000080 /* UART1 interrupt */
273#define SIIH_UART2 0x00000040 /* UART2 interrupt */
274#define SIIH_SEC 0x00000020 /* SEC interrupt */
275#define SIIH_I2C1 0x00000004 /* I2C1 interrupt */
276#define SIIH_I2C2 0x00000002 /* I2C1 interrupt */
277#define SIIH_SPI 0x00000001 /* SPI interrupt */
278#define SIIH_RES ~(SIIH_TSEC1TX|SIIH_TSEC1RX|SIIH_TSEC1ER|SIIH_TSEC2TX \
279 |SIIH_TSEC2RX|SIIH_TSEC2ER|SIIH_USB2DR|SIIH_USB2MPH \
280 |SIIH_UART1 |SIIH_UART2 |SIIH_SEC |SIIH_I2C1 \
281 |SIIH_I2C2 |SIIH_SPI)
282 u32 sipnr_l; /* System Internal Interrupt Pending Register - Low (SIPNR_L) */
283#define SIIL_RTCS 0x80000000 /* RTC SECOND interrupt */
284#define SIIL_PIT 0x40000000 /* PIT interrupt */
285#define SIIL_PCI1 0x20000000 /* PCI1 interrupt */
286#define SIIL_PCI2 0x10000000 /* PCI2 interrupt */
287#define SIIL_RTCA 0x08000000 /* RTC ALARM interrupt */
288#define SIIL_MU 0x04000000 /* Message Unit interrupt */
289#define SIIL_SBA 0x02000000 /* System Bus Arbiter interrupt */
290#define SIIL_DMA 0x01000000 /* DMA interrupt */
291#define SIIL_GTM4 0x00800000 /* GTM4 interrupt */
292#define SIIL_GTM8 0x00400000 /* GTM8 interrupt */
293#define SIIL_GPIO1 0x00200000 /* GPIO1 interrupt */
294#define SIIL_GPIO2 0x00100000 /* GPIO2 interrupt */
295#define SIIL_DDR 0x00080000 /* DDR interrupt */
296#define SIIL_LBC 0x00040000 /* LBC interrupt */
297#define SIIL_GTM2 0x00020000 /* GTM2 interrupt */
298#define SIIL_GTM6 0x00010000 /* GTM6 interrupt */
299#define SIIL_PMC 0x00008000 /* PMC interrupt */
300#define SIIL_GTM3 0x00000800 /* GTM3 interrupt */
301#define SIIL_GTM7 0x00000400 /* GTM7 interrupt */
302#define SIIL_GTM1 0x00000020 /* GTM1 interrupt */
303#define SIIL_GTM5 0x00000010 /* GTM5 interrupt */
304#define SIIL_DPTC 0x00000001 /* DPTC interrupt (!!! Invisible for user !!!) */
305#define SIIL_RES ~(SIIL_RTCS |SIIL_PIT |SIIL_PCI1 |SIIL_PCI2 |SIIL_RTCA \
306 |SIIL_MU |SIIL_SBA |SIIL_DMA |SIIL_GTM4 |SIIL_GTM8 \
307 |SIIL_GPIO1|SIIL_GPIO2|SIIL_DDR |SIIL_LBC |SIIL_GTM2 \
308 |SIIL_GTM6 |SIIL_PMC |SIIL_GTM3 |SIIL_GTM7 |SIIL_GTM1 \
309 |SIIL_GTM5 |SIIL_DPTC )
310 u32 siprr_a; /* System Internal Interrupt Group A Priority Register (PRR) */
311 u8 res0[8];
312 u32 siprr_d; /* System Internal Interrupt Group D Priority Register (PRR) */
313 u32 simsr_h; /* System Internal Interrupt Mask Register - High (SIIH) */
314 u32 simsr_l; /* System Internal Interrupt Mask Register - Low (SIIL) */
315 u8 res1[4];
316 u32 sepnr; /* System External Interrupt Pending Register (SEI) */
317 u32 smprr_a; /* System Mixed Interrupt Group A Priority Register (PRR) */
318 u32 smprr_b; /* System Mixed Interrupt Group B Priority Register (PRR) */
319#define PRR_0 0xe0000000 /* Priority Register, Position 0 programming */
320#define PRR_1 0x1c000000 /* Priority Register, Position 1 programming */
321#define PRR_2 0x03800000 /* Priority Register, Position 2 programming */
322#define PRR_3 0x00700000 /* Priority Register, Position 3 programming */
323#define PRR_4 0x0000e000 /* Priority Register, Position 4 programming */
324#define PRR_5 0x00001c00 /* Priority Register, Position 5 programming */
325#define PRR_6 0x00000380 /* Priority Register, Position 6 programming */
326#define PRR_7 0x00000070 /* Priority Register, Position 7 programming */
327#define PRR_RES ~(PRR_0|PRR_1|PRR_2|PRR_3|PRR_4|PRR_5|PRR_6|PRR_7)
328 u32 semsr; /* System External Interrupt Mask Register (SEI) */
329#define SEI_IRQ0 0x80000000 /* IRQ0 external interrupt */
330#define SEI_IRQ1 0x40000000 /* IRQ1 external interrupt */
331#define SEI_IRQ2 0x20000000 /* IRQ2 external interrupt */
332#define SEI_IRQ3 0x10000000 /* IRQ3 external interrupt */
333#define SEI_IRQ4 0x08000000 /* IRQ4 external interrupt */
334#define SEI_IRQ5 0x04000000 /* IRQ5 external interrupt */
335#define SEI_IRQ6 0x02000000 /* IRQ6 external interrupt */
336#define SEI_IRQ7 0x01000000 /* IRQ7 external interrupt */
337#define SEI_SIRQ0 0x00008000 /* SIRQ0 external interrupt */
338#define SEI_RES ~( SEI_IRQ0 |SEI_IRQ1 |SEI_IRQ2 |SEI_IRQ3 |SEI_IRQ4 \
339 |SEI_IRQ5 |SEI_IRQ6 |SEI_IRQ7 |SEI_SIRQ0)
340 u32 secnr; /* System External Interrupt Control Register (SECNR) */
341#define SECNR_MIXB0T 0xc0000000 /* MIXB0 priority position IPIC output interrupt type */
342#define SECNR_MIXB1T 0x30000000 /* MIXB1 priority position IPIC output interrupt type */
343#define SECNR_MIXA0T 0x00c00000 /* MIXA0 priority position IPIC output interrupt type */
344#define SECNR_SYSA1T 0x00300000 /* MIXA1 priority position IPIC output interrupt type */
345#define SECNR_EDI0 0x00008000 /* IRQ0 external interrupt edge/level detect */
346#define SECNR_EDI1 0x00004000 /* IRQ1 external interrupt edge/level detect */
347#define SECNR_EDI2 0x00002000 /* IRQ2 external interrupt edge/level detect */
348#define SECNR_EDI3 0x00001000 /* IRQ3 external interrupt edge/level detect */
349#define SECNR_EDI4 0x00000800 /* IRQ4 external interrupt edge/level detect */
350#define SECNR_EDI5 0x00000400 /* IRQ5 external interrupt edge/level detect */
351#define SECNR_EDI6 0x00000200 /* IRQ6 external interrupt edge/level detect */
352#define SECNR_EDI7 0x00000100 /* IRQ7 external interrupt edge/level detect */
353#define SECNR_RES ~( SECNR_MIXB0T|SECNR_MIXB1T|SECNR_MIXA0T|SECNR_SYSA1T \
354 |SECNR_EDI0 |SECNR_EDI1 |SECNR_EDI2 |SECNR_EDI3 \
355 |SECNR_EDI4 |SECNR_EDI5 |SECNR_EDI6 |SECNR_EDI7)
356 u32 sersr; /* System Error Status Register (SERR) */
357 u32 sermr; /* System Error Mask Register (SERR) */
358#define SERR_IRQ0 0x80000000 /* IRQ0 MCP request */
359#define SERR_WDT 0x40000000 /* WDT MCP request */
360#define SERR_SBA 0x20000000 /* SBA MCP request */
361#define SERR_DDR 0x10000000 /* DDR MCP request */
362#define SERR_LBC 0x08000000 /* LBC MCP request */
363#define SERR_PCI1 0x04000000 /* PCI1 MCP request */
364#define SERR_PCI2 0x02000000 /* PCI2 MCP request */
365#define SERR_MU 0x01000000 /* MU MCP request */
366#define SERR_RNC 0x00010000 /* MU MCP request (!!! Non-visible for users !!!) */
367#define SERR_RES ~( SERR_IRQ0|SERR_WDT |SERR_SBA |SERR_DDR |SERR_LBC \
368 |SERR_PCI1|SERR_PCI2|SERR_MU |SERR_RNC )
369 u32 sercr; /* System Error Control Register (SERCR) */
370#define SERCR_MCPR 0x00000001 /* MCP Route */
371#define SERCR_RES ~(SERCR_MCPR)
372 u8 res2[4];
373 u32 sifcr_h; /* System Internal Interrupt Force Register - High (SIIH) */
374 u32 sifcr_l; /* System Internal Interrupt Force Register - Low (SIIL) */
375 u32 sefcr; /* System External Interrupt Force Register (SEI) */
376 u32 serfr; /* System Error Force Register (SERR) */
377 u8 res3[0xA0];
378} ipic8349_t;
379
380/*
381 * System Arbiter Registers
382 */
383typedef struct arbiter8349 {
384 u32 acr; /* Arbiter Configuration Register */
385#define ACR_COREDIS 0x10000000 /* Core disable. */
386#define ACR_PIPE_DEP 0x00070000 /* Pipeline depth (number of outstanding transactions). */
387#define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count. */
388#define ACR_RPTCNT 0x00000700 /* Repeat count. */
389#define ACR_APARK 0x00000030 /* Address parking. */
390#define ACR_PARKM 0x0000000F /* Parking master. */
391#define ACR_RES ~(ACR_COREDIS|ACR_PIPE_DEP|ACR_PCI_RPTCNT|ACR_RPTCNT|ACR_APARK|ACR_PARKM)
392 u32 atr; /* Arbiter Timers Register */
393#define ATR_DTO 0x00FF0000 /* Data time out. */
394#define ATR_ATO 0x000000FF /* Address time out. */
395#define ATR_RES ~(ATR_DTO|ATR_ATO)
396 u8 res[4];
397 u32 aer; /* Arbiter Event Register (AE)*/
398 u32 aidr; /* Arbiter Interrupt Definition Register (AE) */
399 u32 amr; /* Arbiter Mask Register (AE) */
400 u32 aeatr; /* Arbiter Event Attributes Register */
401#define AEATR_EVENT 0x07000000 /* Event type. */
402#define AEATR_MSTR_ID 0x001F0000 /* Master Id. */
403#define AEATR_TBST 0x00000800 /* Transfer burst. */
404#define AEATR_TSIZE 0x00000700 /* Transfer Size. */
405#define AEATR_TTYPE 0x0000001F /* Transfer Type. */
406#define AEATR_RES ~(AEATR_EVENT|AEATR_MSTR_ID|AEATR_TBST|AEATR_TSIZE|AEATR_TTYPE)
407 u32 aeadr; /* Arbiter Event Address Register */
408 u32 aerr; /* Arbiter Event Response Register (AE)*/
409#define AE_ETEA 0x00000020 /* Transfer error. */
410#define AE_RES_ 0x00000010 /* Reserved transfer type. */
411#define AE_ECW 0x00000008 /* External control word transfer type. */
412#define AE_AO 0x00000004 /* Address Only transfer type. */
413#define AE_DTO 0x00000002 /* Data time out. */
414#define AE_ATO 0x00000001 /* Address time out. */
415#define AE_RSRV ~(AE_ETEA|AE_RES_|AE_ECW|AE_AO|AE_DTO|AE_ATO)
416 u8 res1[0xDC];
417} arbiter8349_t;
418
419/*
420 * Reset Module
421 */
422typedef struct reset8349 {
423 u32 rcwl; /* RCWL Register */
424#define RCWL_LBIUCM 0x80000000 /* LBIUCM */
425#define RCWL_LBIUCM_SHIFT 31
426#define RCWL_DDRCM 0x40000000 /* DDRCM */
427#define RCWL_DDRCM_SHIFT 30
428#define RCWL_SVCOD 0x30000000 /* SVCOD */
429#define RCWL_SPMF 0x0f000000 /* SPMF */
430#define RCWL_SPMF_SHIFT 24
431#define RCWL_COREPLL 0x007F0000 /* COREPLL */
432#define RCWL_COREPLL_SHIFT 16
433#define RCWL_CEVCOD 0x000000C0 /* CEVCOD */
434#define RCWL_CEPDF 0x00000020 /* CEPDF */
435#define RCWL_CEPMF 0x0000001F /* CEPMF */
436#define RCWL_RES ~(RCWL_BIUCM|RCWL_DDRCM|RCWL_SVCOD|RCWL_SPMF|RCWL_COREPLL|RCWL_CEVCOD|RCWL_CEPDF|RCWL_CEPMF)
437 u32 rcwh; /* RCHL Register */
438#define RCWH_PCIHOST 0x80000000 /* PCIHOST */
439#define RCWH_PCIHOST_SHIFT 31
440#define RCWH_PCI64 0x40000000 /* PCI64 */
441#define RCWH_PCI1ARB 0x20000000 /* PCI1ARB */
442#define RCWH_PCI2ARB 0x10000000 /* PCI2ARB */
443#define RCWH_COREDIS 0x08000000 /* COREDIS */
444#define RCWH_BMS 0x04000000 /* BMS */
445#define RCWH_BOOTSEQ 0x03000000 /* BOOTSEQ */
446#define RCWH_SWEN 0x00800000 /* SWEN */
447#define RCWH_ROMLOC 0x00700000 /* ROMLOC */
448#define RCWH_TSEC1M 0x0000c000 /* TSEC1M */
449#define RCWH_TSEC2M 0x00003000 /* TSEC2M */
450#define RCWH_TPR 0x00000100 /* TPR */
451#define RCWH_TLE 0x00000008 /* TLE */
452#define RCWH_LALE 0x00000004 /* LALE */
453#define RCWH_RES ~(RCWH_PCIHOST|RCWH_PCI64|RCWH_PCI1ARB|RCWH_PCI2ARB \
454 |RCWH_COREDIS|RCWH_BMS|RCWH_BOOTSEQ|RCWH_SWEN|RCWH_ROMLOC \
455 |RCWH_TSEC1M|RCWH_TSEC2M|RCWH_TPR|RCWH_TLE|RCWH_LALE)
456 u8 res0[8];
457 u32 rsr; /* Reset status Register */
458#define RSR_RSTSRC 0xE0000000 /* Reset source */
459#define RSR_RSTSRC_SHIFT 29
460#define RSR_BSF 0x00010000 /* Boot seq. fail */
461#define RSR_BSF_SHIFT 16
462#define RSR_SWSR 0x00002000 /* software soft reset */
463#define RSR_SWSR_SHIFT 13
464#define RSR_SWHR 0x00001000 /* software hard reset */
465#define RSR_SWHR_SHIFT 12
466#define RSR_JHRS 0x00000200 /* jtag hreset */
467#define RSR_JHRS_SHIFT 9
468#define RSR_JSRS 0x00000100 /* jtag sreset status */
469#define RSR_JSRS_SHIFT 8
470#define RSR_CSHR 0x00000010 /* checkstop reset status */
471#define RSR_CSHR_SHIFT 4
472#define RSR_SWRS 0x00000008 /* software watchdog reset status */
473#define RSR_SWRS_SHIFT 3
474#define RSR_BMRS 0x00000004 /* bus monitop reset status */
475#define RSR_BMRS_SHIFT 2
476#define RSR_SRS 0x00000002 /* soft reset status */
477#define RSR_SRS_SHIFT 1
478#define RSR_HRS 0x00000001 /* hard reset status */
479#define RSR_HRS_SHIFT 0
480#define RSR_RES ~(RSR_RSTSRC|RSR_BSF|RSR_SWSR|RSR_SWHR|RSR_JHRS|RSR_JSRS|RSR_CSHR|RSR_SWRS|RSR_BMRS|RSR_SRS|RSR_HRS)
481 u32 rmr; /* Reset mode Register */
482#define RMR_CSRE 0x00000001 /* checkstop reset enable */
483#define RMR_CSRE_SHIFT 0
484#define RMR_RES ~(RMR_CSRE)
485 u32 rpr; /* Reset protection Register */
486 u32 rcr; /* Reset Control Register */
487#define RCR_SWHR 0x00000002 /* software hard reset */
488#define RCR_SWSR 0x00000001 /* software soft reset */
489#define RCR_RES ~(RCR_SWHR|RCR_SWSR)
490 u32 rcer; /* Reset Control Enable Register */
491#define RCER_CRE 0x00000001 /* software hard reset */
492#define RCER_RES ~(RCER_CRE)
493 u8 res1[0xDC];
494} reset8349_t;
495
496typedef struct clk8349 {
497 u32 spmr; /* system PLL mode Register */
498#define SPMR_LBIUCM 0x80000000 /* LBIUCM */
499#define SPMR_DDRCM 0x40000000 /* DDRCM */
500#define SPMR_SVCOD 0x30000000 /* SVCOD */
501#define SPMR_SPMF 0x0F000000 /* SPMF */
502#define SPMR_CKID 0x00800000 /* CKID */
503#define SPMR_CKID_SHIFT 23
504#define SPMR_COREPLL 0x007F0000 /* COREPLL */
505#define SPMR_CEVCOD 0x000000C0 /* CEVCOD */
506#define SPMR_CEPDF 0x00000020 /* CEPDF */
507#define SPMR_CEPMF 0x0000001F /* CEPMF */
508#define SPMR_RES ~(SPMR_LBIUCM|SPMR_DDRCM|SPMR_SVCOD|SPMR_SPMF|SPMR_CKID \
509 |SPMR_COREPLL|SPMR_CEVCOD|SPMR_CEPDF|SPMR_CEPMF)
510 u32 occr; /* output clock control Register */
511#define OCCR_PCICOE0 0x80000000 /* PCICOE0 */
512#define OCCR_PCICOE1 0x40000000 /* PCICOE1 */
513#define OCCR_PCICOE2 0x20000000 /* PCICOE2 */
514#define OCCR_PCICOE3 0x10000000 /* PCICOE3 */
515#define OCCR_PCICOE4 0x08000000 /* PCICOE4 */
516#define OCCR_PCICOE5 0x04000000 /* PCICOE5 */
517#define OCCR_PCICOE6 0x02000000 /* PCICOE6 */
518#define OCCR_PCICOE7 0x01000000 /* PCICOE7 */
519#define OCCR_PCICD0 0x00800000 /* PCICD0 */
520#define OCCR_PCICD1 0x00400000 /* PCICD1 */
521#define OCCR_PCICD2 0x00200000 /* PCICD2 */
522#define OCCR_PCICD3 0x00100000 /* PCICD3 */
523#define OCCR_PCICD4 0x00080000 /* PCICD4 */
524#define OCCR_PCICD5 0x00040000 /* PCICD5 */
525#define OCCR_PCICD6 0x00020000 /* PCICD6 */
526#define OCCR_PCICD7 0x00010000 /* PCICD7 */
527#define OCCR_PCI1CR 0x00000002 /* PCI1CR */
528#define OCCR_PCI2CR 0x00000001 /* PCI2CR */
529#define OCCR_RES ~(OCCR_PCICOE0|OCCR_PCICOE1|OCCR_PCICOE2|OCCR_PCICOE3|OCCR_PCICOE4 \
530 |OCCR_PCICOE5|OCCR_PCICOE6|OCCR_PCICOE7|OCCR_PCICD0|OCCR_PCICD1 \
531 |OCCR_PCICD2 |OCCR_PCICD3 |OCCR_PCICD4 |OCCR_PCICD5|OCCR_PCICD6 \
532 |OCCR_PCICD7 |OCCR_PCI1CR |OCCR_PCI2CR )
533 u32 sccr; /* system clock control Register */
534#define SCCR_TSEC1CM 0xc0000000 /* TSEC1CM */
535#define SCCR_TSEC1CM_SHIFT 30
536#define SCCR_TSEC2CM 0x30000000 /* TSEC2CM */
537#define SCCR_TSEC2CM_SHIFT 28
538#define SCCR_ENCCM 0x03000000 /* ENCCM */
539#define SCCR_ENCCM_SHIFT 24
540#define SCCR_USBMPHCM 0x00c00000 /* USBMPHCM */
541#define SCCR_USBMPHCM_SHIFT 22
542#define SCCR_USBDRCM 0x00300000 /* USBDRCM */
543#define SCCR_USBDRCM_SHIFT 20
544#define SCCR_PCICM 0x00010000 /* PCICM */
545#define SCCR_RES ~( SCCR_TSEC1CM|SCCR_TSEC2CM|SCCR_ENCCM|SCCR_USBMPHCM \
546 |SCCR_USBDRCM|SCCR_PCICM)
547 u8 res0[0xF4];
548} clk8349_t;
549
550/*
551 * Power Management Control Module
552 */
553typedef struct pmc8349 {
554 u32 pmccr; /* PMC Configuration Register */
555#define PMCCR_SLPEN 0x00000001 /* System Low Power Enable */
556#define PMCCR_DLPEN 0x00000002 /* DDR SDRAM Low Power Enable */
557#define PMCCR_RES ~(PMCCR_SLPEN|PMCCR_DLPEN)
558 u32 pmcer; /* PMC Event Register */
559#define PMCER_PMCI 0x00000001 /* PMC Interrupt */
560#define PMCER_RES ~(PMCER_PMCI)
561 u32 pmcmr; /* PMC Mask Register */
562#define PMCMR_PMCIE 0x0001 /* PMC Interrupt Enable */
563#define PMCMR_RES ~(PMCMR_PMCIE)
564 u8 res0[0xF4];
565} pmc8349_t;
566
567
568/*
569 * general purpose I/O module
570 */
571typedef struct gpio8349 {
572 u32 dir; /* direction register */
573 u32 odr; /* open drain register */
574 u32 dat; /* data register */
575 u32 ier; /* interrupt event register */
576 u32 imr; /* interrupt mask register */
577 u32 icr; /* external interrupt control register */
578 u8 res0[0xE8];
579} gpio8349_t;
580
581/*
582 * DDR Memory Controller Memory Map
583 */
584typedef struct ddr_cs_bnds{
585 u32 csbnds;
586#define CSBNDS_SA 0x00FF0000
587#define CSBNDS_SA_SHIFT 16
588#define CSBNDS_EA 0x000000FF
589#define CSBNDS_EA_SHIFT 0
590 u8 res0[4];
591} ddr_cs_bnds_t;
592
593typedef struct ddr8349{
594 ddr_cs_bnds_t csbnds[4]; /**< Chip Select x Memory Bounds */
595 u8 res0[0x60];
596 u32 cs_config[4]; /**< Chip Select x Configuration */
597#define CSCONFIG_EN 0x80000000
598#define CSCONFIG_AP 0x00800000
599#define CSCONFIG_ROW_BIT 0x00000700
600#define CSCONFIG_ROW_BIT_12 0x00000000
601#define CSCONFIG_ROW_BIT_13 0x00000100
602#define CSCONFIG_ROW_BIT_14 0x00000200
603#define CSCONFIG_COL_BIT 0x00000007
604#define CSCONFIG_COL_BIT_8 0x00000000
605#define CSCONFIG_COL_BIT_9 0x00000001
606#define CSCONFIG_COL_BIT_10 0x00000002
607#define CSCONFIG_COL_BIT_11 0x00000003
608 u8 res1[0x78];
609 u32 timing_cfg_1; /**< SDRAM Timing Configuration 1 */
610#define TIMING_CFG1_PRETOACT 0x70000000
611#define TIMING_CFG1_PRETOACT_SHIFT 28
612#define TIMING_CFG1_ACTTOPRE 0x0F000000
613#define TIMING_CFG1_ACTTOPRE_SHIFT 24
614#define TIMING_CFG1_ACTTORW 0x00700000
615#define TIMING_CFG1_ACTTORW_SHIFT 20
616#define TIMING_CFG1_CASLAT 0x00070000
617#define TIMING_CFG1_CASLAT_SHIFT 16
618#define TIMING_CFG1_REFREC 0x0000F000
619#define TIMING_CFG1_REFREC_SHIFT 12
620#define TIMING_CFG1_WRREC 0x00000700
621#define TIMING_CFG1_WRREC_SHIFT 8
622#define TIMING_CFG1_ACTTOACT 0x00000070
623#define TIMING_CFG1_ACTTOACT_SHIFT 4
624#define TIMING_CFG1_WRTORD 0x00000007
625#define TIMING_CFG1_WRTORD_SHIFT 0
626
627 u32 timing_cfg_2; /**< SDRAM Timing Configuration 2 */
628#define TIMING_CFG2_CPO 0x0F000000
629#define TIMING_CFG2_CPO_SHIFT 24
630#define TIMING_CFG2_ACSM 0x00080000
631#define TIMING_CFG2_WR_DATA_DELAY 0x00001C00
632#define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10
633
634 u32 sdram_cfg; /**< SDRAM Control Configuration */
635#define SDRAM_CFG_MEM_EN 0x80000000
636#define SDRAM_CFG_SREN 0x40000000
637#define SDRAM_CFG_ECC_EN 0x20000000
638#define SDRAM_CFG_RD_EN 0x10000000
639#define SDRAM_CFG_SDRAM_TYPE 0x03000000
640#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
641#define SDRAM_CFG_DYN_PWR 0x00200000
642#define SDRAM_CFG_32_BE 0x00080000
643#define SDRAM_CFG_8_BE 0x00040000
644#define SDRAM_CFG_NCAP 0x00020000
645#define SDRAM_CFG_2T_EN 0x00008000
646
647 u8 res2[4];
648 u32 sdram_mode; /**< SDRAM Mode Configuration */
649#define SDRAM_MODE_ESD 0xFFFF0000
650#define SDRAM_MODE_ESD_SHIFT 16
651#define SDRAM_MODE_SD 0x0000FFFF
652#define SDRAM_MODE_SD_SHIFT 0
653
654 u8 res3[8];
655 u32 sdram_interval; /**< SDRAM Interval Configuration */
656#define SDRAM_INTERVAL_REFINT 0x3FFF0000
657#define SDRAM_INTERVAL_REFINT_SHIFT 16
658#define SDRAM_INTERVAL_BSTOPRE 0x00003FFF
659#define SDRAM_INTERVAL_BSTOPRE_SHIFT 0
660 u8 res9[8];
661 u32 sdram_clk_cntl;
662 u8 res4[0xCCC];
663 u32 data_err_inject_hi; /**< Memory Data Path Error Injection Mask High */
664 u32 data_err_inject_lo; /**< Memory Data Path Error Injection Mask Low */
665 u32 ecc_err_inject; /**< Memory Data Path Error Injection Mask ECC */
666 u8 res5[0x14];
667 u32 capture_data_hi; /**< Memory Data Path Read Capture High */
668 u32 capture_data_lo; /**< Memory Data Path Read Capture Low */
669 u32 capture_ecc; /**< Memory Data Path Read Capture ECC */
670 u8 res6[0x14];
671 u32 err_detect; /**< Memory Error Detect */
672 u32 err_disable; /**< Memory Error Disable */
673 u32 err_int_en; /**< Memory Error Interrupt Enable */
674 u32 capture_attributes; /**< Memory Error Attributes Capture */
675 u32 capture_address; /**< Memory Error Address Capture */
676 u32 capture_ext_address;/**< Memory Error Extended Address Capture */
677 u32 err_sbe; /**< Memory Single-Bit ECC Error Management */
678 u8 res7[0xA4];
679 u32 debug_reg;
680 u8 res8[0xFC];
681} ddr8349_t;
682
683/*
684 * I2C1 Controller
685 */
686
687
688/*
689 * DUART
690 */
691typedef struct duart8349{
692 u8 urbr_ulcr_udlb; /**< combined register for URBR, UTHR and UDLB */
693 u8 uier_udmb; /**< combined register for UIER and UDMB */
694 u8 uiir_ufcr_uafr; /**< combined register for UIIR, UFCR and UAFR */
695 u8 ulcr; /**< line control register */
696 u8 umcr; /**< MODEM control register */
697 u8 ulsr; /**< line status register */
698 u8 umsr; /**< MODEM status register */
699 u8 uscr; /**< scratch register */
700 u8 res0[8];
701 u8 udsr; /**< DMA status register */
702 u8 res1[3];
703 u8 res2[0xEC];
704
705} duart8349_t;
706
707/*
708 * Local Bus Controller Registers
709 */
710typedef struct lbus_bank{
711 u32 br; /**< Base Register */
712 u32 or; /**< Base Register */
713} lbus_bank_t;
714
715typedef struct lbus8349 {
716 lbus_bank_t bank[8];
717 u8 res0[0x28];
718 u32 mar; /**< UPM Address Register */
719 u8 res1[0x4];
720 u32 mamr; /**< UPMA Mode Register */
721 u32 mbmr; /**< UPMB Mode Register */
722 u32 mcmr; /**< UPMC Mode Register */
723 u8 res2[0x8];
724 u32 mrtpr; /**< Memory Refresh Timer Prescaler Register */
725 u32 mdr; /**< UPM Data Register */
726 u8 res3[0x8];
727 u32 lsdmr; /**< SDRAM Mode Register */
728 u8 res4[0x8];
729 u32 lurt; /**< UPM Refresh Timer */
730 u32 lsrt; /**< SDRAM Refresh Timer */
731 u8 res5[0x8];
732 u32 ltesr; /**< Transfer Error Status Register */
733 u32 ltedr; /**< Transfer Error Disable Register */
734 u32 lteir; /**< Transfer Error Interrupt Register */
735 u32 lteatr; /**< Transfer Error Attributes Register */
736 u32 ltear; /**< Transfer Error Address Register */
737 u8 res6[0xC];
738 u32 lbcr; /**< Configuration Register */
739#define LBCR_LDIS 0x80000000
740#define LBCR_LDIS_SHIFT 31
741#define LBCR_BCTLC 0x00C00000
742#define LBCR_BCTLC_SHIFT 22
743#define LBCR_LPBSE 0x00020000
744#define LBCR_LPBSE_SHIFT 17
745#define LBCR_EPAR 0x00010000
746#define LBCR_EPAR_SHIFT 16
747#define LBCR_BMT 0x0000FF00
748#define LBCR_BMT_SHIFT 8
749 u32 lcrr; /**< Clock Ratio Register */
750#define LCRR_DBYP 0x80000000
751#define LCRR_DBYP_SHIFT 31
752#define LCRR_BUFCMDC 0x30000000
753#define LCRR_BUFCMDC_SHIFT 28
754#define LCRR_ECL 0x03000000
755#define LCRR_ECL_SHIFT 24
756#define LCRR_EADC 0x00030000
757#define LCRR_EADC_SHIFT 16
758#define LCRR_CLKDIV 0x0000000F
759#define LCRR_CLKDIV_SHIFT 0
760
761
762 u8 res7[0x28];
763 u8 res8[0xF00];
764} lbus8349_t;
765
766/*
767 * Serial Peripheral Interface
768 */
769typedef struct spi8349
770{
771 u32 mode; /**< mode register */
772 u32 event; /**< event register */
773 u32 mask; /**< mask register */
774 u32 com; /**< command register */
775 u8 res0[0x10];
776 u32 tx; /**< transmit register */
777 u32 rx; /**< receive register */
778 u8 res1[0xD8];
779} spi8349_t;
780
781typedef struct dma8349 {
782 u8 fixme[0x300];
783} dma8349_t;
784
785/*
786 * PCI Software Configuration Registers
787 */
788typedef struct pciconf8349 {
789 u32 config_address;
790#define PCI_CONFIG_ADDRESS_EN 0x80000000
791#define PCI_CONFIG_ADDRESS_BN_SHIFT 16
792#define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000
793#define PCI_CONFIG_ADDRESS_DN_SHIFT 11
794#define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800
795#define PCI_CONFIG_ADDRESS_FN_SHIFT 8
796#define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700
797#define PCI_CONFIG_ADDRESS_RN_SHIFT 0
798#define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc
799 u32 config_data;
800 u32 int_ack;
801 u8 res[116];
802} pciconf8349_t;
803
804/*
805 * PCI Outbound Translation Register
806 */
807typedef struct pci_outbound_window {
808 u32 potar;
809 u8 res0[4];
810 u32 pobar;
811 u8 res1[4];
812 u32 pocmr;
813 u8 res2[4];
814} pot8349_t;
815/*
816 * Sequencer
817 */
818typedef struct ios8349 {
819 pot8349_t pot[6];
820#define POTAR_TA_MASK 0x000fffff
821#define POBAR_BA_MASK 0x000fffff
822#define POCMR_EN 0x80000000
823#define POCMR_IO 0x40000000 /* 0--memory space 1--I/O space */
824#define POCMR_SE 0x20000000 /* streaming enable */
825#define POCMR_DST 0x10000000 /* 0--PCI1 1--PCI2*/
826#define POCMR_CM_MASK 0x000fffff
827#define POCMR_CM_4G 0x00000000
828#define POCMR_CM_2G 0x00080000
829#define POCMR_CM_1G 0x000C0000
830#define POCMR_CM_512M 0x000E0000
831#define POCMR_CM_256M 0x000F0000
832#define POCMR_CM_128M 0x000F8000
833#define POCMR_CM_64M 0x000FC000
834#define POCMR_CM_32M 0x000FE000
835#define POCMR_CM_16M 0x000FF000
836#define POCMR_CM_8M 0x000FF800
837#define POCMR_CM_4M 0x000FFC00
838#define POCMR_CM_2M 0x000FFE00
839#define POCMR_CM_1M 0x000FFF00
840#define POCMR_CM_512K 0x000FFF80
841#define POCMR_CM_256K 0x000FFFC0
842#define POCMR_CM_128K 0x000FFFE0
843#define POCMR_CM_64K 0x000FFFF0
844#define POCMR_CM_32K 0x000FFFF8
845#define POCMR_CM_16K 0x000FFFFC
846#define POCMR_CM_8K 0x000FFFFE
847#define POCMR_CM_4K 0x000FFFFF
848 u8 res0[0x60];
849 u32 pmcr;
850 u8 res1[4];
851 u32 dtcr;
852 u8 res2[4];
853} ios8349_t;
854
855/*
856 * PCI Controller Control and Status Registers
857 */
858typedef struct pcictrl8349 {
859 u32 esr;
860#define ESR_MERR 0x80000000
861#define ESR_APAR 0x00000400
862#define ESR_PCISERR 0x00000200
863#define ESR_MPERR 0x00000100
864#define ESR_TPERR 0x00000080
865#define ESR_NORSP 0x00000040
866#define ESR_TABT 0x00000020
867 u32 ecdr;
868#define ECDR_APAR 0x00000400
869#define ECDR_PCISERR 0x00000200
870#define ECDR_MPERR 0x00000100
871#define ECDR_TPERR 0x00000080
872#define ECDR_NORSP 0x00000040
873#define ECDR_TABT 0x00000020
874 u32 eer;
875#define EER_APAR 0x00000400
876#define EER_PCISERR 0x00000200
877#define EER_MPERR 0x00000100
878#define EER_TPERR 0x00000080
879#define EER_NORSP 0x00000040
880#define EER_TABT 0x00000020
881 u32 eatcr;
882#define EATCR_ERRTYPR_MASK 0x70000000
883#define EATCR_ERRTYPR_APR 0x00000000 /* address parity error */
884#define EATCR_ERRTYPR_WDPR 0x10000000 /* write data parity error */
885#define EATCR_ERRTYPR_RDPR 0x20000000 /* read data parity error */
886#define EATCR_ERRTYPR_MA 0x30000000 /* master abort */
887#define EATCR_ERRTYPR_TA 0x40000000 /* target abort */
888#define EATCR_ERRTYPR_SE 0x50000000 /* system error indication received */
889#define EATCR_ERRTYPR_PEA 0x60000000 /* parity error indication received on a read */
890#define EATCR_ERRTYPR_PEW 0x70000000 /* parity error indication received on a write */
891#define EATCR_BN_MASK 0x0f000000 /* beat number */
892#define EATCR_BN_1st 0x00000000
893#define EATCR_BN_2ed 0x01000000
894#define EATCR_BN_3rd 0x02000000
895#define EATCR_BN_4th 0x03000000
896#define EATCR_BN_5th 0x0400000
897#define EATCR_BN_6th 0x05000000
898#define EATCR_BN_7th 0x06000000
899#define EATCR_BN_8th 0x07000000
900#define EATCR_BN_9th 0x08000000
901#define EATCR_TS_MASK 0x00300000 /* transaction size */
902#define EATCR_TS_4 0x00000000
903#define EATCR_TS_1 0x00100000
904#define EATCR_TS_2 0x00200000
905#define EATCR_TS_3 0x00300000
906#define EATCR_ES_MASK 0x000f0000 /* error source */
907#define EATCR_ES_EM 0x00000000 /* external master */
908#define EATCR_ES_DMA 0x00050000
909#define EATCR_CMD_MASK 0x0000f000
910#define EATCR_HBE_MASK 0x00000f00 /* PCI high byte enable*/
911#define EATCR_BE_MASK 0x000000f0 /* PCI byte enable */
912#define EATCR_HPB 0x00000004 /* high parity bit */
913#define EATCR_PB 0x00000002 /* parity bit*/
914#define EATCR_VI 0x00000001 /* error information valid */
915 u32 eacr;
916 u32 eeacr;
917 u32 edlcr;
918 u32 edhcr;
919 u32 gcr;
920 u32 ecr;
921 u32 gsr;
922 u8 res0[12];
923 u32 pitar2;
924 u8 res1[4];
925 u32 pibar2;
926 u32 piebar2;
927 u32 piwar2;
928 u8 res2[4];
929 u32 pitar1;
930 u8 res3[4];
931 u32 pibar1;
932 u32 piebar1;
933 u32 piwar1;
934 u8 res4[4];
935 u32 pitar0;
936 u8 res5[4];
937 u32 pibar0;
938 u8 res6[4];
939 u32 piwar0;
940 u8 res7[132];
941#define PITAR_TA_MASK 0x000fffff
942#define PIBAR_MASK 0xffffffff
943#define PIEBAR_EBA_MASK 0x000fffff
944#define PIWAR_EN 0x80000000
945#define PIWAR_PF 0x20000000
946#define PIWAR_RTT_MASK 0x000f0000
947#define PIWAR_RTT_NO_SNOOP 0x00040000
948#define PIWAR_RTT_SNOOP 0x00050000
949#define PIWAR_WTT_MASK 0x0000f000
950#define PIWAR_WTT_NO_SNOOP 0x00004000
951#define PIWAR_WTT_SNOOP 0x00005000
952#define PIWAR_IWS_MASK 0x0000003F
953#define PIWAR_IWS_4K 0x0000000B
954#define PIWAR_IWS_8K 0x0000000C
955#define PIWAR_IWS_16K 0x0000000D
956#define PIWAR_IWS_32K 0x0000000E
957#define PIWAR_IWS_64K 0x0000000F
958#define PIWAR_IWS_128K 0x00000010
959#define PIWAR_IWS_256K 0x00000011
960#define PIWAR_IWS_512K 0x00000012
961#define PIWAR_IWS_1M 0x00000013
962#define PIWAR_IWS_2M 0x00000014
963#define PIWAR_IWS_4M 0x00000015
964#define PIWAR_IWS_8M 0x00000016
965#define PIWAR_IWS_16M 0x00000017
966#define PIWAR_IWS_32M 0x00000018
967#define PIWAR_IWS_64M 0x00000019
968#define PIWAR_IWS_128M 0x0000001A
969#define PIWAR_IWS_256M 0x0000001B
970#define PIWAR_IWS_512M 0x0000001C
971#define PIWAR_IWS_1G 0x0000001D
972#define PIWAR_IWS_2G 0x0000001E
973} pcictrl8349_t;
974
975/*
976 * USB
977 */
978typedef struct usb8349 {
979 u8 fixme[0x2000];
980} usb8349_t;
981
982/*
983 * TSEC
984 */
985typedef struct tsec8349 {
986 u8 fixme[0x1000];
987} tsec8349_t;
988
989/*
990 * Security
991 */
992typedef struct security8349 {
993 u8 fixme[0x10000];
994} security8349_t;
995
996typedef struct immap {
997 sysconf8349_t sysconf; /* System configuration */
998 wdt8349_t wdt; /* Watch Dog Timer (WDT) Registers */
999 rtclk8349_t rtc; /* Real Time Clock Module Registers */
1000 rtclk8349_t pit; /* Periodic Interval Timer */
1001 gtm8349_t gtm[2]; /* Global Timers Module */
1002 ipic8349_t ipic; /* Integrated Programmable Interrupt Controller */
1003 arbiter8349_t arbiter; /* System Arbiter Registers */
1004 reset8349_t reset; /* Reset Module */
1005 clk8349_t clk; /* System Clock Module */
1006 pmc8349_t pmc; /* Power Management Control Module */
1007 gpio8349_t pgio[2]; /* general purpose I/O module */
1008 u8 res0[0x200];
1009 u8 DDL_DDR[0x100];
1010 u8 DDL_LBIU[0x100];
1011 u8 res1[0xE00];
1012 ddr8349_t ddr; /* DDR Memory Controller Memory */
1013 i2c_t i2c[2]; /* I2C1 Controller */
1014 u8 res2[0x1300];
1015 duart8349_t duart[2];/* DUART */
1016 u8 res3[0x900];
1017 lbus8349_t lbus; /* Local Bus Controller Registers */
1018 u8 res4[0x1000];
1019 spi8349_t spi; /* Serial Peripheral Interface */
1020 u8 res5[0xF00];
1021 dma8349_t dma; /* DMA */
1022 pciconf8349_t pci_conf[2]; /* PCI Software Configuration Registers */
1023 ios8349_t ios; /* Sequencer */
1024 pcictrl8349_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */
1025 u8 res6[0x19900];
1026 usb8349_t usb;
1027 tsec8349_t tsec[2];
1028 u8 res7[0xA000];
1029 security8349_t security;
1030} immap_t;
1031
1032#endif /* __IMMAP_8349__ */