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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +09002/*
3 * include/configs/alt.h
4 * This file is alt board configuration.
5 *
6 * Copyright (C) 2014 Renesas Electronics Corporation
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +09007 */
8
9#ifndef __ALT_H
10#define __ALT_H
11
Nobuhiro Iwamatsu5ca6dfe2014-11-10 14:34:07 +090012#include "rcar-gen2-common.h"
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090013
Marek Vasutbb6d2ff2018-04-23 20:24:16 +020014#define STACK_AREA_SIZE 0x00100000
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090015#define LOW_LEVEL_MERAM_STACK \
Tom Rinieaf6ea62022-05-25 12:16:03 -040016 (SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090017
18/* MEMORY */
Nobuhiro Iwamatsu5ca6dfe2014-11-10 14:34:07 +090019#define RCAR_GEN2_SDRAM_BASE 0x40000000
20#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
21#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090022
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090023/* SH Ether */
Tom Rini97148cb2022-12-04 10:13:52 -050024#define CFG_SH_ETHER_USE_PORT 0
Tom Rini7c480ba2022-12-04 10:13:50 -050025#define CFG_SH_ETHER_PHY_ADDR 0x1
Tom Rini85b55112022-12-04 10:13:51 -050026#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
Tom Riniff53ecc2022-12-04 10:13:49 -050027#define CFG_SH_ETHER_CACHE_WRITEBACK
Tom Rinic253cea2022-12-04 10:13:48 -050028#define CFG_SH_ETHER_CACHE_INVALIDATE
Tom Rini24513c32022-12-04 10:13:47 -050029#define CFG_SH_ETHER_ALIGNE_SIZE 64
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090030
31/* Board Clock */
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090032
Tom Rini0613c362022-12-04 10:03:50 -050033#define CFG_EXTRA_ENV_SETTINGS \
Marek Vasut8c563502019-03-30 08:04:29 +010034 "bootm_size=0x10000000\0" \
35 "usb_pgood_delay=2000\0"
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090036
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090037#endif /* __ALT_H */