blob: 8d44ec6d7208f60b0512035553c7bde333e71356 [file] [log] [blame]
wdenkba56f622004-02-06 23:19:44 +00001/*
2 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/************************************************************************
24 * config for XPedite1000 from XES Inc.
25 * Ported from EBONY config by Travis B. Sawyer <tsawyer@sandburst.com>
26 * (C) Copyright 2003 Sandburst Corporation
Wolfgang Denk0c8721a2005-09-23 11:05:55 +020027 * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony)
wdenkba56f622004-02-06 23:19:44 +000028 ***********************************************************************/
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33/*-----------------------------------------------------------------------
34 * High Level Configuration Options
35 *----------------------------------------------------------------------*/
36#define CONFIG_XPEDITE1K 1 /* Board is XPedite 1000 */
37#define CONFIG_4xx 1 /* ... PPC4xx family */
38#define CONFIG_440 1
Stefan Roese846b0dd2005-08-08 12:42:22 +020039#define CONFIG_440GX 1 /* 440 GX */
wdenk3c74e322004-02-22 23:46:08 +000040#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041#undef CONFIG_SYS_DRAM_TEST /* Disable-takes long time! */
wdenkba56f622004-02-06 23:19:44 +000042#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
43
44
45/* POST support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020046#define CONFIG_POST (CONFIG_SYS_POST_RTC | \
47 CONFIG_SYS_POST_I2C)
wdenkba56f622004-02-06 23:19:44 +000048
49/*-----------------------------------------------------------------------
50 * Base addresses -- Note these are effective addresses where the
51 * actual resources get mapped (not physical addresses)
52 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
54#define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */
wdenkba56f622004-02-06 23:19:44 +000055
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* start of monitor */
57#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
58#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
59#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
60#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
wdenkba56f622004-02-06 23:19:44 +000061
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020062#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
63#define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
wdenkba56f622004-02-06 23:19:44 +000064
65#define USR_LED0 0x00000080
66#define USR_LED1 0x00000100
67#define USR_LED2 0x00000200
68#define USR_LED3 0x00000400
69
70#ifndef __ASSEMBLY__
71extern unsigned long in32(unsigned int);
72extern void out32(unsigned int, unsigned long);
73
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#define LED0_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED0))
75#define LED1_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED1))
76#define LED2_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED2))
77#define LED3_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED3))
wdenkba56f622004-02-06 23:19:44 +000078
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079#define LED0_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED0))
80#define LED1_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED1))
81#define LED2_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED2))
82#define LED3_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED3))
wdenkba56f622004-02-06 23:19:44 +000083#endif
84
85/*-----------------------------------------------------------------------
86 * Initial RAM & stack pointer (placed in internal SRAM)
87 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_TEMP_STACK_OCM 1
89#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
90#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
91#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
92#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
wdenkba56f622004-02-06 23:19:44 +000093
94
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
96#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
97#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR
wdenkba56f622004-02-06 23:19:44 +000098
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
100#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
wdenkba56f622004-02-06 23:19:44 +0000101
102/*-----------------------------------------------------------------------
103 * Serial Port
104 *----------------------------------------------------------------------*/
105#undef CONFIG_SERIAL_SOFTWARE_FIFO
106#define CONFIG_BAUDRATE 9600
107
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_BAUDRATE_TABLE \
wdenkba56f622004-02-06 23:19:44 +0000109 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
110
111/*-----------------------------------------------------------------------
112 * NVRAM/RTC
113 *
114 * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
115 * The DS1743 code assumes this condition (i.e. -- it assumes the base
116 * address for the RTC registers is:
117 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118 * CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
wdenkba56f622004-02-06 23:19:44 +0000119 *
120 *----------------------------------------------------------------------*/
121/* TBS: Xpedite 1000 has STMicro M41T00 via IIC */
122#define CONFIG_RTC_M41T11 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_I2C_RTC_ADDR 0x68
124#define CONFIG_SYS_M41T11_BASE_YEAR 2000
wdenkba56f622004-02-06 23:19:44 +0000125
126/*-----------------------------------------------------------------------
127 * FLASH related
128 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
130#define CONFIG_SYS_MAX_FLASH_SECT 8 /* sectors per device */
wdenkba56f622004-02-06 23:19:44 +0000131
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#undef CONFIG_SYS_FLASH_CHECKSUM
133#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
134#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenkba56f622004-02-06 23:19:44 +0000135
136/*-----------------------------------------------------------------------
137 * DDR SDRAM
138 *----------------------------------------------------------------------*/
139#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
140#define SPD_EEPROM_ADDRESS {0x54} /* SPD i2c spd addresses */
141#define CONFIG_VERY_BIG_RAM 1
142/*-----------------------------------------------------------------------
143 * I2C
144 *----------------------------------------------------------------------*/
145#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
146#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
148#define CONFIG_SYS_I2C_SLAVE 0x7f
149#define CONFIG_SYS_I2C_NOPROBES {0x55,0x56,0x57,0x58,0x59,0x5a,0x5b,0x5c,0x69} /* Don't probe these addrs */
wdenkba56f622004-02-06 23:19:44 +0000150
151/*-----------------------------------------------------------------------
152 * Environment
153 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200154#define CONFIG_ENV_IS_IN_EEPROM 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200155#define CONFIG_ENV_SIZE 0x100 /* Size of Environment vars */
156#define CONFIG_ENV_OFFSET 0x100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* this is actually the second page of the eeprom */
158#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
159#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
160#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
wdenkba56f622004-02-06 23:19:44 +0000161
162#define CONFIG_BOOTARGS "root=/dev/hda1 "
163#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */
wdenke7c85682004-02-27 08:21:54 +0000164#define CONFIG_BOOTDELAY 5 /* disable autoboot */
wdenkba56f622004-02-06 23:19:44 +0000165#define CONFIG_BAUDRATE 9600
166
167#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenkba56f622004-02-06 23:19:44 +0000169
Ben Warren96e21f82008-10-27 23:50:15 -0700170#define CONFIG_PPC4xx_EMAC
wdenkba56f622004-02-06 23:19:44 +0000171#define CONFIG_MII 1 /* MII PHY management */
172#define CONFIG_PHY_ADDR 0 /* PHY address phy0 not populated */
173#define CONFIG_PHY1_ADDR 1 /* PHY address phy1 not populated */
174#define CONFIG_PHY2_ADDR 4 /* PHY address phy2 */
175#define CONFIG_PHY3_ADDR 8 /* PHY address phy3 */
176#define CONFIG_NET_MULTI 1
wdenk6fb6af62004-03-23 23:20:24 +0000177#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200178#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
wdenkba56f622004-02-06 23:19:44 +0000180
wdenke2ffd592004-12-31 09:32:47 +0000181#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
182#define CONFIG_HAS_ETH2 1 /* add support for "eth2addr" */
183#define CONFIG_HAS_ETH3 1 /* add support for "eth3addr" */
184
wdenkba56f622004-02-06 23:19:44 +0000185
Jon Loeligera5562902007-07-08 15:31:57 -0500186/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500187 * BOOTP options
188 */
189#define CONFIG_BOOTP_BOOTFILESIZE
190#define CONFIG_BOOTP_BOOTPATH
191#define CONFIG_BOOTP_GATEWAY
192#define CONFIG_BOOTP_HOSTNAME
193
194
195/*
Jon Loeligera5562902007-07-08 15:31:57 -0500196 * Command line configuration.
197 */
198#include <config_cmd_default.h>
wdenkba56f622004-02-06 23:19:44 +0000199
Jon Loeligera5562902007-07-08 15:31:57 -0500200#define CONFIG_CMD_PCI
201#define CONFIG_CMD_IRQ
202#define CONFIG_CMD_I2C
203#define CONFIG_CMD_DATE
204#define CONFIG_CMD_BEDBUG
205#define CONFIG_CMD_EEPROM
206#define CONFIG_CMD_PING
207#define CONFIG_CMD_ELF
208#define CONFIG_CMD_MII
209#define CONFIG_CMD_DIAG
210#define CONFIG_CMD_FAT
wdenkba56f622004-02-06 23:19:44 +0000211
wdenkba56f622004-02-06 23:19:44 +0000212
213#undef CONFIG_WATCHDOG /* watchdog disabled */
214
215/*
216 * Miscellaneous configurable options
217 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_LONGHELP /* undef to save memory */
219#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligera5562902007-07-08 15:31:57 -0500220#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkba56f622004-02-06 23:19:44 +0000222#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkba56f622004-02-06 23:19:44 +0000224#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
226#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
227#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkba56f622004-02-06 23:19:44 +0000228
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
230#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkba56f622004-02-06 23:19:44 +0000231
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
233#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
wdenkba56f622004-02-06 23:19:44 +0000234
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkba56f622004-02-06 23:19:44 +0000236
237
238/*-----------------------------------------------------------------------
239 * PCI stuff
240 *-----------------------------------------------------------------------
241 */
242/* General PCI */
243#define CONFIG_PCI /* include pci support */
244#define CONFIG_PCI_PNP /* do pci plug-and-play */
245#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
wdenkba56f622004-02-06 23:19:44 +0000247
248/* Board-specific PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
wdenkba56f622004-02-06 23:19:44 +0000250
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
252#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
253#define CONFIG_SYS_PCI_FORCE_PCI_CONV /* Force PCI Conventional Mode */
wdenkba56f622004-02-06 23:19:44 +0000254/*
255 * For booting Linux, the board info and command line data
256 * have to be in the first 8 MB of memory, since this is
257 * the maximum mapped by the Linux kernel during initialization.
258 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkba56f622004-02-06 23:19:44 +0000260
261/*
262 * Internal Definitions
263 *
264 * Boot Flags
265 */
266#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
267#define BOOTFLAG_WARM 0x02 /* Software reboot */
268
Jon Loeligera5562902007-07-08 15:31:57 -0500269#if defined(CONFIG_CMD_KGDB)
wdenkba56f622004-02-06 23:19:44 +0000270#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
271#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
272#endif
273#endif /* __CONFIG_H */