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wdenk682011f2003-06-03 23:54:09 +00001/*
2 * (C) Copyright 2000, 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * Modified by Udi Finkelstein udif@udif.com
6 * For the RBC823 board.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27/*
28 * board/config.h - configuration options, board specific
29 */
30
31#ifndef __CONFIG_H
32#define __CONFIG_H
33
34/*
35 * High Level Configuration Options
36 * (easy to change)
37 */
38
39#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
40#define CONFIG_RBC823 1 /* ...on a RBC823 module */
41
42
43#if 0
44#define DEBUG 1
45#define CONFIG_LAST_STAGE_INIT
46#endif
47#define CONFIG_KEYBOARD 1 /* This board has a custom keybpard */
48#define CONFIG_LCD 1 /* use LCD controller ... */
49#define CONFIG_HITACHI_SP19X001_Z1A /* The LCD type we use */
50
51#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
52#undef CONFIG_8xx_CONS_SMC1
53#undef CONFIG_8xx_CONS_NONE
54#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
55#if 1
56#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
57#else
58#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
59#endif
60
61#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
62#define CONFIG_8xx_GCLK_FREQ 48000000L
63
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010064#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
wdenk682011f2003-06-03 23:54:09 +000065
66#undef CONFIG_BOOTARGS
67#define CONFIG_BOOTCOMMAND \
Wolfgang Denk53677ef2008-05-20 16:00:29 +020068 "bootp; " \
69 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
70 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenk682011f2003-06-03 23:54:09 +000071 "bootm"
72
73#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenk682011f2003-06-03 23:54:09 +000075
76#undef CONFIG_WATCHDOG /* watchdog disabled */
77
78#define CONFIG_STATUS_LED 1 /* Status LED enabled */
79
80#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
81
Jon Loeliger18225e82007-07-09 21:31:24 -050082/*
83 * BOOTP options
84 */
85#define CONFIG_BOOTP_SUBNETMASK
86#define CONFIG_BOOTP_GATEWAY
87#define CONFIG_BOOTP_HOSTNAME
88#define CONFIG_BOOTP_BOOTPATH
89#define CONFIG_BOOTP_BOOTFILESIZE
90
wdenk682011f2003-06-03 23:54:09 +000091
92#undef CONFIG_MAC_PARTITION
93#define CONFIG_DOS_PARTITION
94
95#undef CONFIG_RTC_MPC8xx /* don't use internal RTC of MPC8xx (no battery) */
96
97#define CONFIG_HARD_I2C
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_I2C_SPEED 40000
99#define CONFIG_SYS_I2C_SLAVE 0xfe
100#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
101#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
102#define CONFIG_SYS_EEPROM_WRITE_BITS 4
103#define CONFIG_SYS_EEPROM_WRITE_DELAY_MS 10
wdenk682011f2003-06-03 23:54:09 +0000104
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500105/*
106 * Command line configuration.
107 */
Jean-Christophe PLAGNIOL-VILLARD4e620412007-10-24 18:16:01 +0200108#include <config_cmd_default.h>
wdenk682011f2003-06-03 23:54:09 +0000109
Jean-Christophe PLAGNIOL-VILLARD4e620412007-10-24 18:16:01 +0200110#define CONFIG_CMD_ASKENV
111#define CONFIG_CMD_BEDBUG
112#define CONFIG_CMD_BMP
113#define CONFIG_CMD_CACHE
114#define CONFIG_CMD_CDP
115#define CONFIG_CMD_DHCP
116#define CONFIG_CMD_DIAG
117#define CONFIG_CMD_DOC
118#define CONFIG_CMD_EEPROM
119#define CONFIG_CMD_ELF
120#define CONFIG_CMD_FAT
121#define CONFIG_CMD_I2C
122#define CONFIG_CMD_IMMAP
123#define CONFIG_CMD_KGDB
124#define CONFIG_CMD_PING
125#define CONFIG_CMD_PORTIO
126#define CONFIG_CMD_REGINFO
127#define CONFIG_CMD_SAVES
128#define CONFIG_CMD_SDRAM
129
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500130#undef CONFIG_CMD_SETGETDCR
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500131#undef CONFIG_CMD_XIMG
132
wdenk682011f2003-06-03 23:54:09 +0000133/*
134 * Miscellaneous configurable options
135 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_LONGHELP /* undef to save memory */
137#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500138#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk682011f2003-06-03 23:54:09 +0000140#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk682011f2003-06-03 23:54:09 +0000142#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
144#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
145#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk682011f2003-06-03 23:54:09 +0000146
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
148#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenk682011f2003-06-03 23:54:09 +0000149
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_LOAD_ADDR 0x0100000 /* default load address */
wdenk682011f2003-06-03 23:54:09 +0000151
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk682011f2003-06-03 23:54:09 +0000153
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenk682011f2003-06-03 23:54:09 +0000155
156/*
157 * Low Level Configuration Settings
158 * (address mappings, register initial values, etc.)
159 * You should know what you are doing if you make changes here.
160 */
161/*-----------------------------------------------------------------------
162 * Internal Memory Mapped Register
163 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_IMMR 0xFF000000
wdenk682011f2003-06-03 23:54:09 +0000165
166/*-----------------------------------------------------------------------
167 * Definitions for initial stack pointer and data area (in DPRAM)
168 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
170#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
171#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
172#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
173#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk682011f2003-06-03 23:54:09 +0000174
175/*-----------------------------------------------------------------------
176 * Start addresses for the final memory configuration
177 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk682011f2003-06-03 23:54:09 +0000179 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_SDRAM_BASE 0x00000000
181#define CONFIG_SYS_FLASH_BASE 0xFFF00000
wdenk682011f2003-06-03 23:54:09 +0000182#if defined(DEBUG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 256 kB for Monitor */
wdenk682011f2003-06-03 23:54:09 +0000184#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 192 kB for Monitor */
wdenk682011f2003-06-03 23:54:09 +0000186#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
188#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenk682011f2003-06-03 23:54:09 +0000189
190/*
191 * For booting Linux, the board info and command line data
192 * have to be in the first 8 MB of memory, since this is
193 * the maximum mapped by the Linux kernel during initialization.
194 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk682011f2003-06-03 23:54:09 +0000196
197/*-----------------------------------------------------------------------
198 * FLASH organization
199 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
201#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
wdenk682011f2003-06-03 23:54:09 +0000202
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
204#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk682011f2003-06-03 23:54:09 +0000205
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200206#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200207#define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
208#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
wdenk682011f2003-06-03 23:54:09 +0000209
210/*-----------------------------------------------------------------------
211 * Cache Configuration
212 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500214#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenk682011f2003-06-03 23:54:09 +0000216#endif
217
218/*-----------------------------------------------------------------------
219 * SYPCR - System Protection Control 11-9
220 * SYPCR can only be written once after reset!
221 *-----------------------------------------------------------------------
222 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
223 */
224#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenk682011f2003-06-03 23:54:09 +0000226 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
227#else
228/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenk682011f2003-06-03 23:54:09 +0000230*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWRI | SYPCR_SWP)
wdenk682011f2003-06-03 23:54:09 +0000232#endif
233
234/*-----------------------------------------------------------------------
235 * SIUMCR - SIU Module Configuration 11-6
236 *-----------------------------------------------------------------------
237 * PCMCIA config., multi-function pin tri-state
238 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_FRC)
wdenk682011f2003-06-03 23:54:09 +0000240
241/*-----------------------------------------------------------------------
242 * TBSCR - Time Base Status and Control 11-26
243 *-----------------------------------------------------------------------
244 * Clear Reference Interrupt Status, Timebase freezing enabled
245 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenk682011f2003-06-03 23:54:09 +0000247
248/*-----------------------------------------------------------------------
249 * RTCSC - Real-Time Clock Status and Control Register 11-27
250 *-----------------------------------------------------------------------
251 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenk682011f2003-06-03 23:54:09 +0000253
254/*-----------------------------------------------------------------------
255 * PISCR - Periodic Interrupt Status and Control 11-31
256 *-----------------------------------------------------------------------
257 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
258 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenk682011f2003-06-03 23:54:09 +0000260
261/*-----------------------------------------------------------------------
262 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
263 *-----------------------------------------------------------------------
264 * Reset PLL lock status sticky bit, timer expired status bit and timer
265 * interrupt status bit
266 *
267 */
268
269/*
270 * for 48 MHz, we use a 4 MHz clock * 12
271 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_PLPRCR \
wdenk682011f2003-06-03 23:54:09 +0000273 ( (12-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_LOLRE )
274
275/*-----------------------------------------------------------------------
276 * SCCR - System Clock and reset Control Register 15-27
277 *-----------------------------------------------------------------------
278 * Set clock output, timebase and RTC source and divider,
279 * power management and some other internal clocks
280 */
281#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_SCCR (SCCR_RTDIV | SCCR_RTSEL | SCCR_CRQEN | \
wdenk682011f2003-06-03 23:54:09 +0000283 SCCR_PRQEN | SCCR_EBDF00 | \
284 SCCR_COM01 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
285 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD001 | \
286 SCCR_DFALCD00)
287
288#ifdef NOT_USED
289/*-----------------------------------------------------------------------
290 * PCMCIA stuff
291 *-----------------------------------------------------------------------
292 *
293 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
295#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
296#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
297#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
298#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
299#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
300#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
301#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenk682011f2003-06-03 23:54:09 +0000302
303/*-----------------------------------------------------------------------
304 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
305 *-----------------------------------------------------------------------
306 */
307
308#define CONFIG_IDE_PCCARD 1 /* Use IDE with PC Card Adapter */
309
310#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */
311#undef CONFIG_IDE_LED /* LED for ide not supported */
312#undef CONFIG_IDE_RESET /* reset for ide not supported */
313
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
315#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenk682011f2003-06-03 23:54:09 +0000316
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenk682011f2003-06-03 23:54:09 +0000318
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenk682011f2003-06-03 23:54:09 +0000320
321/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenk682011f2003-06-03 23:54:09 +0000323
324/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenk682011f2003-06-03 23:54:09 +0000326
327/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenk682011f2003-06-03 23:54:09 +0000329
330#endif
331
332/************************************************************
333 * Disk-On-Chip configuration
334 ************************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
336#define CONFIG_SYS_DOC_SHORT_TIMEOUT
337#define CONFIG_SYS_DOC_SUPPORT_2000
338#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
wdenk682011f2003-06-03 23:54:09 +0000339
340/*-----------------------------------------------------------------------
341 *
342 *-----------------------------------------------------------------------
343 *
344 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345/*#define CONFIG_SYS_DER 0x2002000F*/
346#define CONFIG_SYS_DER 0
wdenk682011f2003-06-03 23:54:09 +0000347
348/*
349 * Init Memory Controller:
350 *
351 * BR0/1 and OR0/1 (FLASH)
352 */
353
354#define FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank #0 */
355#define FLASH_BASE1_PRELIM 0x04000000 /* D.O.C Millenium */
356
357/* used to re-map FLASH both when starting from SRAM or FLASH:
358 * restrict access enough to keep SRAM working (if any)
359 * but not too much to meddle with FLASH accesses
360 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200361#define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */
wdenk682011f2003-06-03 23:54:09 +0000362
363/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 7, EHTR = 1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_BI | OR_SCY_7_CLK | OR_EHTR)
wdenk682011f2003-06-03 23:54:09 +0000365
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200366#define CONFIG_SYS_OR_TIMING_MSYS (OR_ACS_DIV1 | OR_BI)
wdenk682011f2003-06-03 23:54:09 +0000367
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200368#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
369#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
wdenk682011f2003-06-03 23:54:09 +0000370
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200371#define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_MSYS)
372#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | \
wdenk682011f2003-06-03 23:54:09 +0000373 BR_PS_8 | BR_V)
374
375/*
376 * BR4 and OR4 (SDRAM)
377 *
378 */
379#define SDRAM_BASE4_PRELIM 0x00000000 /* SDRAM bank #0 */
380#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
381
382/*
383 * SDRAM timing:
384 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200385#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM)
wdenk682011f2003-06-03 23:54:09 +0000386
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200387#define CONFIG_SYS_OR4_PRELIM (~(SDRAM_MAX_SIZE-1) | CONFIG_SYS_OR_TIMING_SDRAM )
388#define CONFIG_SYS_BR4_PRELIM ((SDRAM_BASE4_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenk682011f2003-06-03 23:54:09 +0000389
390/*
391 * Memory Periodic Timer Prescaler
392 */
393
394/* periodic timer for refresh */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200395#define CONFIG_SYS_MAMR_PTA 187 /* start with divider for 48 MHz */
wdenk682011f2003-06-03 23:54:09 +0000396
397/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200398#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
399#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenk682011f2003-06-03 23:54:09 +0000400
401/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200402#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
403#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenk682011f2003-06-03 23:54:09 +0000404
405/*
406 * MAMR settings for SDRAM
407 */
408
409/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200410#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenk682011f2003-06-03 23:54:09 +0000411 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
412 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
413/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200414#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenk682011f2003-06-03 23:54:09 +0000415 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
416 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
417
418
419/*
420 * Internal Definitions
421 *
422 * Boot Flags
423 */
424#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
425#define BOOTFLAG_WARM 0x02 /* Software reboot */
426
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200427/*
428 * JFFS2 partitions
429 *
430 */
431/* No command line, one static partition, whole device */
432#undef CONFIG_JFFS2_CMDLINE
433#define CONFIG_JFFS2_DEV "nor0"
434#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
435#define CONFIG_JFFS2_PART_OFFSET 0x00000000
436
437/* mtdparts command line support */
438/* Note: fake mtd_id used, no linux mtd map file */
439/*
440#define CONFIG_JFFS2_CMDLINE
441#define MTDIDS_DEFAULT ""
442#define MTDPARTS_DEFAULT ""
443*/
444
wdenk682011f2003-06-03 23:54:09 +0000445#endif /* __CONFIG_H */