Gitiles
Code Review Sign In
gerrit.cesnet.cz / github / trini / u-boot / ef26a08fef928b7bc11ae2c109e638dc3a016d91 / . / include / configs / bf533-stamp.h
blob: 353a43c286a3c5c530233c61dde162ab468e2136 [file] [log] [blame]
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800[diff] [blame]1/*
2 * U-boot - Configuration file for BF533 STAMP board
3 */
4
5#ifndef __CONFIG_STAMP_H__
6#define __CONFIG_STAMP_H__
7
8#define CONFIG_STAMP 1
9#define CONFIG_RTC_BFIN 1
10#define CONFIG_BF533 1
11/*
12 * Boot Mode Set
13 * Blackfin can support several boot modes
14 */
15#define BF533_BYPASS_BOOT 0x0001 /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */
16#define BF533_PARA_BOOT 0x0002 /* Bootmode 1: Boot from 8-bit or 16-bit flash */
17#define BF533_SPI_BOOT 0x0004 /* Bootmode 3: Boot from SPI flash */
18/* Define the boot mode */
19#define BFIN_BOOT_MODE BF533_BYPASS_BOOT
20//#define BFIN_BOOT_MODE BF533_SPI_BOOT
21
22#define CONFIG_PANIC_HANG 1
23
24#define ADSP_BF531 0x31
25#define ADSP_BF532 0x32
26#define ADSP_BF533 0x33
27#define BFIN_CPU ADSP_BF533
28
29/* This sets the default state of the cache on U-Boot's boot */
30#define CONFIG_ICACHE_ON
31#define CONFIG_DCACHE_ON
32
33/* Define where the uboot will be loaded by on-chip boot rom */
34#define APP_ENTRY 0x00001000
35
36/*
37 * Stringize definitions - needed for environmental settings
38 */
39#define STRINGIZE2(x) #x
40#define STRINGIZE(x) STRINGIZE2(x)
41
42/*
43 * Board settings
44 *
45 */
46#define CONFIG_DRIVER_SMC91111 1
47#define CONFIG_SMC91111_BASE 0x20300300
48
49/* FLASH/ETHERNET uses the same address range */
50#define SHARED_RESOURCES 1
51
52/* Is I2C bit-banged? */
53#define CONFIG_SOFT_I2C 1
54
55/*
56 * Software (bit-bang) I2C driver configuration
57 */
58#define PF_SCL PF3
59#define PF_SDA PF2
60
61/*
62 * Video splash screen support
63 */
64#define CONFIG_VIDEO 0
65
66#define CONFIG_VDSP 1
67
68/*
69 * Clock settings
70 *
71 */
72
73/* CONFIG_CLKIN_HZ is any value in Hz */
74#define CONFIG_CLKIN_HZ 11059200
75/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
76/* 1=CLKIN/2 */
77#define CONFIG_CLKIN_HALF 0
78/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
79/* 1=bypass PLL */
80#define CONFIG_PLL_BYPASS 0
81/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
82/* Values can range from 1-64 */
83#define CONFIG_VCO_MULT 36
84/* CONFIG_CCLK_DIV controls what the core clock divider is */
85/* Values can be 1, 2, 4, or 8 ONLY */
86#define CONFIG_CCLK_DIV 1
87/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
88/* Values can range from 1-15 */
89#define CONFIG_SCLK_DIV 5
90/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
91/* Values can range from 2-65535 */
92/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
93#define CONFIG_SPI_BAUD 2
94
95#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
96#define CONFIG_SPI_BAUD_INITBLOCK 4
97#endif
98
99
100/*
101 * Network settings
102 *
103 */
104
105#if (CONFIG_DRIVER_SMC91111)
106#if 0
107#define CONFIG_MII
108#endif
109
110/* network support */
111#define CONFIG_IPADDR 192.168.0.15
112#define CONFIG_NETMASK 255.255.255.0
113#define CONFIG_GATEWAYIP 192.168.0.1
114#define CONFIG_SERVERIP 192.168.0.2
115#define CONFIG_HOSTNAME STAMP
116#define CONFIG_ROOTPATH /checkout/uClinux-dist/romfs
117
118/* To remove hardcoding and enable MAC storage in EEPROM */
119/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */
120#endif /* CONFIG_DRIVER_SMC91111 */
121
122/*
123 * Flash settings
124 *
125 */
126
127#define CFG_FLASH_CFI /* The flash is CFI compatible */
128#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
129#define CFG_FLASH_CFI_AMD_RESET
130
131#define CFG_FLASH_BASE 0x20000000
132#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
133#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
134
135#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
136#define CFG_ENV_IS_IN_FLASH 1
137#define CFG_ENV_ADDR 0x20004000
138#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
139#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
140#define CFG_ENV_IS_IN_EEPROM 1
141#define CFG_ENV_OFFSET 0x4000
142#define CFG_ENV_HEADER (CFG_ENV_OFFSET + 0x12A) /* 0x12A is the length of LDR file header */
143#endif
144
145#define CFG_ENV_SIZE 0x2000
146#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
147#define ENV_IS_EMBEDDED
148
149#define CFG_FLASH_ERASE_TOUT 30000 /* Timeout for Chip Erase (in ms) */
150#define CFG_FLASH_ERASEBLOCK_TOUT 5000 /* Timeout for Block Erase (in ms) */
151#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
152
153/* JFFS Partition offset set */
154#define CFG_JFFS2_FIRST_BANK 0
155#define CFG_JFFS2_NUM_BANKS 1
156/* 512k reserved for u-boot */
157#define CFG_JFFS2_FIRST_SECTOR 11
158
159/*
160 * following timeouts shall be used once the
161 * Flash real protection is enabled
162 */
163#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
164#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
165
166/*
167 * SDRAM settings & memory map
168 *
169 */
170
171#define CONFIG_MEM_SIZE 128 /* 128, 64, 32, 16 */
172#define CONFIG_MEM_ADD_WDTH 11 /* 8, 9, 10, 11 */
173#define CONFIG_MEM_MT48LC64M4A2FB_7E 1
174
175#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
176#define CFG_MEMTEST_START 0x00000000 /* memtest works on */
177#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
178#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
179#endif
180
181#define CFG_SDRAM_BASE 0x00000000
182
183#define CFG_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 *1024)
184#define CFG_MEMTEST_END (CFG_MAX_RAM_SIZE - 0x80000 - 1)
185#define CONFIG_LOADADDR 0x01000000
186
187#define CFG_LOAD_ADDR CONFIG_LOADADDR
188#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
189#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
190#define CFG_GBL_DATA_SIZE 0x4000 /* Reserve 16k for Global Data */
191#define CONFIG_STACKSIZE (128*1024) /* regular stack */
192
193#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - 0x40000)
194#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
195#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
196#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4)
197
198/* Check to make sure everything fits in SDRAM */
199#if ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) > CFG_MAX_RAM_SIZE)
200 #error Memory Map does not fit into configuration
201#endif
202
203#if ( CONFIG_CLKIN_HALF == 0 )
204#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
205#else
206#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
207#endif
208
209#if (CONFIG_PLL_BYPASS == 0)
210#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
211#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
212#else
213#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
214#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
215#endif
216
217#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
218#if (CONFIG_SCLK_HZ / (2*CONFIG_SPI_BAUD) > 20000000)
219#define CONFIG_SPI_FLASH_FAST_READ 1 /* Needed if SPI_CLK > 20 MHz */
220#else
221#undef CONFIG_SPI_FLASH_FAST_READ
222#endif
223#endif
224/*
225 * Command settings
226 *
227 */
228
229#define CFG_LONGHELP 1
230#define CONFIG_CMDLINE_EDITING 1
231
232#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
233#define CFG_AUTOLOAD "no" /*rarpb, bootp or dhcp commands will perform only a */
234#endif
235 /* configuration lookup from the BOOTP/DHCP server, */
236 /* but not try to load any image using TFTP */
237
238#define CONFIG_BOOTDELAY 5
239#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
240#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
241#define CONFIG_BOOTCOMMAND "run ramboot"
242#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
243#define CONFIG_BOOTCOMMAND "eeprom read 0x1000000 0x100000 0x180000;icache on;dcache on;bootm 0x1000000"
244#endif
245
246#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
247
248#if (CONFIG_DRIVER_SMC91111)
249#define CONFIG_COMMANDS1 (CONFIG_CMD_DFL | \
250 CFG_CMD_PING | \
251 CFG_CMD_ELF | \
252 CFG_CMD_CACHE | \
253 CFG_CMD_JFFS2 | \
254 CFG_CMD_EEPROM | \
255 CFG_CMD_DATE)
256
257#else
258#define CONFIG_COMMANDS1 (CONFIG_CMD_DFL | \
259 CFG_CMD_ELF | \
260 CFG_CMD_CACHE | \
261 CFG_CMD_JFFS2 | \
262 CFG_CMD_EEPROM | \
263 CFG_CMD_DATE)
264
265#endif
266
267#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
268#if (CONFIG_DRIVER_SMC91111)
269#define CONFIG_EXTRA_ENV_SETTINGS \
270 "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
271 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
272 "$(rootpath) console=ttyBF0,57600\0" \
273 "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
274 "$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
275 "ramboot=tftpboot $(loadaddr) linux; " \
276 "run ramargs;run addip;bootelf\0" \
277 "nfsboot=tftpboot $(loadaddr) linux; " \
278 "run nfsargs;run addip;bootelf\0" \
279 "flashboot=bootm 0x20100000\0" \
280 "update=tftpboot $(loadaddr) u-boot.bin; " \
281 "protect off 0x20000000 0x2003FFFF; erase 0x20000000 0x2003FFFF;" \
282 "cp.b $(loadaddr) 0x20000000 $(filesize)\0" \
283 ""
284#else
285#define CONFIG_EXTRA_ENV_SETTINGS \
286 "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
287 "flashboot=bootm 0x20100000\0" \
288 ""
289#endif
290
291#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
292#define CONFIG_EXTRA_ENV_SETTINGS \
293 "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
294 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
295 "$(rootpath) console=ttyBF0,57600\0" \
296 "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
297 "$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
298 "ramboot=tftpboot $(loadaddr) linux; " \
299 "run ramargs;run addip;bootelf\0" \
300 "nfsboot=tftpboot $(loadaddr) linux; " \
301 "run nfsargs;run addip;bootelf\0" \
302 "flashboot=bootm 0x20100000\0" \
303 "update=tftpboot $(loadaddr) u-boot.ldr;" \
304 "eeprom write $(loadaddr) 0x0 $(filesize);\0"\
305 ""
306#endif
307
308#ifdef CONFIG_SOFT_I2C
309#if (!CONFIG_SOFT_I2C)
310#undef CONFIG_SOFT_I2C
311#endif
312#endif
313
314#if (CONFIG_SOFT_I2C)
315#define CONFIG_COMMANDS2 CFG_CMD_I2C
316#else
317#define CONFIG_COMMANDS2 0
318#endif /* CONFIG_SOFT_I2C */
319
320#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
321#define CONFIG_COMMANDS ( CONFIG_COMMANDS1 | CONFIG_COMMANDS2 | CFG_CMD_DHCP)
322#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
323#define CONFIG_COMMANDS ( CONFIG_COMMANDS1 | CONFIG_COMMANDS2)
324#endif
325
326/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
327#include <cmd_confdefs.h>
328
329/*
330 * Console settings
331 *
332 */
333
334#define CONFIG_BAUDRATE 57600
335#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
336
337#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
338#if (BFIN_CPU == ADSP_BF531)
339#define CFG_PROMPT "serial_bf531> " /* Monitor Command Prompt */
340#elif (BFIN_CPU == ADSP_BF532)
341#define CFG_PROMPT "serial_bf532> " /* Monitor Command Prompt */
342#else
343#define CFG_PROMPT "serial_bf533> " /* Monitor Command Prompt */
344#endif
345#else
346#if (BFIN_CPU == ADSP_BF531)
347#define CFG_PROMPT "bf531> " /* Monitor Command Prompt */
348#elif (BFIN_CPU == ADSP_BF532)
349#define CFG_PROMPT "bf532> " /* Monitor Command Prompt */
350#else
351#define CFG_PROMPT "bf533> " /* Monitor Command Prompt */
352#endif
353#endif
354
355#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
356#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
357#else
358#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
359#endif
360#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
361#define CFG_MAXARGS 16 /* max number of command args */
362#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
363
364#define CONFIG_LOADS_ECHO 1
365
366/*
367 * I2C settings
368 * By default PF2 is used as SDA and PF3 as SCL on the Stamp board
369 */
370#if (CONFIG_SOFT_I2C)
371
372#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;")
373#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
374#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
375#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
376#define I2C_SDA(bit) if(bit) { \
377 *pFIO_FLAG_S = PF_SDA; \
378 asm("ssync;"); \
379 } \
380 else { \
381 *pFIO_FLAG_C = PF_SDA; \
382 asm("ssync;"); \
383 }
384#define I2C_SCL(bit) if(bit) { \
385 *pFIO_FLAG_S = PF_SCL; \
386 asm("ssync;"); \
387 } \
388 else { \
389 *pFIO_FLAG_C = PF_SCL; \
390 asm("ssync;"); \
391 }
392#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
393
394#define CFG_I2C_SPEED 50000
395#define CFG_I2C_SLAVE 0xFE
396#endif /* CONFIG_SOFT_I2C */
397
398/*
399 * Compact Flash settings
400 */
401
402/* Enabled below option for CF support */
403/* #define CONFIG_STAMP_CF 1 */
404
405#if defined(CONFIG_STAMP_CF) && (CONFIG_COMMANDS & CFG_CMD_IDE)
406
407#define CONFIG_MISC_INIT_R 1
408#define CONFIG_DOS_PARTITION 1
409/*
410 * IDE/ATA stuff
411 */
412#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
413#undef CONFIG_IDE_LED /* no led for ide supported */
414#undef CONFIG_IDE_RESET /* no reset for ide supported */
415
416#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
417#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
418
419#define CFG_ATA_BASE_ADDR 0x20200000
420#define CFG_ATA_IDE0_OFFSET 0x0000
421
422#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
423#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
424#define CFG_ATA_ALT_OFFSET 0x0007 /* Offset for alternate registers */
425
426#define CFG_ATA_STRIDE 2
427#endif
428
429/*
430 * Miscellaneous configurable options
431 */
432
433#define CFG_HZ 1000 /* 1ms time tick */
434
435#define CFG_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */
436
437#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
438
439#define CONFIG_SPI
440
441#ifdef CONFIG_VIDEO
442#if (CONFIG_VIDEO)
443#define CONFIG_SPLASH_SCREEN 1
444#define CONFIG_SILENT_CONSOLE 1
445#else
446#undef CONFIG_VIDEO
447#endif
448#endif
449
450/*
451 * FLASH organization and environment definitions
452 */
453#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
454
455/* 0xFF, 0xBBC3BBc3, 0x99B39983 */
456/*#define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
457#define AMBCTL0VAL (B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL | \
458 B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN)
459#define AMBCTL1VAL (B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL | \
460 B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN)
461*/
462#define AMGCTLVAL 0xFF
463#define AMBCTL0VAL 0xBBC3BBC3
464#define AMBCTL1VAL 0x99B39983
465#define CF_AMBCTL1VAL 0x99B3ffc2
466
467#ifdef CONFIG_VDSP
468#define ET_EXEC_VDSP 0x8
469#define SHT_STRTAB_VDSP 0x1
470#define ELFSHDRSIZE_VDSP 0x2C
471#define VDSP_ENTRY_ADDR 0xFFA00000
472#endif
473
474
475#endif