Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 1 | /* |
| 2 | * |
| 3 | * See file CREDITS for list of people who contributed to this |
| 4 | * project. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; either version 2 of |
| 9 | * the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 19 | * MA 02111-1307 USA |
| 20 | */ |
| 21 | |
| 22 | #include <common.h> |
Stefan Roese | 34c0a5e | 2005-09-15 11:34:07 +0200 | [diff] [blame] | 23 | #include <ppc4xx.h> |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 24 | #include <asm/processor.h> |
| 25 | #include <spd_sdram.h> |
| 26 | |
Stefan Roese | 34c0a5e | 2005-09-15 11:34:07 +0200 | [diff] [blame] | 27 | extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
| 28 | |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 29 | int board_early_init_f(void) |
| 30 | { |
| 31 | register uint reg; |
| 32 | |
| 33 | /*-------------------------------------------------------------------- |
| 34 | * Setup the external bus controller/chip selects |
| 35 | *-------------------------------------------------------------------*/ |
| 36 | mtdcr(ebccfga, xbcfg); |
| 37 | reg = mfdcr(ebccfgd); |
| 38 | mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */ |
| 39 | |
| 40 | mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */ |
Stefan Roese | 34c0a5e | 2005-09-15 11:34:07 +0200 | [diff] [blame] | 41 | mtebc(pb0cr, 0xfc0da000); /* BAS=0xfc0 64MB r/w 16-bit */ |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 42 | |
| 43 | mtebc(pb1ap, 0x00000000); |
| 44 | mtebc(pb1cr, 0x00000000); |
| 45 | |
| 46 | mtebc(pb2ap, 0x04814500); |
| 47 | /*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */ |
| 48 | |
| 49 | mtebc(pb3ap, 0x00000000); |
| 50 | mtebc(pb3cr, 0x00000000); |
| 51 | |
| 52 | mtebc(pb4ap, 0x00000000); |
| 53 | mtebc(pb4cr, 0x00000000); |
| 54 | |
| 55 | mtebc(pb5ap, 0x00000000); |
| 56 | mtebc(pb5cr, 0x00000000); |
| 57 | |
| 58 | /*-------------------------------------------------------------------- |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 59 | * Setup the GPIO pins |
| 60 | *-------------------------------------------------------------------*/ |
| 61 | /*CPLD cs */ |
| 62 | /*setup Address lines for flash sizes larger than 16Meg. */ |
| 63 | out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x40010000); |
| 64 | out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40010000); |
| 65 | out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x40000000); |
| 66 | |
| 67 | /*setup emac */ |
| 68 | out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080); |
| 69 | out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40); |
| 70 | out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55); |
| 71 | out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000); |
| 72 | out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000); |
| 73 | |
| 74 | /*UART1 */ |
| 75 | out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000); |
| 76 | out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000); |
| 77 | out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000); |
| 78 | |
Stefan Roese | e190290 | 2005-10-28 12:21:06 +0200 | [diff] [blame] | 79 | /* external interrupts IRQ0...3 */ |
| 80 | out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x0f000000); |
| 81 | out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500); |
| 82 | out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500); |
| 83 | |
Stefan Roese | 34c0a5e | 2005-09-15 11:34:07 +0200 | [diff] [blame] | 84 | #if 0 /* test-only */ |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 85 | /*setup USB 2.0 */ |
| 86 | out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000); |
| 87 | out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000); |
| 88 | out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf); |
| 89 | out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa); |
| 90 | out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500); |
Stefan Roese | 34c0a5e | 2005-09-15 11:34:07 +0200 | [diff] [blame] | 91 | #endif |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 92 | |
| 93 | /*-------------------------------------------------------------------- |
Stefan Roese | ef04a0a | 2005-11-03 08:31:33 +0100 | [diff] [blame^] | 94 | * Setup the interrupt controller polarities, triggers, etc. |
| 95 | *-------------------------------------------------------------------*/ |
| 96 | mtdcr(uic0sr, 0xffffffff); /* clear all */ |
| 97 | mtdcr(uic0er, 0x00000000); /* disable all */ |
| 98 | mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */ |
| 99 | mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ |
| 100 | mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ |
| 101 | mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ |
| 102 | mtdcr(uic0sr, 0xffffffff); /* clear all */ |
| 103 | |
| 104 | mtdcr(uic1sr, 0xffffffff); /* clear all */ |
| 105 | mtdcr(uic1er, 0x00000000); /* disable all */ |
| 106 | mtdcr(uic1cr, 0x00000000); /* all non-critical */ |
| 107 | mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ |
| 108 | mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ |
| 109 | mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ |
| 110 | mtdcr(uic1sr, 0xffffffff); /* clear all */ |
| 111 | |
| 112 | /*-------------------------------------------------------------------- |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 113 | * Setup other serial configuration |
| 114 | *-------------------------------------------------------------------*/ |
| 115 | mfsdr(sdr_pci0, reg); |
| 116 | mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */ |
| 117 | mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */ |
| 118 | mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */ |
| 119 | |
| 120 | /*clear tmrclk divisor */ |
| 121 | *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00; |
| 122 | |
| 123 | /*enable ethernet */ |
| 124 | *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0; |
| 125 | |
Stefan Roese | 34c0a5e | 2005-09-15 11:34:07 +0200 | [diff] [blame] | 126 | #if 0 /* test-only */ |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 127 | /*enable usb 1.1 fs device and remove usb 2.0 reset */ |
| 128 | *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00; |
Stefan Roese | 34c0a5e | 2005-09-15 11:34:07 +0200 | [diff] [blame] | 129 | #endif |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 130 | |
| 131 | /*get rid of flash write protect */ |
| 132 | *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x40; |
| 133 | |
| 134 | return 0; |
| 135 | } |
| 136 | |
Stefan Roese | 34c0a5e | 2005-09-15 11:34:07 +0200 | [diff] [blame] | 137 | int misc_init_r (void) |
| 138 | { |
| 139 | DECLARE_GLOBAL_DATA_PTR; |
| 140 | uint pbcr; |
| 141 | int size_val = 0; |
| 142 | |
| 143 | /* Re-do sizing to get full correct info */ |
| 144 | mtdcr(ebccfga, pb0cr); |
| 145 | pbcr = mfdcr(ebccfgd); |
| 146 | switch (gd->bd->bi_flashsize) { |
| 147 | case 1 << 20: |
| 148 | size_val = 0; |
| 149 | break; |
| 150 | case 2 << 20: |
| 151 | size_val = 1; |
| 152 | break; |
| 153 | case 4 << 20: |
| 154 | size_val = 2; |
| 155 | break; |
| 156 | case 8 << 20: |
| 157 | size_val = 3; |
| 158 | break; |
| 159 | case 16 << 20: |
| 160 | size_val = 4; |
| 161 | break; |
| 162 | case 32 << 20: |
| 163 | size_val = 5; |
| 164 | break; |
| 165 | case 64 << 20: |
| 166 | size_val = 6; |
| 167 | break; |
| 168 | case 128 << 20: |
| 169 | size_val = 7; |
| 170 | break; |
| 171 | } |
| 172 | pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); |
| 173 | mtdcr(ebccfga, pb0cr); |
| 174 | mtdcr(ebccfgd, pbcr); |
| 175 | |
| 176 | /* Monitor protection ON by default */ |
| 177 | (void)flash_protect(FLAG_PROTECT_SET, |
| 178 | -CFG_MONITOR_LEN, |
| 179 | 0xffffffff, |
| 180 | &flash_info[0]); |
| 181 | |
| 182 | return 0; |
| 183 | } |
| 184 | |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 185 | int checkboard(void) |
| 186 | { |
| 187 | sys_info_t sysinfo; |
Stefan Roese | 93b17ec | 2005-10-03 15:27:50 +0200 | [diff] [blame] | 188 | unsigned char *s = getenv("serial#"); |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 189 | |
| 190 | get_sys_info(&sysinfo); |
| 191 | |
Stefan Roese | 93b17ec | 2005-10-03 15:27:50 +0200 | [diff] [blame] | 192 | printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board"); |
| 193 | if (s != NULL) { |
| 194 | puts(", serial# "); |
| 195 | puts(s); |
| 196 | } |
| 197 | putc('\n'); |
| 198 | |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 199 | printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000); |
| 200 | printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000); |
| 201 | printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000); |
| 202 | printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000); |
Stefan Roese | 93b17ec | 2005-10-03 15:27:50 +0200 | [diff] [blame] | 203 | printf("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000); |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 204 | printf("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000); |
Stefan Roese | 34c0a5e | 2005-09-15 11:34:07 +0200 | [diff] [blame] | 205 | |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 206 | return (0); |
| 207 | } |
| 208 | |
| 209 | /************************************************************************* |
| 210 | * sdram_init -- doesn't use serial presence detect. |
| 211 | * |
| 212 | * Assumes: 256 MB, ECC, non-registered |
| 213 | * PLB @ 133 MHz |
| 214 | * |
| 215 | ************************************************************************/ |
| 216 | void sdram_init(void) |
| 217 | { |
| 218 | register uint reg; |
| 219 | |
| 220 | /*-------------------------------------------------------------------- |
| 221 | * Setup some default |
| 222 | *------------------------------------------------------------------*/ |
| 223 | mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */ |
| 224 | mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ |
| 225 | mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ |
| 226 | mtsdram(mem_clktr, 0x40000000); /* ?? */ |
| 227 | mtsdram(mem_wddctr, 0x40000000); /* ?? */ |
| 228 | |
| 229 | /*clear this first, if the DDR is enabled by a debugger |
| 230 | then you can not make changes. */ |
| 231 | mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */ |
| 232 | |
| 233 | /*-------------------------------------------------------------------- |
| 234 | * Setup for board-specific specific mem |
| 235 | *------------------------------------------------------------------*/ |
| 236 | /* |
| 237 | * Following for CAS Latency = 2.5 @ 133 MHz PLB |
| 238 | */ |
| 239 | mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ |
| 240 | mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */ |
Stefan Roese | 34c0a5e | 2005-09-15 11:34:07 +0200 | [diff] [blame] | 241 | |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 242 | mtsdram(mem_tr0, 0x410a4012); /* ?? */ |
| 243 | mtsdram(mem_tr1, 0x8080080b); /* ?? */ |
| 244 | mtsdram(mem_rtr, 0x04080000); /* ?? */ |
| 245 | mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ |
| 246 | mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */ |
| 247 | udelay(400); /* Delay 200 usecs (min) */ |
| 248 | |
| 249 | /*-------------------------------------------------------------------- |
| 250 | * Enable the controller, then wait for DCEN to complete |
| 251 | *------------------------------------------------------------------*/ |
| 252 | mtsdram(mem_cfg0, 0x84000000); /* Enable */ |
| 253 | |
| 254 | for (;;) { |
| 255 | mfsdram(mem_mcsts, reg); |
| 256 | if (reg & 0x80000000) |
| 257 | break; |
| 258 | } |
| 259 | } |
| 260 | |
| 261 | /************************************************************************* |
| 262 | * long int initdram |
| 263 | * |
| 264 | ************************************************************************/ |
| 265 | long int initdram(int board) |
| 266 | { |
| 267 | sdram_init(); |
| 268 | return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024); /* return bytes */ |
| 269 | } |
| 270 | |
| 271 | #if defined(CFG_DRAM_TEST) |
| 272 | int testdram(void) |
| 273 | { |
| 274 | unsigned long *mem = (unsigned long *)0; |
| 275 | const unsigned long kend = (1024 / sizeof(unsigned long)); |
| 276 | unsigned long k, n; |
| 277 | |
| 278 | mtmsr(0); |
| 279 | |
| 280 | for (k = 0; k < CFG_KBYTES_SDRAM; |
| 281 | ++k, mem += (1024 / sizeof(unsigned long))) { |
| 282 | if ((k & 1023) == 0) { |
| 283 | printf("%3d MB\r", k / 1024); |
| 284 | } |
| 285 | |
| 286 | memset(mem, 0xaaaaaaaa, 1024); |
| 287 | for (n = 0; n < kend; ++n) { |
| 288 | if (mem[n] != 0xaaaaaaaa) { |
| 289 | printf("SDRAM test fails at: %08x\n", |
| 290 | (uint) & mem[n]); |
| 291 | return 1; |
| 292 | } |
| 293 | } |
| 294 | |
| 295 | memset(mem, 0x55555555, 1024); |
| 296 | for (n = 0; n < kend; ++n) { |
| 297 | if (mem[n] != 0x55555555) { |
| 298 | printf("SDRAM test fails at: %08x\n", |
| 299 | (uint) & mem[n]); |
| 300 | return 1; |
| 301 | } |
| 302 | } |
| 303 | } |
| 304 | printf("SDRAM test passes\n"); |
| 305 | return 0; |
| 306 | } |
| 307 | #endif |
| 308 | |
| 309 | /************************************************************************* |
| 310 | * pci_pre_init |
| 311 | * |
| 312 | * This routine is called just prior to registering the hose and gives |
| 313 | * the board the opportunity to check things. Returning a value of zero |
| 314 | * indicates that things are bad & PCI initialization should be aborted. |
| 315 | * |
| 316 | * Different boards may wish to customize the pci controller structure |
| 317 | * (add regions, override default access routines, etc) or perform |
| 318 | * certain pre-initialization actions. |
| 319 | * |
| 320 | ************************************************************************/ |
| 321 | #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) |
| 322 | int pci_pre_init(struct pci_controller *hose) |
| 323 | { |
| 324 | unsigned long strap; |
| 325 | unsigned long addr; |
| 326 | |
| 327 | /*--------------------------------------------------------------------------+ |
Stefan Roese | 34c0a5e | 2005-09-15 11:34:07 +0200 | [diff] [blame] | 328 | * Bamboo is always configured as the host & requires the |
| 329 | * PCI arbiter to be enabled. |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 330 | *--------------------------------------------------------------------------*/ |
| 331 | mfsdr(sdr_sdstp1, strap); |
| 332 | if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) { |
| 333 | printf("PCI: SDR0_STRP1[PAE] not set.\n"); |
| 334 | printf("PCI: Configuration aborted.\n"); |
| 335 | return 0; |
| 336 | } |
| 337 | |
Stefan Roese | 34c0a5e | 2005-09-15 11:34:07 +0200 | [diff] [blame] | 338 | /*-------------------------------------------------------------------------+ |
| 339 | | Set priority for all PLB3 devices to 0. |
| 340 | | Set PLB3 arbiter to fair mode. |
| 341 | +-------------------------------------------------------------------------*/ |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 342 | mfsdr(sdr_amp1, addr); |
| 343 | mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); |
| 344 | addr = mfdcr(plb3_acr); |
| 345 | mtdcr(plb3_acr, addr | 0x80000000); |
| 346 | |
Stefan Roese | 34c0a5e | 2005-09-15 11:34:07 +0200 | [diff] [blame] | 347 | /*-------------------------------------------------------------------------+ |
| 348 | | Set priority for all PLB4 devices to 0. |
| 349 | +-------------------------------------------------------------------------*/ |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 350 | mfsdr(sdr_amp0, addr); |
| 351 | mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); |
| 352 | addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ |
| 353 | mtdcr(plb4_acr, addr); |
| 354 | |
Stefan Roese | 34c0a5e | 2005-09-15 11:34:07 +0200 | [diff] [blame] | 355 | /*-------------------------------------------------------------------------+ |
| 356 | | Set Nebula PLB4 arbiter to fair mode. |
| 357 | +-------------------------------------------------------------------------*/ |
| 358 | /* Segment0 */ |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 359 | addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; |
| 360 | addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; |
| 361 | addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; |
| 362 | addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; |
| 363 | mtdcr(plb0_acr, addr); |
| 364 | |
| 365 | /* Segment1 */ |
| 366 | addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; |
| 367 | addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; |
| 368 | addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; |
| 369 | addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; |
| 370 | mtdcr(plb1_acr, addr); |
| 371 | |
| 372 | return 1; |
| 373 | } |
| 374 | #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ |
| 375 | |
| 376 | /************************************************************************* |
| 377 | * pci_target_init |
| 378 | * |
| 379 | * The bootstrap configuration provides default settings for the pci |
| 380 | * inbound map (PIM). But the bootstrap config choices are limited and |
| 381 | * may not be sufficient for a given board. |
| 382 | * |
| 383 | ************************************************************************/ |
| 384 | #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) |
| 385 | void pci_target_init(struct pci_controller *hose) |
| 386 | { |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 387 | /*--------------------------------------------------------------------------+ |
| 388 | * Set up Direct MMIO registers |
| 389 | *--------------------------------------------------------------------------*/ |
Stefan Roese | 34c0a5e | 2005-09-15 11:34:07 +0200 | [diff] [blame] | 390 | /*--------------------------------------------------------------------------+ |
| 391 | | PowerPC440 EP PCI Master configuration. |
| 392 | | Map one 1Gig range of PLB/processor addresses to PCI memory space. |
| 393 | | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF |
| 394 | | Use byte reversed out routines to handle endianess. |
| 395 | | Make this region non-prefetchable. |
| 396 | +--------------------------------------------------------------------------*/ |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 397 | out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ |
| 398 | out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ |
| 399 | out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ |
| 400 | out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ |
| 401 | out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ |
| 402 | |
| 403 | out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ |
| 404 | out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ |
| 405 | out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ |
| 406 | out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ |
| 407 | out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ |
| 408 | |
| 409 | out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ |
| 410 | out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ |
| 411 | out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ |
| 412 | out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ |
| 413 | |
| 414 | /*--------------------------------------------------------------------------+ |
| 415 | * Set up Configuration registers |
| 416 | *--------------------------------------------------------------------------*/ |
| 417 | |
| 418 | /* Program the board's subsystem id/vendor id */ |
| 419 | pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, |
| 420 | CFG_PCI_SUBSYS_VENDORID); |
| 421 | pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); |
| 422 | |
| 423 | /* Configure command register as bus master */ |
| 424 | pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); |
| 425 | |
| 426 | /* 240nS PCI clock */ |
| 427 | pci_write_config_word(0, PCI_LATENCY_TIMER, 1); |
| 428 | |
| 429 | /* No error reporting */ |
| 430 | pci_write_config_word(0, PCI_ERREN, 0); |
| 431 | |
| 432 | pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); |
| 433 | |
| 434 | } |
| 435 | #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ |
| 436 | |
| 437 | /************************************************************************* |
| 438 | * pci_master_init |
| 439 | * |
| 440 | ************************************************************************/ |
| 441 | #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) |
| 442 | void pci_master_init(struct pci_controller *hose) |
| 443 | { |
| 444 | unsigned short temp_short; |
| 445 | |
Stefan Roese | 34c0a5e | 2005-09-15 11:34:07 +0200 | [diff] [blame] | 446 | /*--------------------------------------------------------------------------+ |
| 447 | | Write the PowerPC440 EP PCI Configuration regs. |
| 448 | | Enable PowerPC440 EP to be a master on the PCI bus (PMM). |
| 449 | | Enable PowerPC440 EP to act as a PCI memory target (PTM). |
| 450 | +--------------------------------------------------------------------------*/ |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 451 | pci_read_config_word(0, PCI_COMMAND, &temp_short); |
| 452 | pci_write_config_word(0, PCI_COMMAND, |
| 453 | temp_short | PCI_COMMAND_MASTER | |
| 454 | PCI_COMMAND_MEMORY); |
| 455 | } |
| 456 | #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ |
| 457 | |
| 458 | /************************************************************************* |
| 459 | * is_pci_host |
| 460 | * |
| 461 | * This routine is called to determine if a pci scan should be |
| 462 | * performed. With various hardware environments (especially cPCI and |
| 463 | * PPMC) it's insufficient to depend on the state of the arbiter enable |
| 464 | * bit in the strap register, or generic host/adapter assumptions. |
| 465 | * |
| 466 | * Rather than hard-code a bad assumption in the general 440 code, the |
| 467 | * 440 pci code requires the board to decide at runtime. |
| 468 | * |
| 469 | * Return 0 for adapter mode, non-zero for host (monarch) mode. |
| 470 | * |
| 471 | * |
| 472 | ************************************************************************/ |
| 473 | #if defined(CONFIG_PCI) |
| 474 | int is_pci_host(struct pci_controller *hose) |
| 475 | { |
| 476 | /* Bamboo is always configured as host. */ |
| 477 | return (1); |
| 478 | } |
| 479 | #endif /* defined(CONFIG_PCI) */ |
| 480 | |
| 481 | /************************************************************************* |
| 482 | * hw_watchdog_reset |
| 483 | * |
| 484 | * This routine is called to reset (keep alive) the watchdog timer |
| 485 | * |
| 486 | ************************************************************************/ |
| 487 | #if defined(CONFIG_HW_WATCHDOG) |
| 488 | void hw_watchdog_reset(void) |
| 489 | { |
Stefan Roese | 34c0a5e | 2005-09-15 11:34:07 +0200 | [diff] [blame] | 490 | |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 491 | } |
| 492 | #endif |