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wdenkaffae2b2002-08-17 09:36:01 +00001/*
2 * (C) Copyright 2001
3 * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkaffae2b2002-08-17 09:36:01 +00006 */
7
8/*
9 * Date & Time support for ST Electronics M48T35Ax RTC
10 */
11
12/*#define DEBUG */
13
14
15#include <common.h>
16#include <command.h>
17#include <rtc.h>
18#include <config.h>
19
Michal Simek871c18d2008-07-14 19:45:37 +020020#if defined(CONFIG_CMD_DATE)
wdenkaffae2b2002-08-17 09:36:01 +000021
22static uchar rtc_read (uchar reg);
23static void rtc_write (uchar reg, uchar val);
wdenkaffae2b2002-08-17 09:36:01 +000024
25/* ------------------------------------------------------------------------- */
26
Yuri Tikhonovb73a19e2008-03-20 17:56:04 +030027int rtc_get (struct rtc_time *tmp)
wdenkaffae2b2002-08-17 09:36:01 +000028{
29 uchar sec, min, hour, cent_day, date, month, year;
30 uchar ccr; /* Clock control register */
31
32 /* Lock RTC for read using clock control register */
33 ccr = rtc_read(0);
34 ccr = ccr | 0x40;
35 rtc_write(0, ccr);
36
37 sec = rtc_read (0x1);
38 min = rtc_read (0x2);
39 hour = rtc_read (0x3);
40 cent_day= rtc_read (0x4);
41 date = rtc_read (0x5);
42 month = rtc_read (0x6);
43 year = rtc_read (0x7);
44
45 /* UNLock RTC */
46 ccr = rtc_read(0);
47 ccr = ccr & 0xBF;
48 rtc_write(0, ccr);
49
50 debug ( "Get RTC year: %02x month: %02x date: %02x cent_day: %02x "
51 "hr: %02x min: %02x sec: %02x\n",
52 year, month, date, cent_day,
53 hour, min, sec );
54
55 tmp->tm_sec = bcd2bin (sec & 0x7F);
56 tmp->tm_min = bcd2bin (min & 0x7F);
57 tmp->tm_hour = bcd2bin (hour & 0x3F);
58 tmp->tm_mday = bcd2bin (date & 0x3F);
59 tmp->tm_mon = bcd2bin (month & 0x1F);
60 tmp->tm_year = bcd2bin (year) + ((cent_day & 0x10) ? 2000 : 1900);
61 tmp->tm_wday = bcd2bin (cent_day & 0x07);
62 tmp->tm_yday = 0;
63 tmp->tm_isdst= 0;
64
65 debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
66 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
67 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
Yuri Tikhonovb73a19e2008-03-20 17:56:04 +030068
69 return 0;
wdenkaffae2b2002-08-17 09:36:01 +000070}
71
Jean-Christophe PLAGNIOL-VILLARDd1e23192008-09-01 23:06:23 +020072int rtc_set (struct rtc_time *tmp)
wdenkaffae2b2002-08-17 09:36:01 +000073{
74 uchar ccr; /* Clock control register */
75 uchar century;
76
77 debug ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
78 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
79 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
80
81 /* Lock RTC for write using clock control register */
82 ccr = rtc_read(0);
83 ccr = ccr | 0x80;
84 rtc_write(0, ccr);
85
86 rtc_write (0x07, bin2bcd(tmp->tm_year % 100));
87 rtc_write (0x06, bin2bcd(tmp->tm_mon));
88 rtc_write (0x05, bin2bcd(tmp->tm_mday));
89
90 century = ((tmp->tm_year >= 2000) ? 0x10 : 0) | 0x20;
91 rtc_write (0x04, bin2bcd(tmp->tm_wday) | century);
92
93 rtc_write (0x03, bin2bcd(tmp->tm_hour));
94 rtc_write (0x02, bin2bcd(tmp->tm_min ));
95 rtc_write (0x01, bin2bcd(tmp->tm_sec ));
96
97 /* UNLock RTC */
98 ccr = rtc_read(0);
99 ccr = ccr & 0x7F;
100 rtc_write(0, ccr);
Jean-Christophe PLAGNIOL-VILLARDd1e23192008-09-01 23:06:23 +0200101
102 return 0;
wdenkaffae2b2002-08-17 09:36:01 +0000103}
104
105void rtc_reset (void)
106{
107 uchar val;
108
109 /* Clear all clock control registers */
110 rtc_write (0x0, 0x80); /* No Read Lock or calibration */
111
112 /* Clear stop bit */
113 val = rtc_read (0x1);
114 val &= 0x7f;
115 rtc_write(0x1, val);
116
117 /* Enable century / disable frequency test */
118 val = rtc_read (0x4);
119 val = (val & 0xBF) | 0x20;
120 rtc_write(0x4, val);
121
122 /* Clear write lock */
123 rtc_write(0x0, 0);
124}
125
126/* ------------------------------------------------------------------------- */
127
128static uchar rtc_read (uchar reg)
129{
Masahiro Yamadaa4ca3792016-09-06 22:17:39 +0900130 return *(unsigned char *)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131 ((CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - 8) + reg);
wdenkaffae2b2002-08-17 09:36:01 +0000132}
133
134static void rtc_write (uchar reg, uchar val)
135{
136 *(unsigned char *)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137 ((CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - 8) + reg) = val;
wdenkaffae2b2002-08-17 09:36:01 +0000138}
139
Jon Loeliger068b60a2007-07-10 10:27:39 -0500140#endif