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gerrit.cesnet.cz / github / trini / u-boot / ee44fb298dd9270aa64bb2cb5a93a43f6a85d70e / . / board / freescale / p2041rdb / tlb.c
blob: 43f28ed14ca0869ea827566c5221b86f5dc93acd [file] [log] [blame]
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <common.h>
24#include <asm/mmu.h>
25
26struct fsl_e_tlb_entry tlb_table[] = {
27 /* TLB 0 - for temp stack in cache */
28 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
29 CONFIG_SYS_INIT_RAM_ADDR_PHYS,
30 MAS3_SX|MAS3_SW|MAS3_SR, 0,
31 0, 0, BOOKE_PAGESZ_4K, 0),
32 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
33 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
34 MAS3_SX|MAS3_SW|MAS3_SR, 0,
35 0, 0, BOOKE_PAGESZ_4K, 0),
36 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
37 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
38 MAS3_SX|MAS3_SW|MAS3_SR, 0,
39 0, 0, BOOKE_PAGESZ_4K, 0),
40 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
41 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
42 MAS3_SX|MAS3_SW|MAS3_SR, 0,
43 0, 0, BOOKE_PAGESZ_4K, 0),
44
45 SET_TLB_ENTRY(0, CPLD_BASE, CPLD_BASE_PHYS,
46 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
47 0, 0, BOOKE_PAGESZ_4K, 0),
48
49 /* TLB 1 */
50 /* *I*** - Covers boot page */
51#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
52 /*
53 * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
54 * SRAM is at 0xfff00000, it covered the 0xfffff000.
55 */
56 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
57 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
58 0, 0, BOOKE_PAGESZ_1M, 1),
59#else
60 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
61 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
62 0, 0, BOOKE_PAGESZ_4K, 1),
63#endif
64
65 /* *I*G* - CCSRBAR */
66 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
67 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
68 0, 1, BOOKE_PAGESZ_16M, 1),
69
70 /* *I*G* - Flash, localbus */
71 /* This will be changed to *I*G* after relocation to RAM. */
72 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
73 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
74 0, 2, BOOKE_PAGESZ_256M, 1),
75
76 /* *I*G* - PCI */
77 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
78 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
79 0, 3, BOOKE_PAGESZ_1G, 1),
80
81 /* *I*G* - PCI */
82 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
83 CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
84 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
85 0, 4, BOOKE_PAGESZ_256M, 1),
86
87 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
88 CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
89 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
90 0, 5, BOOKE_PAGESZ_256M, 1),
91
92 /* *I*G* - PCI I/O */
93 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
94 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
95 0, 6, BOOKE_PAGESZ_256K, 1),
96
97 /* Bman/Qman */
98 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
99 MAS3_SX|MAS3_SW|MAS3_SR, 0,
100 0, 9, BOOKE_PAGESZ_1M, 1),
101 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
102 CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
103 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
104 0, 10, BOOKE_PAGESZ_1M, 1),
105 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
106 MAS3_SX|MAS3_SW|MAS3_SR, 0,
107 0, 11, BOOKE_PAGESZ_1M, 1),
108 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
109 CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
110 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
111 0, 12, BOOKE_PAGESZ_1M, 1),
112#ifdef CONFIG_SYS_DCSRBAR_PHYS
113 SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
114 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
115 0, 13, BOOKE_PAGESZ_4M, 1),
116#endif
117};
118
119int num_tlb_entries = ARRAY_SIZE(tlb_table);