Ian Campbell | fe1b4db | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2007-2012 |
| 3 | * Allwinner Technology Co., Ltd. <www.allwinnertech.com> |
| 4 | * Tom Cubie <tangliang@allwinnertech.com> |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 7 | */ |
| 8 | |
| 9 | #ifndef _SUNXI_GPIO_H |
| 10 | #define _SUNXI_GPIO_H |
| 11 | |
| 12 | #include <linux/types.h> |
Hans de Goede | e373aad | 2014-10-22 16:47:45 +0800 | [diff] [blame] | 13 | #include <asm/arch/cpu.h> |
Ian Campbell | fe1b4db | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 14 | |
| 15 | /* |
| 16 | * sunxi has 9 banks of gpio, they are: |
| 17 | * PA0 - PA17 | PB0 - PB23 | PC0 - PC24 |
| 18 | * PD0 - PD27 | PE0 - PE31 | PF0 - PF5 |
| 19 | * PG0 - PG9 | PH0 - PH27 | PI0 - PI12 |
| 20 | */ |
| 21 | |
| 22 | #define SUNXI_GPIO_A 0 |
| 23 | #define SUNXI_GPIO_B 1 |
| 24 | #define SUNXI_GPIO_C 2 |
| 25 | #define SUNXI_GPIO_D 3 |
| 26 | #define SUNXI_GPIO_E 4 |
| 27 | #define SUNXI_GPIO_F 5 |
| 28 | #define SUNXI_GPIO_G 6 |
| 29 | #define SUNXI_GPIO_H 7 |
| 30 | #define SUNXI_GPIO_I 8 |
Hans de Goede | e373aad | 2014-10-22 16:47:45 +0800 | [diff] [blame] | 31 | |
| 32 | /* |
| 33 | * This defines the number of GPIO banks for the _main_ GPIO controller. |
| 34 | * You should fix up the padding in struct sunxi_gpio_reg below if you |
| 35 | * change this. |
| 36 | */ |
Ian Campbell | fe1b4db | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 37 | #define SUNXI_GPIO_BANKS 9 |
| 38 | |
Hans de Goede | e373aad | 2014-10-22 16:47:45 +0800 | [diff] [blame] | 39 | /* |
| 40 | * sun6i/sun8i and later SoCs have an additional GPIO controller (R_PIO) |
| 41 | * at a different register offset. |
| 42 | * |
| 43 | * sun6i has 2 banks: |
| 44 | * PL0 - PL8 | PM0 - PM7 |
| 45 | * |
| 46 | * sun8i has 1 bank: |
| 47 | * PL0 - PL11 |
| 48 | */ |
| 49 | #define SUNXI_GPIO_L 11 |
| 50 | #define SUNXI_GPIO_M 12 |
| 51 | |
Ian Campbell | fe1b4db | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 52 | struct sunxi_gpio { |
| 53 | u32 cfg[4]; |
| 54 | u32 dat; |
| 55 | u32 drv[2]; |
| 56 | u32 pull[2]; |
| 57 | }; |
| 58 | |
| 59 | /* gpio interrupt control */ |
| 60 | struct sunxi_gpio_int { |
| 61 | u32 cfg[3]; |
| 62 | u32 ctl; |
| 63 | u32 sta; |
| 64 | u32 deb; /* interrupt debounce */ |
| 65 | }; |
| 66 | |
| 67 | struct sunxi_gpio_reg { |
| 68 | struct sunxi_gpio gpio_bank[SUNXI_GPIO_BANKS]; |
| 69 | u8 res[0xbc]; |
| 70 | struct sunxi_gpio_int gpio_int; |
| 71 | }; |
| 72 | |
Hans de Goede | e373aad | 2014-10-22 16:47:45 +0800 | [diff] [blame] | 73 | #define BANK_TO_GPIO(bank) (((bank) < SUNXI_GPIO_L) ? \ |
| 74 | &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \ |
| 75 | &((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - SUNXI_GPIO_L]) |
Ian Campbell | fe1b4db | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 76 | |
| 77 | #define GPIO_BANK(pin) ((pin) >> 5) |
| 78 | #define GPIO_NUM(pin) ((pin) & 0x1f) |
| 79 | |
| 80 | #define GPIO_CFG_INDEX(pin) (((pin) & 0x1f) >> 3) |
| 81 | #define GPIO_CFG_OFFSET(pin) ((((pin) & 0x1f) & 0x7) << 2) |
| 82 | |
| 83 | #define GPIO_DRV_INDEX(pin) (((pin) & 0x1f) >> 4) |
| 84 | #define GPIO_DRV_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1) |
| 85 | |
| 86 | #define GPIO_PULL_INDEX(pin) (((pin) & 0x1f) >> 4) |
| 87 | #define GPIO_PULL_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1) |
| 88 | |
| 89 | /* GPIO bank sizes */ |
| 90 | #define SUNXI_GPIO_A_NR 32 |
| 91 | #define SUNXI_GPIO_B_NR 32 |
| 92 | #define SUNXI_GPIO_C_NR 32 |
| 93 | #define SUNXI_GPIO_D_NR 32 |
| 94 | #define SUNXI_GPIO_E_NR 32 |
| 95 | #define SUNXI_GPIO_F_NR 32 |
| 96 | #define SUNXI_GPIO_G_NR 32 |
| 97 | #define SUNXI_GPIO_H_NR 32 |
| 98 | #define SUNXI_GPIO_I_NR 32 |
Hans de Goede | e373aad | 2014-10-22 16:47:45 +0800 | [diff] [blame] | 99 | #define SUNXI_GPIO_L_NR 32 |
| 100 | #define SUNXI_GPIO_M_NR 32 |
Ian Campbell | fe1b4db | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 101 | |
| 102 | #define SUNXI_GPIO_NEXT(__gpio) \ |
| 103 | ((__gpio##_START) + (__gpio##_NR) + 0) |
| 104 | |
| 105 | enum sunxi_gpio_number { |
| 106 | SUNXI_GPIO_A_START = 0, |
| 107 | SUNXI_GPIO_B_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_A), |
| 108 | SUNXI_GPIO_C_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_B), |
| 109 | SUNXI_GPIO_D_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_C), |
| 110 | SUNXI_GPIO_E_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_D), |
| 111 | SUNXI_GPIO_F_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_E), |
| 112 | SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F), |
| 113 | SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G), |
| 114 | SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H), |
Hans de Goede | e373aad | 2014-10-22 16:47:45 +0800 | [diff] [blame] | 115 | SUNXI_GPIO_L_START = 352, |
| 116 | SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L), |
Ian Campbell | fe1b4db | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 117 | }; |
| 118 | |
| 119 | /* SUNXI GPIO number definitions */ |
| 120 | #define SUNXI_GPA(_nr) (SUNXI_GPIO_A_START + (_nr)) |
| 121 | #define SUNXI_GPB(_nr) (SUNXI_GPIO_B_START + (_nr)) |
| 122 | #define SUNXI_GPC(_nr) (SUNXI_GPIO_C_START + (_nr)) |
| 123 | #define SUNXI_GPD(_nr) (SUNXI_GPIO_D_START + (_nr)) |
| 124 | #define SUNXI_GPE(_nr) (SUNXI_GPIO_E_START + (_nr)) |
| 125 | #define SUNXI_GPF(_nr) (SUNXI_GPIO_F_START + (_nr)) |
| 126 | #define SUNXI_GPG(_nr) (SUNXI_GPIO_G_START + (_nr)) |
| 127 | #define SUNXI_GPH(_nr) (SUNXI_GPIO_H_START + (_nr)) |
| 128 | #define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr)) |
Hans de Goede | e373aad | 2014-10-22 16:47:45 +0800 | [diff] [blame] | 129 | #define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr)) |
| 130 | #define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr)) |
Ian Campbell | fe1b4db | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 131 | |
| 132 | /* GPIO pin function config */ |
| 133 | #define SUNXI_GPIO_INPUT 0 |
| 134 | #define SUNXI_GPIO_OUTPUT 1 |
| 135 | |
| 136 | #define SUNXI_GPA0_EMAC 2 |
| 137 | #define SUN7I_GPA0_GMAC 5 |
| 138 | |
| 139 | #define SUNXI_GPB0_TWI0 2 |
| 140 | |
| 141 | #define SUN4I_GPB22_UART0_TX 2 |
| 142 | #define SUN4I_GPB23_UART0_RX 2 |
| 143 | |
| 144 | #define SUN5I_GPB19_UART0_TX 2 |
| 145 | #define SUN5I_GPB20_UART0_RX 2 |
| 146 | |
Hans de Goede | bbff84b | 2014-10-03 16:44:57 +0200 | [diff] [blame] | 147 | #define SUN5I_GPG3_SDC1 2 |
| 148 | |
Ian Campbell | fe1b4db | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 149 | #define SUN5I_GPG3_UART1_TX 4 |
| 150 | #define SUN5I_GPG4_UART1_RX 4 |
| 151 | |
| 152 | #define SUNXI_GPC6_SDC2 3 |
| 153 | |
| 154 | #define SUNXI_GPF0_SDC0 2 |
| 155 | |
| 156 | #define SUNXI_GPF2_SDC0 2 |
Chen-Yu Tsai | 7f87ad3 | 2014-10-22 16:47:41 +0800 | [diff] [blame] | 157 | |
Ian Campbell | ed41e62 | 2014-10-24 21:20:47 +0100 | [diff] [blame^] | 158 | #ifdef CONFIG_MACH_SUN8I |
Chen-Yu Tsai | 7f87ad3 | 2014-10-22 16:47:41 +0800 | [diff] [blame] | 159 | #define SUNXI_GPF2_UART0_TX 3 |
| 160 | #define SUNXI_GPF4_UART0_RX 3 |
| 161 | #else |
Ian Campbell | fe1b4db | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 162 | #define SUNXI_GPF2_UART0_TX 4 |
| 163 | #define SUNXI_GPF4_UART0_RX 4 |
Chen-Yu Tsai | 7f87ad3 | 2014-10-22 16:47:41 +0800 | [diff] [blame] | 164 | #endif |
Ian Campbell | fe1b4db | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 165 | |
| 166 | #define SUN4I_GPG0_SDC1 4 |
| 167 | |
| 168 | #define SUN4I_GPH22_SDC1 5 |
| 169 | |
Chen-Yu Tsai | ba1e40f | 2014-10-03 20:16:27 +0800 | [diff] [blame] | 170 | #define SUN6I_GPH20_UART0_TX 2 |
| 171 | #define SUN6I_GPH21_UART0_RX 2 |
| 172 | |
Ian Campbell | fe1b4db | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 173 | #define SUN4I_GPI4_SDC3 2 |
| 174 | |
Chen-Yu Tsai | c757a50 | 2014-10-22 16:47:47 +0800 | [diff] [blame] | 175 | #define SUN8I_GPL2_R_UART_TX 2 |
| 176 | #define SUN8I_GPL3_R_UART_RX 2 |
| 177 | |
Ian Campbell | fe1b4db | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 178 | /* GPIO pin pull-up/down config */ |
| 179 | #define SUNXI_GPIO_PULL_DISABLE 0 |
| 180 | #define SUNXI_GPIO_PULL_UP 1 |
| 181 | #define SUNXI_GPIO_PULL_DOWN 2 |
| 182 | |
| 183 | int sunxi_gpio_set_cfgpin(u32 pin, u32 val); |
| 184 | int sunxi_gpio_get_cfgpin(u32 pin); |
| 185 | int sunxi_gpio_set_drv(u32 pin, u32 val); |
| 186 | int sunxi_gpio_set_pull(u32 pin, u32 val); |
Ian Campbell | abce2c6 | 2014-06-05 19:00:15 +0100 | [diff] [blame] | 187 | int sunxi_name_to_gpio(const char *name); |
| 188 | #define name_to_gpio(name) sunxi_name_to_gpio(name) |
Ian Campbell | fe1b4db | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 189 | |
| 190 | #endif /* _SUNXI_GPIO_H */ |