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Jean-Christophe PLAGNIOL-VILLARD1332a2a2009-03-21 21:07:59 +01001/*
2 * (C) Copyright 2007-2008
Stelian Popc9e798d2011-11-01 00:00:39 +01003 * Stelian Pop <stelian@popies.net>
Jean-Christophe PLAGNIOL-VILLARD1332a2a2009-03-21 21:07:59 +01004 * Lead Tech Design <www.leadtechdesign.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Jean-Christophe PLAGNIOL-VILLARD1332a2a2009-03-21 21:07:59 +01007 */
8
9#include <common.h>
Xu, Hongf87353f2011-08-01 03:56:32 +000010#include <asm/io.h>
Jean-Christophe PLAGNIOL-VILLARD1332a2a2009-03-21 21:07:59 +010011#include <asm/arch/at91_common.h>
Wenyou Yangeced5a72016-02-03 10:16:49 +080012#include <asm/arch/clk.h>
Jean-Christophe PLAGNIOL-VILLARD1332a2a2009-03-21 21:07:59 +010013#include <asm/arch/gpio.h>
Xu, Hongf87353f2011-08-01 03:56:32 +000014
15/*
16 * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
17 * peripheral pins. Good to have if hardware is soldered optionally
18 * or in case of SPI no slave is selected. Avoid lines to float
19 * needlessly. Use a short local PUP define.
20 *
21 * Due to errata "TXD floats when CTS is inactive" pullups are always
22 * on for TXD pins.
23 */
24#ifdef CONFIG_AT91_GPIO_PULLUP
25# define PUP CONFIG_AT91_GPIO_PULLUP
26#else
27# define PUP 0
28#endif
Jean-Christophe PLAGNIOL-VILLARD1332a2a2009-03-21 21:07:59 +010029
30void at91_serial0_hw_init(void)
31{
Jens Scharsig7f9e8632010-02-03 22:46:46 +010032 at91_set_a_periph(AT91_PIO_PORTA, 6, 1); /* TXD0 */
Xu, Hongf87353f2011-08-01 03:56:32 +000033 at91_set_a_periph(AT91_PIO_PORTA, 7, PUP); /* RXD0 */
Wenyou Yangeced5a72016-02-03 10:16:49 +080034 at91_periph_clk_enable(ATMEL_ID_USART0);
Jean-Christophe PLAGNIOL-VILLARD1332a2a2009-03-21 21:07:59 +010035}
36
37void at91_serial1_hw_init(void)
38{
Jens Scharsig7f9e8632010-02-03 22:46:46 +010039 at91_set_a_periph(AT91_PIO_PORTA, 11, 1); /* TXD1 */
Xu, Hongf87353f2011-08-01 03:56:32 +000040 at91_set_a_periph(AT91_PIO_PORTA, 12, PUP); /* RXD1 */
Wenyou Yangeced5a72016-02-03 10:16:49 +080041 at91_periph_clk_enable(ATMEL_ID_USART1);
Jean-Christophe PLAGNIOL-VILLARD1332a2a2009-03-21 21:07:59 +010042}
43
44void at91_serial2_hw_init(void)
45{
Jens Scharsig7f9e8632010-02-03 22:46:46 +010046 at91_set_a_periph(AT91_PIO_PORTA, 13, 1); /* TXD2 */
Xu, Hongf87353f2011-08-01 03:56:32 +000047 at91_set_a_periph(AT91_PIO_PORTA, 14, PUP); /* RXD2 */
Wenyou Yangeced5a72016-02-03 10:16:49 +080048 at91_periph_clk_enable(ATMEL_ID_USART2);
Jean-Christophe PLAGNIOL-VILLARD1332a2a2009-03-21 21:07:59 +010049}
50
Xu, Hongf87353f2011-08-01 03:56:32 +000051void at91_seriald_hw_init(void)
Jean-Christophe PLAGNIOL-VILLARD1332a2a2009-03-21 21:07:59 +010052{
Xu, Hongf87353f2011-08-01 03:56:32 +000053 at91_set_a_periph(AT91_PIO_PORTA, 21, PUP); /* DRXD */
Jens Scharsig7f9e8632010-02-03 22:46:46 +010054 at91_set_a_periph(AT91_PIO_PORTA, 22, 1); /* DTXD */
Wenyou Yangeced5a72016-02-03 10:16:49 +080055 at91_periph_clk_enable(ATMEL_ID_SYS);
Jean-Christophe PLAGNIOL-VILLARD1332a2a2009-03-21 21:07:59 +010056}
57
Xu, Hongf87353f2011-08-01 03:56:32 +000058#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
Jean-Christophe PLAGNIOL-VILLARD1699da62009-05-13 21:01:13 +020059void at91_spi0_hw_init(unsigned long cs_mask)
60{
Xu, Hongf87353f2011-08-01 03:56:32 +000061 at91_set_a_periph(AT91_PIO_PORTA, 25, PUP); /* SPI0_MISO */
62 at91_set_a_periph(AT91_PIO_PORTA, 26, PUP); /* SPI0_MOSI */
63 at91_set_a_periph(AT91_PIO_PORTA, 27, PUP); /* SPI0_SPCK */
Jean-Christophe PLAGNIOL-VILLARD1699da62009-05-13 21:01:13 +020064
Wenyou Yangeced5a72016-02-03 10:16:49 +080065 at91_periph_clk_enable(ATMEL_ID_SPI);
Jean-Christophe PLAGNIOL-VILLARD1699da62009-05-13 21:01:13 +020066
67 if (cs_mask & (1 << 0)) {
Jens Scharsig7f9e8632010-02-03 22:46:46 +010068 at91_set_a_periph(AT91_PIO_PORTA, 28, 1);
Jean-Christophe PLAGNIOL-VILLARD1699da62009-05-13 21:01:13 +020069 }
70 if (cs_mask & (1 << 1)) {
Jens Scharsig7f9e8632010-02-03 22:46:46 +010071 at91_set_b_periph(AT91_PIO_PORTB, 7, 1);
Jean-Christophe PLAGNIOL-VILLARD1699da62009-05-13 21:01:13 +020072 }
73 if (cs_mask & (1 << 2)) {
Jens Scharsig7f9e8632010-02-03 22:46:46 +010074 at91_set_a_periph(AT91_PIO_PORTD, 8, 1);
Jean-Christophe PLAGNIOL-VILLARD1699da62009-05-13 21:01:13 +020075 }
76 if (cs_mask & (1 << 3)) {
Jens Scharsig7f9e8632010-02-03 22:46:46 +010077 at91_set_b_periph(AT91_PIO_PORTD, 9, 1);
Jean-Christophe PLAGNIOL-VILLARD1699da62009-05-13 21:01:13 +020078 }
79 if (cs_mask & (1 << 4)) {
Jens Scharsig7f9e8632010-02-03 22:46:46 +010080 at91_set_pio_output(AT91_PIO_PORTA, 28, 1);
Jean-Christophe PLAGNIOL-VILLARD1699da62009-05-13 21:01:13 +020081 }
82 if (cs_mask & (1 << 5)) {
Jens Scharsig7f9e8632010-02-03 22:46:46 +010083 at91_set_pio_output(AT91_PIO_PORTB, 7, 1);
Jean-Christophe PLAGNIOL-VILLARD1699da62009-05-13 21:01:13 +020084 }
85 if (cs_mask & (1 << 6)) {
Jens Scharsig7f9e8632010-02-03 22:46:46 +010086 at91_set_pio_output(AT91_PIO_PORTD, 8, 1);
Jean-Christophe PLAGNIOL-VILLARD1699da62009-05-13 21:01:13 +020087 }
88 if (cs_mask & (1 << 7)) {
Jens Scharsig7f9e8632010-02-03 22:46:46 +010089 at91_set_pio_output(AT91_PIO_PORTD, 9, 1);
Jean-Christophe PLAGNIOL-VILLARD1699da62009-05-13 21:01:13 +020090 }
91}
92#endif
Wu, Josh111ec4c2015-02-02 17:51:00 +080093
94#ifdef CONFIG_GENERIC_ATMEL_MCI
95void at91_mci_hw_init(void)
96{
Wu, Josh111ec4c2015-02-02 17:51:00 +080097 at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* MCI CLK */
98 at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* MCI CDA */
99 at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* MCI DA0 */
100 at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* MCI DA1 */
101 at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* MCI DA2 */
102 at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* MCI DA3 */
103
Wenyou Yangeced5a72016-02-03 10:16:49 +0800104 at91_periph_clk_enable(ATMEL_ID_MCI);
Wu, Josh111ec4c2015-02-02 17:51:00 +0800105}
106#endif