blob: 1f77adf4c22a3001004edf70bbb3fa32b2cd6f6f [file] [log] [blame]
TsiChung Liew8e585f02007-06-18 13:50:13 -05001/*
2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Alison Wangaa0d99f2012-03-26 21:49:05 +00005 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
TsiChung Liew8e585f02007-06-18 13:50:13 -05006 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
TsiChung Liew8e585f02007-06-18 13:50:13 -05009 */
10
TsiChung Liew8e585f02007-06-18 13:50:13 -050011#include <config.h>
TsiChungLiew427c8142007-07-05 22:54:42 -050012#include <common.h>
13#include <asm/immap.h>
Alison Wangaa0d99f2012-03-26 21:49:05 +000014#include <asm/io.h>
TsiChung Liew8e585f02007-06-18 13:50:13 -050015
16DECLARE_GLOBAL_DATA_PTR;
17
18int checkboard(void)
19{
20 puts("Board: ");
21 puts("Freescale FireEngine 5329 EVB\n");
22 return 0;
23};
24
Becky Bruce9973e3c2008-06-09 16:03:40 -050025phys_size_t initdram(int board_type)
TsiChung Liew8e585f02007-06-18 13:50:13 -050026{
Alison Wangaa0d99f2012-03-26 21:49:05 +000027 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
TsiChung Liew8e585f02007-06-18 13:50:13 -050028 u32 dramsize, i;
29
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020030 dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
TsiChung Liew8e585f02007-06-18 13:50:13 -050031
32 for (i = 0x13; i < 0x20; i++) {
33 if (dramsize == (1 << i))
34 break;
35 }
36 i--;
37
Alison Wangaa0d99f2012-03-26 21:49:05 +000038 out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
39 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
40 out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
TsiChung Liew8e585f02007-06-18 13:50:13 -050041
42 /* Issue PALL */
Alison Wangaa0d99f2012-03-26 21:49:05 +000043 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
TsiChung Liew8e585f02007-06-18 13:50:13 -050044
45 /* Issue LEMR */
Alison Wangaa0d99f2012-03-26 21:49:05 +000046 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
47 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
TsiChung Liew8e585f02007-06-18 13:50:13 -050048
49 udelay(500);
50
51 /* Issue PALL */
Alison Wangaa0d99f2012-03-26 21:49:05 +000052 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
TsiChung Liew8e585f02007-06-18 13:50:13 -050053
54 /* Perform two refresh cycles */
Alison Wangaa0d99f2012-03-26 21:49:05 +000055 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
56 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
TsiChung Liew8e585f02007-06-18 13:50:13 -050057
Alison Wangaa0d99f2012-03-26 21:49:05 +000058 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
TsiChung Liew8e585f02007-06-18 13:50:13 -050059
Alison Wangaa0d99f2012-03-26 21:49:05 +000060 out_be32(&sdram->ctrl,
61 (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
TsiChung Liew8e585f02007-06-18 13:50:13 -050062
63 udelay(100);
64
65 return dramsize;
66};
67
68int testdram(void)
69{
70 /* TODO: XXX XXX XXX */
71 printf("DRAM test not implemented!\n");
72
73 return (0);
74}