| Simon Glass | e1ae0d1 | 2012-10-17 13:24:49 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Tegra pulse width frequency modulator definitions |
| 3 | * |
| 4 | * Copyright (c) 2011 The Chromium OS Authors. |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #ifndef __ASM_ARCH_TEGRA_PWM_H |
| 25 | #define __ASM_ARCH_TEGRA_PWM_H |
| 26 | |
| 27 | /* This is a single PWM channel */ |
| 28 | struct pwm_ctlr { |
| 29 | uint control; /* Control register */ |
| 30 | uint reserved[3]; /* Space space */ |
| 31 | }; |
| 32 | |
| 33 | #define PWM_NUM_CHANNELS 4 |
| 34 | |
| 35 | /* PWM_CONTROLLER_PWM_CSR_0/1/2/3_0 */ |
| 36 | #define PWM_ENABLE_SHIFT 31 |
| 37 | #define PWM_ENABLE_MASK (0x1 << PWM_ENABLE_SHIFT) |
| 38 | |
| 39 | #define PWM_WIDTH_SHIFT 16 |
| 40 | #define PWM_WIDTH_MASK (0x7FFF << PWM_WIDTH_SHIFT) |
| 41 | |
| 42 | #define PWM_DIVIDER_SHIFT 0 |
| 43 | #define PWM_DIVIDER_MASK (0x1FFF << PWM_DIVIDER_SHIFT) |
| 44 | |
| 45 | /** |
| 46 | * Program the PWM with the given parameters. |
| 47 | * |
| 48 | * @param channel PWM channel to update |
| 49 | * @param rate Clock rate to use for PWM |
| 50 | * @param pulse_width high pulse width: 0=always low, 1=1/256 pulse high, |
| 51 | * n = n/256 pulse high |
| 52 | * @param freq_divider frequency divider value (1 to use rate as is) |
| 53 | */ |
| 54 | void pwm_enable(unsigned channel, int rate, int pulse_width, int freq_divider); |
| 55 | |
| 56 | /** |
| 57 | * Request a pwm channel as referenced by a device tree node. |
| 58 | * |
| 59 | * This channel can then be passed to pwm_enable(). |
| 60 | * |
| 61 | * @param blob Device tree blob |
| 62 | * @param node Node containing reference to pwm |
| 63 | * @param prop_name Property name of pwm reference |
| 64 | * @return channel number, if ok, else -1 |
| 65 | */ |
| 66 | int pwm_request(const void *blob, int node, const char *prop_name); |
| 67 | |
| 68 | /** |
| 69 | * Set up the pwm controller, by looking it up in the fdt. |
| 70 | * |
| 71 | * @return 0 if ok, -1 if the device tree node was not found or invalid. |
| 72 | */ |
| 73 | int pwm_init(const void *blob); |
| 74 | |
| 75 | #endif /* __ASM_ARCH_TEGRA_PWM_H */ |