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Siva Durga Prasad Paladugu128ec1f2016-11-15 16:15:41 +05301/*
2 * ZynqMP clock driver
3 *
4 * Copyright (C) 2016 Xilinx, Inc.
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#include <common.h>
10#include <linux/bitops.h>
11#include <clk-uclass.h>
Siva Durga Prasad Paladugu128ec1f2016-11-15 16:15:41 +053012#include <clk.h>
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +053013#include <asm/arch/sys_proto.h>
Simon Glass9d922452017-05-17 17:18:03 -060014#include <dm.h>
Siva Durga Prasad Paladugu128ec1f2016-11-15 16:15:41 +053015
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +053016DECLARE_GLOBAL_DATA_PTR;
Siva Durga Prasad Paladugu128ec1f2016-11-15 16:15:41 +053017
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +053018static const resource_size_t zynqmp_crf_apb_clkc_base = 0xfd1a0020;
19static const resource_size_t zynqmp_crl_apb_clkc_base = 0xff5e0020;
Siva Durga Prasad Paladugu128ec1f2016-11-15 16:15:41 +053020
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +053021/* Full power domain clocks */
22#define CRF_APB_APLL_CTRL (zynqmp_crf_apb_clkc_base + 0x00)
23#define CRF_APB_DPLL_CTRL (zynqmp_crf_apb_clkc_base + 0x0c)
24#define CRF_APB_VPLL_CTRL (zynqmp_crf_apb_clkc_base + 0x18)
25#define CRF_APB_PLL_STATUS (zynqmp_crf_apb_clkc_base + 0x24)
26#define CRF_APB_APLL_TO_LPD_CTRL (zynqmp_crf_apb_clkc_base + 0x28)
27#define CRF_APB_DPLL_TO_LPD_CTRL (zynqmp_crf_apb_clkc_base + 0x2c)
28#define CRF_APB_VPLL_TO_LPD_CTRL (zynqmp_crf_apb_clkc_base + 0x30)
29/* Peripheral clocks */
30#define CRF_APB_ACPU_CTRL (zynqmp_crf_apb_clkc_base + 0x40)
31#define CRF_APB_DBG_TRACE_CTRL (zynqmp_crf_apb_clkc_base + 0x44)
32#define CRF_APB_DBG_FPD_CTRL (zynqmp_crf_apb_clkc_base + 0x48)
33#define CRF_APB_DP_VIDEO_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x50)
34#define CRF_APB_DP_AUDIO_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x54)
35#define CRF_APB_DP_STC_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x5c)
36#define CRF_APB_DDR_CTRL (zynqmp_crf_apb_clkc_base + 0x60)
37#define CRF_APB_GPU_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x64)
38#define CRF_APB_SATA_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x80)
39#define CRF_APB_PCIE_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x94)
40#define CRF_APB_GDMA_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x98)
41#define CRF_APB_DPDMA_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x9c)
42#define CRF_APB_TOPSW_MAIN_CTRL (zynqmp_crf_apb_clkc_base + 0xa0)
43#define CRF_APB_TOPSW_LSBUS_CTRL (zynqmp_crf_apb_clkc_base + 0xa4)
44#define CRF_APB_GTGREF0_REF_CTRL (zynqmp_crf_apb_clkc_base + 0xa8)
45#define CRF_APB_DBG_TSTMP_CTRL (zynqmp_crf_apb_clkc_base + 0xd8)
46
47/* Low power domain clocks */
48#define CRL_APB_IOPLL_CTRL (zynqmp_crl_apb_clkc_base + 0x00)
49#define CRL_APB_RPLL_CTRL (zynqmp_crl_apb_clkc_base + 0x10)
50#define CRL_APB_PLL_STATUS (zynqmp_crl_apb_clkc_base + 0x20)
51#define CRL_APB_IOPLL_TO_FPD_CTRL (zynqmp_crl_apb_clkc_base + 0x24)
52#define CRL_APB_RPLL_TO_FPD_CTRL (zynqmp_crl_apb_clkc_base + 0x28)
53/* Peripheral clocks */
54#define CRL_APB_USB3_DUAL_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x2c)
55#define CRL_APB_GEM0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x30)
56#define CRL_APB_GEM1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x34)
57#define CRL_APB_GEM2_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x38)
58#define CRL_APB_GEM3_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x3c)
59#define CRL_APB_USB0_BUS_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x40)
60#define CRL_APB_USB1_BUS_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x44)
61#define CRL_APB_QSPI_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x48)
62#define CRL_APB_SDIO0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x4c)
63#define CRL_APB_SDIO1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x50)
64#define CRL_APB_UART0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x54)
65#define CRL_APB_UART1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x58)
66#define CRL_APB_SPI0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x5c)
67#define CRL_APB_SPI1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x60)
68#define CRL_APB_CAN0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x64)
69#define CRL_APB_CAN1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x68)
70#define CRL_APB_CPU_R5_CTRL (zynqmp_crl_apb_clkc_base + 0x70)
71#define CRL_APB_IOU_SWITCH_CTRL (zynqmp_crl_apb_clkc_base + 0x7c)
72#define CRL_APB_CSU_PLL_CTRL (zynqmp_crl_apb_clkc_base + 0x80)
73#define CRL_APB_PCAP_CTRL (zynqmp_crl_apb_clkc_base + 0x84)
74#define CRL_APB_LPD_SWITCH_CTRL (zynqmp_crl_apb_clkc_base + 0x88)
75#define CRL_APB_LPD_LSBUS_CTRL (zynqmp_crl_apb_clkc_base + 0x8c)
76#define CRL_APB_DBG_LPD_CTRL (zynqmp_crl_apb_clkc_base + 0x90)
77#define CRL_APB_NAND_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x94)
78#define CRL_APB_ADMA_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x98)
79#define CRL_APB_PL0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xa0)
80#define CRL_APB_PL1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xa4)
81#define CRL_APB_PL2_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xa8)
82#define CRL_APB_PL3_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xac)
83#define CRL_APB_PL0_THR_CNT (zynqmp_crl_apb_clkc_base + 0xb4)
84#define CRL_APB_PL1_THR_CNT (zynqmp_crl_apb_clkc_base + 0xbc)
85#define CRL_APB_PL2_THR_CNT (zynqmp_crl_apb_clkc_base + 0xc4)
86#define CRL_APB_PL3_THR_CNT (zynqmp_crl_apb_clkc_base + 0xdc)
87#define CRL_APB_GEM_TSU_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xe0)
88#define CRL_APB_DLL_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xe4)
89#define CRL_APB_AMS_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xe8)
90#define CRL_APB_I2C0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x100)
91#define CRL_APB_I2C1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x104)
92#define CRL_APB_TIMESTAMP_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x108)
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +053093
94#define ZYNQ_CLK_MAXDIV 0x3f
95#define CLK_CTRL_DIV1_SHIFT 16
96#define CLK_CTRL_DIV1_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT)
97#define CLK_CTRL_DIV0_SHIFT 8
98#define CLK_CTRL_DIV0_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT)
99#define CLK_CTRL_SRCSEL_SHIFT 0
100#define CLK_CTRL_SRCSEL_MASK (0x3 << CLK_CTRL_SRCSEL_SHIFT)
101#define PLLCTRL_FBDIV_MASK 0x7f00
102#define PLLCTRL_FBDIV_SHIFT 8
103#define PLLCTRL_RESET_MASK 1
104#define PLLCTRL_RESET_SHIFT 0
105#define PLLCTRL_BYPASS_MASK 0x8
106#define PLLCTRL_BYPASS_SHFT 3
107#define PLLCTRL_POST_SRC_SHFT 24
108#define PLLCTRL_POST_SRC_MASK (0x7 << PLLCTRL_POST_SRC_SHFT)
109
110
111#define NUM_MIO_PINS 77
112
113enum zynqmp_clk {
114 iopll, rpll,
115 apll, dpll, vpll,
116 iopll_to_fpd, rpll_to_fpd, apll_to_lpd, dpll_to_lpd, vpll_to_lpd,
117 acpu, acpu_half,
118 dbg_fpd, dbg_lpd, dbg_trace, dbg_tstmp,
119 dp_video_ref, dp_audio_ref,
120 dp_stc_ref, gdma_ref, dpdma_ref,
121 ddr_ref, sata_ref, pcie_ref,
122 gpu_ref, gpu_pp0_ref, gpu_pp1_ref,
123 topsw_main, topsw_lsbus,
124 gtgref0_ref,
125 lpd_switch, lpd_lsbus,
126 usb0_bus_ref, usb1_bus_ref, usb3_dual_ref, usb0, usb1,
127 cpu_r5, cpu_r5_core,
128 csu_spb, csu_pll, pcap,
129 iou_switch,
130 gem_tsu_ref, gem_tsu,
131 gem0_ref, gem1_ref, gem2_ref, gem3_ref,
132 gem0_rx, gem1_rx, gem2_rx, gem3_rx,
133 qspi_ref,
134 sdio0_ref, sdio1_ref,
135 uart0_ref, uart1_ref,
136 spi0_ref, spi1_ref,
137 nand_ref,
138 i2c0_ref, i2c1_ref, can0_ref, can1_ref, can0, can1,
139 dll_ref,
140 adma_ref,
141 timestamp_ref,
142 ams_ref,
143 pl0, pl1, pl2, pl3,
144 wdt,
145 clk_max,
146};
147
148static const char * const clk_names[clk_max] = {
149 "iopll", "rpll", "apll", "dpll",
150 "vpll", "iopll_to_fpd", "rpll_to_fpd",
151 "apll_to_lpd", "dpll_to_lpd", "vpll_to_lpd",
152 "acpu", "acpu_half", "dbf_fpd", "dbf_lpd",
153 "dbg_trace", "dbg_tstmp", "dp_video_ref",
154 "dp_audio_ref", "dp_stc_ref", "gdma_ref",
155 "dpdma_ref", "ddr_ref", "sata_ref", "pcie_ref",
156 "gpu_ref", "gpu_pp0_ref", "gpu_pp1_ref",
157 "topsw_main", "topsw_lsbus", "gtgref0_ref",
158 "lpd_switch", "lpd_lsbus", "usb0_bus_ref",
159 "usb1_bus_ref", "usb3_dual_ref", "usb0",
160 "usb1", "cpu_r5", "cpu_r5_core", "csu_spb",
161 "csu_pll", "pcap", "iou_switch", "gem_tsu_ref",
162 "gem_tsu", "gem0_ref", "gem1_ref", "gem2_ref",
163 "gem3_ref", "gem0_tx", "gem1_tx", "gem2_tx",
164 "gem3_tx", "qspi_ref", "sdio0_ref", "sdio1_ref",
165 "uart0_ref", "uart1_ref", "spi0_ref",
166 "spi1_ref", "nand_ref", "i2c0_ref", "i2c1_ref",
167 "can0_ref", "can1_ref", "can0", "can1",
168 "dll_ref", "adma_ref", "timestamp_ref",
169 "ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt"
170};
171
172struct zynqmp_clk_priv {
173 unsigned long ps_clk_freq;
174 unsigned long video_clk;
175 unsigned long pss_alt_ref_clk;
176 unsigned long gt_crx_ref_clk;
177 unsigned long aux_ref_clk;
178};
179
180static u32 zynqmp_clk_get_register(enum zynqmp_clk id)
Siva Durga Prasad Paladugu128ec1f2016-11-15 16:15:41 +0530181{
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530182 switch (id) {
183 case iopll:
184 return CRL_APB_IOPLL_CTRL;
185 case rpll:
186 return CRL_APB_RPLL_CTRL;
187 case apll:
188 return CRF_APB_APLL_CTRL;
189 case dpll:
190 return CRF_APB_DPLL_CTRL;
191 case vpll:
192 return CRF_APB_VPLL_CTRL;
193 case acpu:
194 return CRF_APB_ACPU_CTRL;
195 case ddr_ref:
196 return CRF_APB_DDR_CTRL;
197 case qspi_ref:
198 return CRL_APB_QSPI_REF_CTRL;
199 case gem0_ref:
200 return CRL_APB_GEM0_REF_CTRL;
201 case gem1_ref:
202 return CRL_APB_GEM1_REF_CTRL;
203 case gem2_ref:
204 return CRL_APB_GEM2_REF_CTRL;
205 case gem3_ref:
206 return CRL_APB_GEM3_REF_CTRL;
207 case uart0_ref:
208 return CRL_APB_UART0_REF_CTRL;
209 case uart1_ref:
210 return CRL_APB_UART1_REF_CTRL;
211 case sdio0_ref:
212 return CRL_APB_SDIO0_REF_CTRL;
213 case sdio1_ref:
214 return CRL_APB_SDIO1_REF_CTRL;
215 case spi0_ref:
216 return CRL_APB_SPI0_REF_CTRL;
217 case spi1_ref:
218 return CRL_APB_SPI1_REF_CTRL;
219 case nand_ref:
220 return CRL_APB_NAND_REF_CTRL;
221 case i2c0_ref:
222 return CRL_APB_I2C0_REF_CTRL;
223 case i2c1_ref:
224 return CRL_APB_I2C1_REF_CTRL;
225 case can0_ref:
226 return CRL_APB_CAN0_REF_CTRL;
227 case can1_ref:
228 return CRL_APB_CAN1_REF_CTRL;
Vipul Kumara79b5902018-03-07 14:52:44 +0530229 case pl0:
230 return CRL_APB_PL0_REF_CTRL;
231 case pl1:
232 return CRL_APB_PL1_REF_CTRL;
233 case pl2:
234 return CRL_APB_PL2_REF_CTRL;
235 case pl3:
236 return CRL_APB_PL3_REF_CTRL;
237 case wdt:
238 return CRF_APB_TOPSW_LSBUS_CTRL;
239 case iopll_to_fpd:
240 return CRL_APB_IOPLL_TO_FPD_CTRL;
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530241 default:
242 debug("Invalid clk id%d\n", id);
243 }
244 return 0;
245}
Siva Durga Prasad Paladugu128ec1f2016-11-15 16:15:41 +0530246
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530247static enum zynqmp_clk zynqmp_clk_get_cpu_pll(u32 clk_ctrl)
248{
249 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
250 CLK_CTRL_SRCSEL_SHIFT;
Siva Durga Prasad Paladugu128ec1f2016-11-15 16:15:41 +0530251
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530252 switch (srcsel) {
253 case 2:
254 return dpll;
255 case 3:
256 return vpll;
257 case 0 ... 1:
258 default:
259 return apll;
260 }
261}
262
263static enum zynqmp_clk zynqmp_clk_get_ddr_pll(u32 clk_ctrl)
264{
265 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
266 CLK_CTRL_SRCSEL_SHIFT;
267
268 switch (srcsel) {
269 case 1:
270 return vpll;
271 case 0:
272 default:
273 return dpll;
274 }
275}
276
277static enum zynqmp_clk zynqmp_clk_get_peripheral_pll(u32 clk_ctrl)
278{
279 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
280 CLK_CTRL_SRCSEL_SHIFT;
281
282 switch (srcsel) {
283 case 2:
284 return rpll;
285 case 3:
286 return dpll;
287 case 0 ... 1:
288 default:
289 return iopll;
290 }
291}
292
Vipul Kumara79b5902018-03-07 14:52:44 +0530293static enum zynqmp_clk zynqmp_clk_get_wdt_pll(u32 clk_ctrl)
294{
295 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
296 CLK_CTRL_SRCSEL_SHIFT;
297
298 switch (srcsel) {
299 case 2:
300 return iopll_to_fpd;
301 case 3:
302 return dpll;
303 case 0 ... 1:
304 default:
305 return apll;
306 }
307}
308
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530309static ulong zynqmp_clk_get_pll_src(ulong clk_ctrl,
310 struct zynqmp_clk_priv *priv,
311 bool is_pre_src)
312{
313 u32 src_sel;
314
315 if (is_pre_src)
316 src_sel = (clk_ctrl & PLLCTRL_POST_SRC_MASK) >>
317 PLLCTRL_POST_SRC_SHFT;
318 else
319 src_sel = (clk_ctrl & PLLCTRL_POST_SRC_MASK) >>
320 PLLCTRL_POST_SRC_SHFT;
321
322 switch (src_sel) {
323 case 4:
324 return priv->video_clk;
325 case 5:
326 return priv->pss_alt_ref_clk;
327 case 6:
328 return priv->aux_ref_clk;
329 case 7:
330 return priv->gt_crx_ref_clk;
331 case 0 ... 3:
332 default:
333 return priv->ps_clk_freq;
334 }
335}
336
337static ulong zynqmp_clk_get_pll_rate(struct zynqmp_clk_priv *priv,
338 enum zynqmp_clk id)
339{
340 u32 clk_ctrl, reset, mul;
341 ulong freq;
342 int ret;
343
344 ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);
Siva Durga Prasad Paladugu154799a2017-04-13 16:59:38 +0530345 if (ret) {
346 printf("%s mio read fail\n", __func__);
347 return -EIO;
348 }
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530349
350 if (clk_ctrl & PLLCTRL_BYPASS_MASK)
351 freq = zynqmp_clk_get_pll_src(clk_ctrl, priv, 0);
352 else
353 freq = zynqmp_clk_get_pll_src(clk_ctrl, priv, 1);
354
355 reset = (clk_ctrl & PLLCTRL_RESET_MASK) >> PLLCTRL_RESET_SHIFT;
356 if (reset && !(clk_ctrl & PLLCTRL_BYPASS_MASK))
357 return 0;
358
359 mul = (clk_ctrl & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT;
360
361 freq *= mul;
362
363 if (clk_ctrl & (1 << 16))
364 freq /= 2;
365
366 return freq;
367}
368
369static ulong zynqmp_clk_get_cpu_rate(struct zynqmp_clk_priv *priv,
370 enum zynqmp_clk id)
371{
372 u32 clk_ctrl, div;
373 enum zynqmp_clk pll;
374 int ret;
Siva Durga Prasad Paladugu154799a2017-04-13 16:59:38 +0530375 unsigned long pllrate;
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530376
377 ret = zynqmp_mmio_read(CRF_APB_ACPU_CTRL, &clk_ctrl);
Siva Durga Prasad Paladugu154799a2017-04-13 16:59:38 +0530378 if (ret) {
379 printf("%s mio read fail\n", __func__);
380 return -EIO;
381 }
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530382
383 div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
384
385 pll = zynqmp_clk_get_cpu_pll(clk_ctrl);
Siva Durga Prasad Paladugu154799a2017-04-13 16:59:38 +0530386 pllrate = zynqmp_clk_get_pll_rate(priv, pll);
387 if (IS_ERR_VALUE(pllrate))
388 return pllrate;
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530389
Siva Durga Prasad Paladugu154799a2017-04-13 16:59:38 +0530390 return DIV_ROUND_CLOSEST(pllrate, div);
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530391}
392
393static ulong zynqmp_clk_get_ddr_rate(struct zynqmp_clk_priv *priv)
394{
395 u32 clk_ctrl, div;
396 enum zynqmp_clk pll;
397 int ret;
Siva Durga Prasad Paladugu154799a2017-04-13 16:59:38 +0530398 ulong pllrate;
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530399
400 ret = zynqmp_mmio_read(CRF_APB_DDR_CTRL, &clk_ctrl);
Siva Durga Prasad Paladugu154799a2017-04-13 16:59:38 +0530401 if (ret) {
402 printf("%s mio read fail\n", __func__);
403 return -EIO;
404 }
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530405
406 div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
407
408 pll = zynqmp_clk_get_ddr_pll(clk_ctrl);
Siva Durga Prasad Paladugu154799a2017-04-13 16:59:38 +0530409 pllrate = zynqmp_clk_get_pll_rate(priv, pll);
410 if (IS_ERR_VALUE(pllrate))
411 return pllrate;
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530412
Siva Durga Prasad Paladugu154799a2017-04-13 16:59:38 +0530413 return DIV_ROUND_CLOSEST(pllrate, div);
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530414}
415
416static ulong zynqmp_clk_get_peripheral_rate(struct zynqmp_clk_priv *priv,
417 enum zynqmp_clk id, bool two_divs)
418{
419 enum zynqmp_clk pll;
420 u32 clk_ctrl, div0;
421 u32 div1 = 1;
422 int ret;
Siva Durga Prasad Paladugu154799a2017-04-13 16:59:38 +0530423 ulong pllrate;
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530424
425 ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);
Siva Durga Prasad Paladugu154799a2017-04-13 16:59:38 +0530426 if (ret) {
427 printf("%s mio read fail\n", __func__);
428 return -EIO;
429 }
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530430
431 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
432 if (!div0)
433 div0 = 1;
434
435 if (two_divs) {
436 div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
437 if (!div1)
438 div1 = 1;
439 }
440
441 pll = zynqmp_clk_get_peripheral_pll(clk_ctrl);
Siva Durga Prasad Paladugu154799a2017-04-13 16:59:38 +0530442 pllrate = zynqmp_clk_get_pll_rate(priv, pll);
443 if (IS_ERR_VALUE(pllrate))
444 return pllrate;
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530445
446 return
447 DIV_ROUND_CLOSEST(
Siva Durga Prasad Paladugu154799a2017-04-13 16:59:38 +0530448 DIV_ROUND_CLOSEST(pllrate, div0), div1);
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530449}
450
Vipul Kumara79b5902018-03-07 14:52:44 +0530451static ulong zynqmp_clk_get_wdt_rate(struct zynqmp_clk_priv *priv,
452 enum zynqmp_clk id, bool two_divs)
453{
454 enum zynqmp_clk pll;
455 u32 clk_ctrl, div0;
456 u32 div1 = 1;
457 int ret;
458 ulong pllrate;
459
460 ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);
461 if (ret) {
462 printf("%d %s mio read fail\n", __LINE__, __func__);
463 return -EIO;
464 }
465
466 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
467 if (!div0)
468 div0 = 1;
469
470 pll = zynqmp_clk_get_wdt_pll(clk_ctrl);
471 if (two_divs) {
472 ret = zynqmp_mmio_read(zynqmp_clk_get_register(pll), &clk_ctrl);
473 if (ret) {
474 printf("%d %s mio read fail\n", __LINE__, __func__);
475 return -EIO;
476 }
477 div1 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
478 if (!div1)
479 div1 = 1;
480 }
481
482 if (pll == iopll_to_fpd)
483 pll = iopll;
484
485 pllrate = zynqmp_clk_get_pll_rate(priv, pll);
486 if (IS_ERR_VALUE(pllrate))
487 return pllrate;
488
489 return
490 DIV_ROUND_CLOSEST(
491 DIV_ROUND_CLOSEST(pllrate, div0), div1);
492}
493
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530494static unsigned long zynqmp_clk_calc_peripheral_two_divs(ulong rate,
495 ulong pll_rate,
496 u32 *div0, u32 *div1)
497{
498 long new_err, best_err = (long)(~0UL >> 1);
499 ulong new_rate, best_rate = 0;
500 u32 d0, d1;
501
502 for (d0 = 1; d0 <= ZYNQ_CLK_MAXDIV; d0++) {
503 for (d1 = 1; d1 <= ZYNQ_CLK_MAXDIV >> 1; d1++) {
504 new_rate = DIV_ROUND_CLOSEST(
505 DIV_ROUND_CLOSEST(pll_rate, d0), d1);
506 new_err = abs(new_rate - rate);
507
508 if (new_err < best_err) {
509 *div0 = d0;
510 *div1 = d1;
511 best_err = new_err;
512 best_rate = new_rate;
513 }
Siva Durga Prasad Paladugu128ec1f2016-11-15 16:15:41 +0530514 }
515 }
516
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530517 return best_rate;
Siva Durga Prasad Paladugu128ec1f2016-11-15 16:15:41 +0530518}
519
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530520static ulong zynqmp_clk_set_peripheral_rate(struct zynqmp_clk_priv *priv,
521 enum zynqmp_clk id, ulong rate,
522 bool two_divs)
Siva Durga Prasad Paladugu128ec1f2016-11-15 16:15:41 +0530523{
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530524 enum zynqmp_clk pll;
525 u32 clk_ctrl, div0 = 0, div1 = 0;
526 ulong pll_rate, new_rate;
527 u32 reg;
528 int ret;
529 u32 mask;
530
531 reg = zynqmp_clk_get_register(id);
532 ret = zynqmp_mmio_read(reg, &clk_ctrl);
Siva Durga Prasad Paladugu154799a2017-04-13 16:59:38 +0530533 if (ret) {
534 printf("%s mio read fail\n", __func__);
535 return -EIO;
536 }
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530537
538 pll = zynqmp_clk_get_peripheral_pll(clk_ctrl);
539 pll_rate = zynqmp_clk_get_pll_rate(priv, pll);
Siva Durga Prasad Paladugu154799a2017-04-13 16:59:38 +0530540 if (IS_ERR_VALUE(pll_rate))
541 return pll_rate;
542
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530543 clk_ctrl &= ~CLK_CTRL_DIV0_MASK;
544 if (two_divs) {
545 clk_ctrl &= ~CLK_CTRL_DIV1_MASK;
546 new_rate = zynqmp_clk_calc_peripheral_two_divs(rate, pll_rate,
547 &div0, &div1);
548 clk_ctrl |= div1 << CLK_CTRL_DIV1_SHIFT;
549 } else {
550 div0 = DIV_ROUND_CLOSEST(pll_rate, rate);
551 if (div0 > ZYNQ_CLK_MAXDIV)
552 div0 = ZYNQ_CLK_MAXDIV;
553 new_rate = DIV_ROUND_CLOSEST(rate, div0);
554 }
555 clk_ctrl |= div0 << CLK_CTRL_DIV0_SHIFT;
556
557 mask = (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT) |
558 (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT);
559
560 ret = zynqmp_mmio_write(reg, mask, clk_ctrl);
Siva Durga Prasad Paladugu154799a2017-04-13 16:59:38 +0530561 if (ret) {
562 printf("%s mio write fail\n", __func__);
563 return -EIO;
564 }
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530565
566 return new_rate;
567}
568
569static ulong zynqmp_clk_get_rate(struct clk *clk)
570{
571 struct zynqmp_clk_priv *priv = dev_get_priv(clk->dev);
572 enum zynqmp_clk id = clk->id;
573 bool two_divs = false;
Siva Durga Prasad Paladugu128ec1f2016-11-15 16:15:41 +0530574
575 switch (id) {
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530576 case iopll ... vpll:
577 return zynqmp_clk_get_pll_rate(priv, id);
578 case acpu:
579 return zynqmp_clk_get_cpu_rate(priv, id);
580 case ddr_ref:
581 return zynqmp_clk_get_ddr_rate(priv);
582 case gem0_ref ... gem3_ref:
583 case qspi_ref ... can1_ref:
Vipul Kumara79b5902018-03-07 14:52:44 +0530584 case pl0 ... pl3:
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530585 two_divs = true;
586 return zynqmp_clk_get_peripheral_rate(priv, id, two_divs);
Vipul Kumara79b5902018-03-07 14:52:44 +0530587 case wdt:
588 two_divs = true;
589 return zynqmp_clk_get_wdt_rate(priv, id, two_divs);
Siva Durga Prasad Paladugu128ec1f2016-11-15 16:15:41 +0530590 default:
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530591 return -ENXIO;
Siva Durga Prasad Paladugu128ec1f2016-11-15 16:15:41 +0530592 }
Siva Durga Prasad Paladugu128ec1f2016-11-15 16:15:41 +0530593}
594
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530595static ulong zynqmp_clk_set_rate(struct clk *clk, ulong rate)
Siva Durga Prasad Paladugu128ec1f2016-11-15 16:15:41 +0530596{
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530597 struct zynqmp_clk_priv *priv = dev_get_priv(clk->dev);
598 enum zynqmp_clk id = clk->id;
599 bool two_divs = true;
Siva Durga Prasad Paladugu128ec1f2016-11-15 16:15:41 +0530600
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530601 switch (id) {
602 case gem0_ref ... gem3_ref:
603 case qspi_ref ... can1_ref:
604 return zynqmp_clk_set_peripheral_rate(priv, id,
605 rate, two_divs);
Siva Durga Prasad Paladugu128ec1f2016-11-15 16:15:41 +0530606 default:
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530607 return -ENXIO;
Siva Durga Prasad Paladugu128ec1f2016-11-15 16:15:41 +0530608 }
Siva Durga Prasad Paladugu128ec1f2016-11-15 16:15:41 +0530609}
610
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530611int soc_clk_dump(void)
Siva Durga Prasad Paladugu128ec1f2016-11-15 16:15:41 +0530612{
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530613 struct udevice *dev;
614 int i, ret;
Siva Durga Prasad Paladugu128ec1f2016-11-15 16:15:41 +0530615
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530616 ret = uclass_get_device_by_driver(UCLASS_CLK,
617 DM_GET_DRIVER(zynqmp_clk), &dev);
618 if (ret)
619 return ret;
Siva Durga Prasad Paladugu128ec1f2016-11-15 16:15:41 +0530620
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530621 printf("clk\t\tfrequency\n");
622 for (i = 0; i < clk_max; i++) {
623 const char *name = clk_names[i];
624 if (name) {
625 struct clk clk;
626 unsigned long rate;
Siva Durga Prasad Paladugu128ec1f2016-11-15 16:15:41 +0530627
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530628 clk.id = i;
629 ret = clk_request(dev, &clk);
630 if (ret < 0)
631 return ret;
Siva Durga Prasad Paladugu128ec1f2016-11-15 16:15:41 +0530632
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530633 rate = clk_get_rate(&clk);
Siva Durga Prasad Paladugu128ec1f2016-11-15 16:15:41 +0530634
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530635 clk_free(&clk);
636
637 if ((rate == (unsigned long)-ENOSYS) ||
Siva Durga Prasad Paladugu154799a2017-04-13 16:59:38 +0530638 (rate == (unsigned long)-ENXIO) ||
639 (rate == (unsigned long)-EIO))
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530640 printf("%10s%20s\n", name, "unknown");
641 else
642 printf("%10s%20lu\n", name, rate);
643 }
Siva Durga Prasad Paladugu128ec1f2016-11-15 16:15:41 +0530644 }
645
646 return 0;
647}
648
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530649static int zynqmp_get_freq_by_name(char *name, struct udevice *dev, ulong *freq)
Siva Durga Prasad Paladugu128ec1f2016-11-15 16:15:41 +0530650{
651 struct clk clk;
652 int ret;
653
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530654 ret = clk_get_by_name(dev, name, &clk);
Siva Durga Prasad Paladugu128ec1f2016-11-15 16:15:41 +0530655 if (ret < 0) {
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530656 dev_err(dev, "failed to get %s\n", name);
Siva Durga Prasad Paladugu128ec1f2016-11-15 16:15:41 +0530657 return ret;
658 }
659
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530660 *freq = clk_get_rate(&clk);
661 if (IS_ERR_VALUE(*freq)) {
662 dev_err(dev, "failed to get rate %s\n", name);
Siva Durga Prasad Paladugu128ec1f2016-11-15 16:15:41 +0530663 return -EINVAL;
664 }
665
666 return 0;
667}
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530668static int zynqmp_clk_probe(struct udevice *dev)
669{
670 int ret;
671 struct zynqmp_clk_priv *priv = dev_get_priv(dev);
672
673 debug("%s\n", __func__);
674 ret = zynqmp_get_freq_by_name("pss_ref_clk", dev, &priv->ps_clk_freq);
675 if (ret < 0)
676 return -EINVAL;
677
678 ret = zynqmp_get_freq_by_name("video_clk", dev, &priv->video_clk);
679 if (ret < 0)
680 return -EINVAL;
681
682 ret = zynqmp_get_freq_by_name("pss_alt_ref_clk", dev,
683 &priv->pss_alt_ref_clk);
684 if (ret < 0)
685 return -EINVAL;
686
687 ret = zynqmp_get_freq_by_name("aux_ref_clk", dev, &priv->aux_ref_clk);
688 if (ret < 0)
689 return -EINVAL;
690
691 ret = zynqmp_get_freq_by_name("gt_crx_ref_clk", dev,
692 &priv->gt_crx_ref_clk);
693 if (ret < 0)
694 return -EINVAL;
695
696 return 0;
697}
Siva Durga Prasad Paladugu128ec1f2016-11-15 16:15:41 +0530698
699static struct clk_ops zynqmp_clk_ops = {
700 .set_rate = zynqmp_clk_set_rate,
701 .get_rate = zynqmp_clk_get_rate,
702};
703
704static const struct udevice_id zynqmp_clk_ids[] = {
Michal Simek969dd4c2018-02-21 13:59:21 +0100705 { .compatible = "xlnx,zynqmp-clk" },
Siva Durga Prasad Paladugu128ec1f2016-11-15 16:15:41 +0530706 { .compatible = "xlnx,zynqmp-clkc" },
707 { }
708};
709
710U_BOOT_DRIVER(zynqmp_clk) = {
711 .name = "zynqmp-clk",
712 .id = UCLASS_CLK,
713 .of_match = zynqmp_clk_ids,
714 .probe = zynqmp_clk_probe,
715 .ops = &zynqmp_clk_ops,
Siva Durga Prasad Paladuguad76f8c2017-02-03 23:56:49 +0530716 .priv_auto_alloc_size = sizeof(struct zynqmp_clk_priv),
Siva Durga Prasad Paladugu128ec1f2016-11-15 16:15:41 +0530717};