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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Dinh Nguyen2ac71882018-04-04 17:18:20 -05002/*
3 * Socfpga Reset Controller Driver
4 *
5 * Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
6 *
7 * based on
8 * Allwinner SoCs Reset Controller driver
9 *
10 * Copyright 2013 Maxime Ripard
11 *
12 * Maxime Ripard <maxime.ripard@free-electrons.com>
Dinh Nguyen2ac71882018-04-04 17:18:20 -050013 */
14
Dinh Nguyen2ac71882018-04-04 17:18:20 -050015#include <dm.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060016#include <log.h>
Simon Glass336d4612020-02-03 07:36:16 -070017#include <malloc.h>
Simon Goldschmidtef72ba02019-07-15 21:47:55 +020018#include <dm/lists.h>
Dinh Nguyen2ac71882018-04-04 17:18:20 -050019#include <dm/of_access.h>
Simon Glass7b51b572019-08-01 09:46:52 -060020#include <env.h>
Dinh Nguyen2ac71882018-04-04 17:18:20 -050021#include <reset-uclass.h>
Ley Foon Tan9e608212020-01-10 13:48:37 +080022#include <wait_bit.h>
Dinh Nguyen2ac71882018-04-04 17:18:20 -050023#include <linux/bitops.h>
24#include <linux/io.h>
25#include <linux/sizes.h>
26
27#define BANK_INCREMENT 4
28#define NR_BANKS 8
29
30struct socfpga_reset_data {
Simon Goldschmidt1ea97502019-03-01 20:12:30 +010031 void __iomem *modrst_base;
Dinh Nguyen2ac71882018-04-04 17:18:20 -050032};
33
Simon Goldschmidtede6e7b2019-03-01 20:12:32 +010034/*
35 * For compatibility with Kernels that don't support peripheral reset, this
36 * driver can keep the old behaviour of not asserting peripheral reset before
37 * starting the OS and deasserting all peripheral resets (enabling all
38 * peripherals).
39 *
40 * For that, the reset driver checks the environment variable
41 * "socfpga_legacy_reset_compat". If this variable is '1', perihperals are not
42 * reset again once taken out of reset and all peripherals in 'permodrst' are
43 * taken out of reset before booting into the OS.
44 * Note that this should be required for gen5 systems only that are running
45 * Linux kernels without proper peripheral reset support for all drivers used.
46 */
47static bool socfpga_reset_keep_enabled(void)
48{
49#if !defined(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(ENV_SUPPORT)
50 const char *env_str;
51 long val;
52
53 env_str = env_get("socfpga_legacy_reset_compat");
54 if (env_str) {
55 val = simple_strtol(env_str, NULL, 0);
56 if (val == 1)
57 return true;
58 }
59#endif
60
61 return false;
62}
63
Dinh Nguyen2ac71882018-04-04 17:18:20 -050064static int socfpga_reset_assert(struct reset_ctl *reset_ctl)
65{
66 struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev);
67 int id = reset_ctl->id;
68 int reg_width = sizeof(u32);
69 int bank = id / (reg_width * BITS_PER_BYTE);
70 int offset = id % (reg_width * BITS_PER_BYTE);
71
Simon Goldschmidt1ea97502019-03-01 20:12:30 +010072 setbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset));
Dinh Nguyen2ac71882018-04-04 17:18:20 -050073 return 0;
74}
75
76static int socfpga_reset_deassert(struct reset_ctl *reset_ctl)
77{
78 struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev);
79 int id = reset_ctl->id;
80 int reg_width = sizeof(u32);
81 int bank = id / (reg_width * BITS_PER_BYTE);
82 int offset = id % (reg_width * BITS_PER_BYTE);
83
Simon Goldschmidt1ea97502019-03-01 20:12:30 +010084 clrbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset));
Ley Foon Tan9e608212020-01-10 13:48:37 +080085
86 return wait_for_bit_le32(data->modrst_base + (bank * BANK_INCREMENT),
87 BIT(offset),
88 false, 500, false);
Dinh Nguyen2ac71882018-04-04 17:18:20 -050089}
90
Dinh Nguyen2ac71882018-04-04 17:18:20 -050091static const struct reset_ops socfpga_reset_ops = {
Dinh Nguyen2ac71882018-04-04 17:18:20 -050092 .rst_assert = socfpga_reset_assert,
93 .rst_deassert = socfpga_reset_deassert,
94};
95
96static int socfpga_reset_probe(struct udevice *dev)
97{
98 struct socfpga_reset_data *data = dev_get_priv(dev);
Dinh Nguyen2ac71882018-04-04 17:18:20 -050099 u32 modrst_offset;
Simon Goldschmidt1ea97502019-03-01 20:12:30 +0100100 void __iomem *membase;
Dinh Nguyen2ac71882018-04-04 17:18:20 -0500101
Masahiro Yamada702e57e2020-08-04 14:14:43 +0900102 membase = dev_read_addr_ptr(dev);
Dinh Nguyen2ac71882018-04-04 17:18:20 -0500103
Simon Goldschmidt6cdd0a42019-05-09 22:11:59 +0200104 modrst_offset = dev_read_u32_default(dev, "altr,modrst-offset", 0x10);
Simon Goldschmidt1ea97502019-03-01 20:12:30 +0100105 data->modrst_base = membase + modrst_offset;
Dinh Nguyen2ac71882018-04-04 17:18:20 -0500106
107 return 0;
108}
109
Simon Goldschmidtede6e7b2019-03-01 20:12:32 +0100110static int socfpga_reset_remove(struct udevice *dev)
111{
112 struct socfpga_reset_data *data = dev_get_priv(dev);
113
114 if (socfpga_reset_keep_enabled()) {
115 puts("Deasserting all peripheral resets\n");
116 writel(0, data->modrst_base + 4);
117 }
118
119 return 0;
120}
121
Simon Goldschmidtef72ba02019-07-15 21:47:55 +0200122static int socfpga_reset_bind(struct udevice *dev)
123{
124 int ret;
125 struct udevice *sys_child;
126
127 /*
128 * The sysreset driver does not have a device node, so bind it here.
129 * Bind it to the node, too, so that it can get its base address.
130 */
131 ret = device_bind_driver_to_node(dev, "socfpga_sysreset", "sysreset",
Simon Glassf10643c2020-12-19 10:40:14 -0700132 dev_ofnode(dev), &sys_child);
Simon Goldschmidtef72ba02019-07-15 21:47:55 +0200133 if (ret)
134 debug("Warning: No sysreset driver: ret=%d\n", ret);
135
136 return 0;
137}
138
Dinh Nguyen2ac71882018-04-04 17:18:20 -0500139static const struct udevice_id socfpga_reset_match[] = {
140 { .compatible = "altr,rst-mgr" },
141 { /* sentinel */ },
142};
143
144U_BOOT_DRIVER(socfpga_reset) = {
145 .name = "socfpga-reset",
146 .id = UCLASS_RESET,
147 .of_match = socfpga_reset_match,
Simon Goldschmidtef72ba02019-07-15 21:47:55 +0200148 .bind = socfpga_reset_bind,
Dinh Nguyen2ac71882018-04-04 17:18:20 -0500149 .probe = socfpga_reset_probe,
Simon Glass41575d82020-12-03 16:55:17 -0700150 .priv_auto = sizeof(struct socfpga_reset_data),
Dinh Nguyen2ac71882018-04-04 17:18:20 -0500151 .ops = &socfpga_reset_ops,
Simon Goldschmidtede6e7b2019-03-01 20:12:32 +0100152 .remove = socfpga_reset_remove,
153 .flags = DM_FLAG_OS_PREPARE,
Dinh Nguyen2ac71882018-04-04 17:18:20 -0500154};