| Dipen Dudhat | d789b5f | 2011-01-20 16:29:35 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2010-2011 Freescale Semiconductor, Inc. |
| 3 | * Author: Dipen Dudhat <dipen.dudhat@freescale.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or |
| 6 | * modify it under the terms of the GNU General Public License as |
| 7 | * published by the Free Software Foundation; either version 2 of |
| 8 | * the License, or (at your option) any later version. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 18 | * MA 02111-1307 USA |
| 19 | */ |
| 20 | |
| 21 | #include <common.h> |
| 22 | #include <asm/fsl_ifc.h> |
| 23 | |
| 24 | void print_ifc_regs(void) |
| 25 | { |
| 26 | int i, j; |
| 27 | |
| 28 | printf("IFC Controller Registers\n"); |
| 29 | for (i = 0; i < FSL_IFC_BANK_COUNT; i++) { |
| 30 | printf("CSPR%d:0x%08X\tAMASK%d:0x%08X\tCSOR%d:0x%08X\n", |
| 31 | i, get_ifc_cspr(i), i, get_ifc_amask(i), |
| 32 | i, get_ifc_csor(i)); |
| 33 | for (j = 0; j < 4; j++) |
| 34 | printf("IFC_FTIM%d:0x%08X\n", j, get_ifc_ftim(i, j)); |
| 35 | } |
| 36 | } |
| 37 | |
| 38 | void init_early_memctl_regs(void) |
| 39 | { |
| 40 | #if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0) |
| 41 | set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0); |
| 42 | set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0); |
| 43 | set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0); |
| 44 | |
| 45 | set_ifc_ftim(IFC_CS0, IFC_FTIM0, CONFIG_SYS_CS0_FTIM0); |
| 46 | set_ifc_ftim(IFC_CS0, IFC_FTIM1, CONFIG_SYS_CS0_FTIM1); |
| 47 | set_ifc_ftim(IFC_CS0, IFC_FTIM2, CONFIG_SYS_CS0_FTIM2); |
| 48 | set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3); |
| 49 | #endif |
| 50 | |
| 51 | #if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1) |
| 52 | set_ifc_csor(IFC_CS1, CONFIG_SYS_CSOR1); |
| 53 | set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1); |
| 54 | set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1); |
| 55 | |
| 56 | set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0); |
| 57 | set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1); |
| 58 | set_ifc_ftim(IFC_CS1, IFC_FTIM2, CONFIG_SYS_CS1_FTIM2); |
| 59 | set_ifc_ftim(IFC_CS1, IFC_FTIM3, CONFIG_SYS_CS1_FTIM3); |
| 60 | #endif |
| 61 | |
| 62 | #if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2) |
| 63 | set_ifc_csor(IFC_CS2, CONFIG_SYS_CSOR2); |
| 64 | set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2); |
| 65 | set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2); |
| 66 | |
| 67 | set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0); |
| 68 | set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1); |
| 69 | set_ifc_ftim(IFC_CS2, IFC_FTIM2, CONFIG_SYS_CS2_FTIM2); |
| 70 | set_ifc_ftim(IFC_CS2, IFC_FTIM3, CONFIG_SYS_CS2_FTIM3); |
| 71 | |
| 72 | #endif |
| 73 | |
| 74 | #if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3) |
| 75 | set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3); |
| 76 | set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3); |
| 77 | set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3); |
| 78 | |
| 79 | set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0); |
| 80 | set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1); |
| 81 | set_ifc_ftim(IFC_CS3, IFC_FTIM2, CONFIG_SYS_CS3_FTIM2); |
| 82 | set_ifc_ftim(IFC_CS3, IFC_FTIM3, CONFIG_SYS_CS3_FTIM3); |
| 83 | #endif |
| 84 | } |