wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1 | /* |
| 2 | * MPC8560 FCC Fast Ethernet |
| 3 | * Copyright (c) 2003 Motorola,Inc. |
| 4 | * Xianghua Xiao, (X.Xiao@motorola.com) |
| 5 | * |
| 6 | * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net) |
| 7 | * |
| 8 | * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
| 9 | * Marius Groeger <mgroeger@sysgo.de> |
| 10 | * |
| 11 | * See file CREDITS for list of people who contributed to this |
| 12 | * project. |
| 13 | * |
| 14 | * This program is free software; you can redistribute it and/or |
| 15 | * modify it under the terms of the GNU General Public License as |
| 16 | * published by the Free Software Foundation; either version 2 of |
| 17 | * the License, or (at your option) any later version. |
| 18 | * |
| 19 | * This program is distributed in the hope that it will be useful, |
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 22 | * GNU General Public License for more details. |
| 23 | * |
| 24 | * You should have received a copy of the GNU General Public License |
| 25 | * along with this program; if not, write to the Free Software |
| 26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 27 | * MA 02111-1307 USA |
| 28 | */ |
| 29 | |
| 30 | /* |
| 31 | * MPC8560 FCC Fast Ethernet |
| 32 | * Basic ET HW initialization and packet RX/TX routines |
| 33 | * |
| 34 | * This code will not perform the IO port configuration. This should be |
| 35 | * done in the iop_conf_t structure specific for the board. |
| 36 | * |
| 37 | * TODO: |
| 38 | * add a PHY driver to do the negotiation |
| 39 | * reflect negotiation results in FPSMR |
| 40 | * look for ways to configure the board specific stuff elsewhere, eg. |
| 41 | * config_xxx.h or the board directory |
| 42 | */ |
| 43 | |
| 44 | #include <common.h> |
| 45 | #include <malloc.h> |
| 46 | #include <asm/cpm_85xx.h> |
| 47 | #include <command.h> |
| 48 | #include <config.h> |
| 49 | #include <net.h> |
| 50 | |
Jon Loeliger | 4431283 | 2007-07-09 19:06:00 -0500 | [diff] [blame] | 51 | #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 52 | #include <miiphy.h> |
| 53 | #endif |
| 54 | |
Mike Frysinger | e2a5345 | 2011-10-02 10:01:27 +0000 | [diff] [blame] | 55 | #if defined(CONFIG_ETHER_ON_FCC) && defined(CONFIG_CMD_NET) |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 56 | |
| 57 | static struct ether_fcc_info_s |
| 58 | { |
| 59 | int ether_index; |
| 60 | int proff_enet; |
| 61 | ulong cpm_cr_enet_sblock; |
| 62 | ulong cpm_cr_enet_page; |
| 63 | ulong cmxfcr_mask; |
| 64 | ulong cmxfcr_value; |
| 65 | } |
| 66 | ether_fcc_info[] = |
| 67 | { |
| 68 | #ifdef CONFIG_ETHER_ON_FCC1 |
| 69 | { |
| 70 | 0, |
| 71 | PROFF_FCC1, |
| 72 | CPM_CR_FCC1_SBLOCK, |
| 73 | CPM_CR_FCC1_PAGE, |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 74 | CONFIG_SYS_CMXFCR_MASK1, |
| 75 | CONFIG_SYS_CMXFCR_VALUE1 |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 76 | }, |
| 77 | #endif |
| 78 | |
| 79 | #ifdef CONFIG_ETHER_ON_FCC2 |
| 80 | { |
| 81 | 1, |
| 82 | PROFF_FCC2, |
| 83 | CPM_CR_FCC2_SBLOCK, |
| 84 | CPM_CR_FCC2_PAGE, |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 85 | CONFIG_SYS_CMXFCR_MASK2, |
| 86 | CONFIG_SYS_CMXFCR_VALUE2 |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 87 | }, |
| 88 | #endif |
| 89 | |
| 90 | #ifdef CONFIG_ETHER_ON_FCC3 |
| 91 | { |
| 92 | 2, |
| 93 | PROFF_FCC3, |
| 94 | CPM_CR_FCC3_SBLOCK, |
| 95 | CPM_CR_FCC3_PAGE, |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 96 | CONFIG_SYS_CMXFCR_MASK3, |
| 97 | CONFIG_SYS_CMXFCR_VALUE3 |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 98 | }, |
| 99 | #endif |
| 100 | }; |
| 101 | |
| 102 | /*---------------------------------------------------------------------*/ |
| 103 | |
| 104 | /* Maximum input DMA size. Must be a should(?) be a multiple of 4. */ |
| 105 | #define PKT_MAXDMA_SIZE 1520 |
| 106 | |
| 107 | /* The FCC stores dest/src/type, data, and checksum for receive packets. */ |
| 108 | #define PKT_MAXBUF_SIZE 1518 |
| 109 | #define PKT_MINBUF_SIZE 64 |
| 110 | |
| 111 | /* Maximum input buffer size. Must be a multiple of 32. */ |
| 112 | #define PKT_MAXBLR_SIZE 1536 |
| 113 | |
| 114 | #define TOUT_LOOP 1000000 |
| 115 | |
| 116 | #define TX_BUF_CNT 2 |
| 117 | |
| 118 | static uint rxIdx; /* index of the current RX buffer */ |
| 119 | static uint txIdx; /* index of the current TX buffer */ |
| 120 | |
| 121 | /* |
| 122 | * FCC Ethernet Tx and Rx buffer descriptors. |
| 123 | * Provide for Double Buffering |
| 124 | * Note: PKTBUFSRX is defined in net.h |
| 125 | */ |
| 126 | |
| 127 | typedef volatile struct rtxbd { |
| 128 | cbd_t rxbd[PKTBUFSRX]; |
| 129 | cbd_t txbd[TX_BUF_CNT]; |
| 130 | } RTXBD; |
| 131 | |
| 132 | /* Good news: the FCC supports external BDs! */ |
| 133 | #ifdef __GNUC__ |
| 134 | static RTXBD rtx __attribute__ ((aligned(8))); |
| 135 | #else |
| 136 | #error "rtx must be 64-bit aligned" |
| 137 | #endif |
| 138 | |
wdenk | 2a8af18 | 2005-04-13 10:02:42 +0000 | [diff] [blame] | 139 | #undef ET_DEBUG |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 140 | |
Joe Hershberger | 412411c | 2012-05-22 07:56:12 +0000 | [diff] [blame] | 141 | static int fec_send(struct eth_device *dev, void *packet, int length) |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 142 | { |
| 143 | int i = 0; |
| 144 | int result = 0; |
| 145 | |
| 146 | if (length <= 0) { |
| 147 | printf("fec: bad packet size: %d\n", length); |
| 148 | goto out; |
| 149 | } |
| 150 | |
| 151 | for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { |
| 152 | if (i >= TOUT_LOOP) { |
| 153 | printf("fec: tx buffer not ready\n"); |
| 154 | goto out; |
| 155 | } |
| 156 | } |
| 157 | |
| 158 | rtx.txbd[txIdx].cbd_bufaddr = (uint)packet; |
| 159 | rtx.txbd[txIdx].cbd_datlen = length; |
| 160 | rtx.txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST | \ |
wdenk | a631092 | 2005-04-21 21:10:22 +0000 | [diff] [blame] | 161 | BD_ENET_TX_TC | BD_ENET_TX_PAD); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 162 | |
| 163 | for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { |
| 164 | if (i >= TOUT_LOOP) { |
| 165 | printf("fec: tx error\n"); |
| 166 | goto out; |
| 167 | } |
| 168 | } |
| 169 | |
| 170 | #ifdef ET_DEBUG |
| 171 | printf("cycles: 0x%x txIdx=0x%04x status: 0x%04x\n", i, txIdx,rtx.txbd[txIdx].cbd_sc); |
| 172 | printf("packets at 0x%08x, length_in_bytes=0x%x\n",(uint)packet,length); |
| 173 | for(i=0;i<(length/16 + 1);i++) { |
| 174 | printf("%08x %08x %08x %08x\n",*((uint *)rtx.txbd[txIdx].cbd_bufaddr+i*4),\ |
| 175 | *((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 1),*((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 2), \ |
| 176 | *((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 3)); |
| 177 | } |
| 178 | #endif |
| 179 | |
| 180 | /* return only status bits */ |
| 181 | result = rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_STATS; |
| 182 | txIdx = (txIdx + 1) % TX_BUF_CNT; |
| 183 | |
| 184 | out: |
| 185 | return result; |
| 186 | } |
| 187 | |
| 188 | static int fec_recv(struct eth_device* dev) |
| 189 | { |
| 190 | int length; |
| 191 | |
| 192 | for (;;) |
| 193 | { |
| 194 | if (rtx.rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { |
| 195 | length = -1; |
| 196 | break; /* nothing received - leave for() loop */ |
| 197 | } |
| 198 | length = rtx.rxbd[rxIdx].cbd_datlen; |
| 199 | |
| 200 | if (rtx.rxbd[rxIdx].cbd_sc & 0x003f) { |
| 201 | printf("fec: rx error %04x\n", rtx.rxbd[rxIdx].cbd_sc); |
| 202 | } |
| 203 | else { |
| 204 | /* Pass the packet up to the protocol layers. */ |
| 205 | NetReceive(NetRxPackets[rxIdx], length - 4); |
| 206 | } |
| 207 | |
| 208 | |
| 209 | /* Give the buffer back to the FCC. */ |
| 210 | rtx.rxbd[rxIdx].cbd_datlen = 0; |
| 211 | |
| 212 | /* wrap around buffer index when necessary */ |
| 213 | if ((rxIdx + 1) >= PKTBUFSRX) { |
| 214 | rtx.rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); |
| 215 | rxIdx = 0; |
| 216 | } |
| 217 | else { |
| 218 | rtx.rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; |
| 219 | rxIdx++; |
| 220 | } |
| 221 | } |
| 222 | return length; |
| 223 | } |
| 224 | |
| 225 | |
| 226 | static int fec_init(struct eth_device* dev, bd_t *bis) |
| 227 | { |
| 228 | struct ether_fcc_info_s * info = dev->priv; |
| 229 | int i; |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 230 | volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; |
Kumar Gala | aafeefb | 2007-11-28 00:36:33 -0600 | [diff] [blame] | 231 | volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 232 | fcc_enet_t *pram_ptr; |
| 233 | unsigned long mem_addr; |
| 234 | |
| 235 | #if 0 |
| 236 | mii_discover_phy(); |
| 237 | #endif |
| 238 | |
| 239 | /* 28.9 - (1-2): ioports have been set up already */ |
| 240 | |
| 241 | /* 28.9 - (3): connect FCC's tx and rx clocks */ |
Kumar Gala | aafeefb | 2007-11-28 00:36:33 -0600 | [diff] [blame] | 242 | cpm->im_cpm_mux.cmxuar = 0; /* ATM */ |
| 243 | cpm->im_cpm_mux.cmxfcr = (cpm->im_cpm_mux.cmxfcr & ~info->cmxfcr_mask) | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 244 | info->cmxfcr_value; |
| 245 | |
| 246 | /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, set Mode Ethernet */ |
| 247 | if(info->ether_index == 0) { |
Kumar Gala | aafeefb | 2007-11-28 00:36:33 -0600 | [diff] [blame] | 248 | cpm->im_cpm_fcc1.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 249 | } else if (info->ether_index == 1) { |
Kumar Gala | aafeefb | 2007-11-28 00:36:33 -0600 | [diff] [blame] | 250 | cpm->im_cpm_fcc2.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 251 | } else if (info->ether_index == 2) { |
Kumar Gala | aafeefb | 2007-11-28 00:36:33 -0600 | [diff] [blame] | 252 | cpm->im_cpm_fcc3.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 253 | } |
| 254 | |
| 255 | /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet,MII */ |
| 256 | if(info->ether_index == 0) { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 257 | cpm->im_cpm_fcc1.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 258 | } else if (info->ether_index == 1){ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 259 | cpm->im_cpm_fcc2.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 260 | } else if (info->ether_index == 2){ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 261 | cpm->im_cpm_fcc3.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 262 | } |
| 263 | |
| 264 | /* 28.9 - (6): FDSR: Ethernet Syn */ |
| 265 | if(info->ether_index == 0) { |
Kumar Gala | aafeefb | 2007-11-28 00:36:33 -0600 | [diff] [blame] | 266 | cpm->im_cpm_fcc1.fdsr = 0xD555; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 267 | } else if (info->ether_index == 1) { |
Kumar Gala | aafeefb | 2007-11-28 00:36:33 -0600 | [diff] [blame] | 268 | cpm->im_cpm_fcc2.fdsr = 0xD555; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 269 | } else if (info->ether_index == 2) { |
Kumar Gala | aafeefb | 2007-11-28 00:36:33 -0600 | [diff] [blame] | 270 | cpm->im_cpm_fcc3.fdsr = 0xD555; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 271 | } |
| 272 | |
| 273 | /* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */ |
| 274 | rxIdx = 0; |
| 275 | txIdx = 0; |
| 276 | |
| 277 | /* Setup Receiver Buffer Descriptors */ |
| 278 | for (i = 0; i < PKTBUFSRX; i++) |
| 279 | { |
| 280 | rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; |
| 281 | rtx.rxbd[i].cbd_datlen = 0; |
| 282 | rtx.rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i]; |
| 283 | } |
| 284 | rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; |
| 285 | |
| 286 | /* Setup Ethernet Transmitter Buffer Descriptors */ |
| 287 | for (i = 0; i < TX_BUF_CNT; i++) |
| 288 | { |
| 289 | rtx.txbd[i].cbd_sc = 0; |
| 290 | rtx.txbd[i].cbd_datlen = 0; |
| 291 | rtx.txbd[i].cbd_bufaddr = 0; |
| 292 | } |
| 293 | rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; |
| 294 | |
| 295 | /* 28.9 - (7): initialize parameter ram */ |
Kumar Gala | aafeefb | 2007-11-28 00:36:33 -0600 | [diff] [blame] | 296 | pram_ptr = (fcc_enet_t *)&(cpm->im_dprambase[info->proff_enet]); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 297 | |
| 298 | /* clear whole structure to make sure all reserved fields are zero */ |
| 299 | memset((void*)pram_ptr, 0, sizeof(fcc_enet_t)); |
| 300 | |
| 301 | /* |
| 302 | * common Parameter RAM area |
| 303 | * |
| 304 | * Allocate space in the reserved FCC area of DPRAM for the |
| 305 | * internal buffers. No one uses this space (yet), so we |
| 306 | * can do this. Later, we will add resource management for |
Wolfgang Denk | a889bd2 | 2005-12-06 15:02:31 +0100 | [diff] [blame] | 307 | * this area. |
| 308 | * CPM_FCC_SPECIAL_BASE: 0xB000 for MPC8540, MPC8560 |
| 309 | * 0x9000 for MPC8541, MPC8555 |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 310 | */ |
| 311 | mem_addr = CPM_FCC_SPECIAL_BASE + ((info->ether_index) * 64); |
| 312 | pram_ptr->fen_genfcc.fcc_riptr = mem_addr; |
| 313 | pram_ptr->fen_genfcc.fcc_tiptr = mem_addr+32; |
| 314 | /* |
| 315 | * Set maximum bytes per receive buffer. |
| 316 | * It must be a multiple of 32. |
| 317 | */ |
| 318 | pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE; /* 1536 */ |
| 319 | /* localbus SDRAM should be preferred */ |
| 320 | pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 321 | CONFIG_SYS_CPMFCR_RAMTYPE) << 24; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 322 | pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]); |
| 323 | pram_ptr->fen_genfcc.fcc_rbdstat = 0; |
| 324 | pram_ptr->fen_genfcc.fcc_rbdlen = 0; |
| 325 | pram_ptr->fen_genfcc.fcc_rdptr = 0; |
| 326 | /* localbus SDRAM should be preferred */ |
| 327 | pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 328 | CONFIG_SYS_CPMFCR_RAMTYPE) << 24; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 329 | pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]); |
| 330 | pram_ptr->fen_genfcc.fcc_tbdstat = 0; |
| 331 | pram_ptr->fen_genfcc.fcc_tbdlen = 0; |
| 332 | pram_ptr->fen_genfcc.fcc_tdptr = 0; |
| 333 | |
| 334 | /* protocol-specific area */ |
| 335 | pram_ptr->fen_statbuf = 0x0; |
| 336 | pram_ptr->fen_cmask = 0xdebb20e3; /* CRC mask */ |
| 337 | pram_ptr->fen_cpres = 0xffffffff; /* CRC preset */ |
| 338 | pram_ptr->fen_crcec = 0; |
| 339 | pram_ptr->fen_alec = 0; |
| 340 | pram_ptr->fen_disfc = 0; |
| 341 | pram_ptr->fen_retlim = 15; /* Retry limit threshold */ |
| 342 | pram_ptr->fen_retcnt = 0; |
| 343 | pram_ptr->fen_pper = 0; |
| 344 | pram_ptr->fen_boffcnt = 0; |
| 345 | pram_ptr->fen_gaddrh = 0; |
| 346 | pram_ptr->fen_gaddrl = 0; |
| 347 | pram_ptr->fen_mflr = PKT_MAXBUF_SIZE; /* maximum frame length register */ |
| 348 | /* |
| 349 | * Set Ethernet station address. |
| 350 | * |
| 351 | * This is supplied in the board information structure, so we |
| 352 | * copy that into the controller. |
| 353 | * So far we have only been given one Ethernet address. We make |
| 354 | * it unique by setting a few bits in the upper byte of the |
| 355 | * non-static part of the address. |
| 356 | */ |
| 357 | #define ea eth_get_dev()->enetaddr |
| 358 | pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4]; |
| 359 | pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2]; |
| 360 | pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0]; |
| 361 | #undef ea |
| 362 | pram_ptr->fen_ibdcount = 0; |
| 363 | pram_ptr->fen_ibdstart = 0; |
| 364 | pram_ptr->fen_ibdend = 0; |
| 365 | pram_ptr->fen_txlen = 0; |
| 366 | pram_ptr->fen_iaddrh = 0; /* disable hash */ |
| 367 | pram_ptr->fen_iaddrl = 0; |
| 368 | pram_ptr->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register: 64 */ |
| 369 | /* pad pointer. use tiptr since we don't need a specific padding char */ |
| 370 | pram_ptr->fen_padptr = pram_ptr->fen_genfcc.fcc_tiptr; |
| 371 | pram_ptr->fen_maxd1 = PKT_MAXDMA_SIZE; /* maximum DMA1 length:1520 */ |
| 372 | pram_ptr->fen_maxd2 = PKT_MAXDMA_SIZE; /* maximum DMA2 length:1520 */ |
| 373 | |
| 374 | #if defined(ET_DEBUG) |
| 375 | printf("parm_ptr(0xff788500) = %p\n",pram_ptr); |
| 376 | printf("pram_ptr->fen_genfcc.fcc_rbase %08x\n", |
| 377 | pram_ptr->fen_genfcc.fcc_rbase); |
| 378 | printf("pram_ptr->fen_genfcc.fcc_tbase %08x\n", |
| 379 | pram_ptr->fen_genfcc.fcc_tbase); |
| 380 | #endif |
| 381 | |
| 382 | /* 28.9 - (8)(9): clear out events in FCCE */ |
| 383 | /* 28.9 - (9): FCCM: mask all events */ |
| 384 | if(info->ether_index == 0) { |
Kumar Gala | aafeefb | 2007-11-28 00:36:33 -0600 | [diff] [blame] | 385 | cpm->im_cpm_fcc1.fcce = ~0x0; |
| 386 | cpm->im_cpm_fcc1.fccm = 0; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 387 | } else if (info->ether_index == 1) { |
Kumar Gala | aafeefb | 2007-11-28 00:36:33 -0600 | [diff] [blame] | 388 | cpm->im_cpm_fcc2.fcce = ~0x0; |
| 389 | cpm->im_cpm_fcc2.fccm = 0; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 390 | } else if (info->ether_index == 2) { |
Kumar Gala | aafeefb | 2007-11-28 00:36:33 -0600 | [diff] [blame] | 391 | cpm->im_cpm_fcc3.fcce = ~0x0; |
| 392 | cpm->im_cpm_fcc3.fccm = 0; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 393 | } |
| 394 | |
| 395 | /* 28.9 - (10-12): we don't use ethernet interrupts */ |
| 396 | |
| 397 | /* 28.9 - (13) |
| 398 | * |
| 399 | * Let's re-initialize the channel now. We have to do it later |
| 400 | * than the manual describes because we have just now finished |
| 401 | * the BD initialization. |
| 402 | */ |
| 403 | cp->cpcr = mk_cr_cmd(info->cpm_cr_enet_page, |
| 404 | info->cpm_cr_enet_sblock, |
| 405 | 0x0c, |
| 406 | CPM_CR_INIT_TRX) | CPM_CR_FLG; |
| 407 | do { |
| 408 | __asm__ __volatile__ ("eieio"); |
| 409 | } while (cp->cpcr & CPM_CR_FLG); |
| 410 | |
| 411 | /* 28.9 - (14): enable tx/rx in gfmr */ |
| 412 | if(info->ether_index == 0) { |
Kumar Gala | aafeefb | 2007-11-28 00:36:33 -0600 | [diff] [blame] | 413 | cpm->im_cpm_fcc1.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 414 | } else if (info->ether_index == 1) { |
Kumar Gala | aafeefb | 2007-11-28 00:36:33 -0600 | [diff] [blame] | 415 | cpm->im_cpm_fcc2.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 416 | } else if (info->ether_index == 2) { |
Kumar Gala | aafeefb | 2007-11-28 00:36:33 -0600 | [diff] [blame] | 417 | cpm->im_cpm_fcc3.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 418 | } |
| 419 | |
wdenk | a631092 | 2005-04-21 21:10:22 +0000 | [diff] [blame] | 420 | return 1; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 421 | } |
| 422 | |
| 423 | static void fec_halt(struct eth_device* dev) |
| 424 | { |
| 425 | struct ether_fcc_info_s * info = dev->priv; |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 426 | volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 427 | |
| 428 | /* write GFMR: disable tx/rx */ |
| 429 | if(info->ether_index == 0) { |
Kumar Gala | aafeefb | 2007-11-28 00:36:33 -0600 | [diff] [blame] | 430 | cpm->im_cpm_fcc1.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 431 | } else if(info->ether_index == 1) { |
Kumar Gala | aafeefb | 2007-11-28 00:36:33 -0600 | [diff] [blame] | 432 | cpm->im_cpm_fcc2.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 433 | } else if(info->ether_index == 2) { |
Kumar Gala | aafeefb | 2007-11-28 00:36:33 -0600 | [diff] [blame] | 434 | cpm->im_cpm_fcc3.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 435 | } |
| 436 | } |
| 437 | |
| 438 | int fec_initialize(bd_t *bis) |
| 439 | { |
| 440 | struct eth_device* dev; |
| 441 | int i; |
| 442 | |
| 443 | for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++) |
| 444 | { |
| 445 | dev = (struct eth_device*) malloc(sizeof *dev); |
| 446 | memset(dev, 0, sizeof *dev); |
| 447 | |
Heiko Schocher | 48690d8 | 2010-07-20 17:45:02 +0200 | [diff] [blame] | 448 | sprintf(dev->name, "FCC%d", |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 449 | ether_fcc_info[i].ether_index + 1); |
| 450 | dev->priv = ðer_fcc_info[i]; |
| 451 | dev->init = fec_init; |
| 452 | dev->halt = fec_halt; |
| 453 | dev->send = fec_send; |
| 454 | dev->recv = fec_recv; |
| 455 | |
| 456 | eth_register(dev); |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 457 | |
Jon Loeliger | 4431283 | 2007-07-09 19:06:00 -0500 | [diff] [blame] | 458 | #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) \ |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 459 | && defined(CONFIG_BITBANGMII) |
| 460 | miiphy_register(dev->name, |
| 461 | bb_miiphy_read, bb_miiphy_write); |
| 462 | #endif |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 463 | } |
| 464 | |
| 465 | return 1; |
| 466 | } |
| 467 | |
Jon Loeliger | 068b60a | 2007-07-10 10:27:39 -0500 | [diff] [blame] | 468 | #endif |