Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright 2008 Freescale Semiconductor. |
| 3 | * |
| 4 | * See file CREDITS for list of people who contributed to this |
| 5 | * project. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307 USA |
| 21 | */ |
| 22 | |
| 23 | #include <common.h> |
| 24 | #include <asm/processor.h> |
| 25 | #include <ioports.h> |
| 26 | #include <asm/io.h> |
| 27 | #include "mp.h" |
| 28 | |
| 29 | DECLARE_GLOBAL_DATA_PTR; |
| 30 | |
| 31 | #define BOOT_ENTRY_ADDR 0 |
| 32 | #define BOOT_ENTRY_PIR 1 |
| 33 | #define BOOT_ENTRY_R3 2 |
| 34 | #define BOOT_ENTRY_R4 3 |
| 35 | #define BOOT_ENTRY_R6 4 |
| 36 | #define BOOT_ENTRY_R7 5 |
| 37 | #define NUM_BOOT_ENTRY 6 |
| 38 | |
| 39 | u32 get_my_id() |
| 40 | { |
| 41 | return mfspr(SPRN_PIR); |
| 42 | } |
| 43 | |
| 44 | int cpu_reset(int nr) |
| 45 | { |
| 46 | volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR); |
| 47 | out_be32(&pic->pir, 1 << nr); |
| 48 | (void)in_be32(&pic->pir); |
| 49 | out_be32(&pic->pir, 0x0); |
| 50 | |
| 51 | return 0; |
| 52 | } |
| 53 | |
| 54 | int cpu_status(int nr) |
| 55 | { |
| 56 | u32 *table, id = get_my_id(); |
| 57 | |
| 58 | if (nr == id) { |
| 59 | table = (u32 *)get_spin_addr(); |
| 60 | printf("table base @ 0x%08x\n", table); |
| 61 | } else { |
| 62 | table = (u32 *)get_spin_addr() + nr * NUM_BOOT_ENTRY; |
| 63 | printf("Running on cpu %d\n", id); |
| 64 | printf("\n"); |
| 65 | printf("table @ 0x%08x:\n", table); |
| 66 | printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR]); |
| 67 | printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]); |
| 68 | printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3]); |
| 69 | printf(" r4 - 0x%08x\n", table[BOOT_ENTRY_R4]); |
| 70 | printf(" r6 - 0x%08x\n", table[BOOT_ENTRY_R6]); |
| 71 | printf(" r7 - 0x%08x\n", table[BOOT_ENTRY_R7]); |
| 72 | } |
| 73 | |
| 74 | return 0; |
| 75 | } |
| 76 | |
| 77 | int cpu_release(int nr, unsigned long boot_addr, int argc, char *argv[]) |
| 78 | { |
| 79 | u32 i, val, *table = (u32 *)get_spin_addr() + nr * NUM_BOOT_ENTRY; |
| 80 | |
| 81 | if (nr == get_my_id()) { |
| 82 | printf("Invalid to release the boot core.\n\n"); |
| 83 | return 1; |
| 84 | } |
| 85 | |
| 86 | if (argc != 5) { |
| 87 | printf("Invalid number of arguments to release.\n\n"); |
| 88 | return 1; |
| 89 | } |
| 90 | |
| 91 | /* handle pir, r3, r4, r6, r7 */ |
| 92 | for (i = 0; i < 5; i++) { |
| 93 | if (argv[i][0] != '-') { |
| 94 | val = simple_strtoul(argv[i], NULL, 16); |
| 95 | table[i+BOOT_ENTRY_PIR] = val; |
| 96 | } |
| 97 | } |
| 98 | |
| 99 | table[BOOT_ENTRY_ADDR] = boot_addr; |
| 100 | |
| 101 | return 0; |
| 102 | } |
| 103 | |
| 104 | ulong get_spin_addr(void) |
| 105 | { |
| 106 | extern ulong __secondary_start_page; |
| 107 | extern ulong __spin_table; |
| 108 | |
| 109 | ulong addr = |
| 110 | (ulong)&__spin_table - (ulong)&__secondary_start_page; |
| 111 | addr += 0xfffff000; |
| 112 | |
| 113 | return addr; |
| 114 | } |
| 115 | |
| 116 | static void pq3_mp_up(unsigned long bootpg) |
| 117 | { |
| 118 | u32 up, cpu_up_mask, whoami; |
| 119 | u32 *table = (u32 *)get_spin_addr(); |
| 120 | volatile u32 bpcr; |
| 121 | volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); |
| 122 | volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); |
| 123 | volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR); |
| 124 | u32 devdisr; |
| 125 | int timeout = 10; |
| 126 | |
| 127 | whoami = in_be32(&pic->whoami); |
| 128 | out_be32(&ecm->bptr, 0x80000000 | (bootpg >> 12)); |
| 129 | |
| 130 | /* disable time base at the platform */ |
| 131 | devdisr = in_be32(&gur->devdisr); |
| 132 | if (whoami) |
| 133 | devdisr |= MPC85xx_DEVDISR_TB0; |
| 134 | else |
| 135 | devdisr |= MPC85xx_DEVDISR_TB1; |
| 136 | out_be32(&gur->devdisr, devdisr); |
| 137 | |
| 138 | /* release the hounds */ |
| 139 | up = ((1 << CONFIG_NR_CPUS) - 1); |
| 140 | bpcr = in_be32(&ecm->eebpcr); |
| 141 | bpcr |= (up << 24); |
| 142 | out_be32(&ecm->eebpcr, bpcr); |
| 143 | asm("sync; isync; msync"); |
| 144 | |
| 145 | cpu_up_mask = 1 << whoami; |
| 146 | /* wait for everyone */ |
| 147 | while (timeout) { |
| 148 | int i; |
| 149 | for (i = 1; i < CONFIG_NR_CPUS; i++) { |
| 150 | if (table[i * NUM_BOOT_ENTRY]) |
| 151 | cpu_up_mask |= (1 << i); |
| 152 | }; |
| 153 | |
| 154 | if ((cpu_up_mask & up) == up) |
| 155 | break; |
| 156 | |
| 157 | udelay(100); |
| 158 | timeout--; |
| 159 | } |
| 160 | |
| 161 | /* enable time base at the platform */ |
| 162 | if (whoami) |
| 163 | devdisr |= MPC85xx_DEVDISR_TB1; |
| 164 | else |
| 165 | devdisr |= MPC85xx_DEVDISR_TB0; |
| 166 | out_be32(&gur->devdisr, devdisr); |
| 167 | mtspr(SPRN_TBWU, 0); |
| 168 | mtspr(SPRN_TBWL, 0); |
| 169 | |
| 170 | devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1); |
| 171 | out_be32(&gur->devdisr, devdisr); |
| 172 | } |
| 173 | |
| 174 | void setup_mp(void) |
| 175 | { |
| 176 | extern ulong __secondary_start_page; |
| 177 | ulong fixup = (ulong)&__secondary_start_page; |
| 178 | u32 bootpg; |
| 179 | |
| 180 | /* if we have 4G or more of memory, put the boot page at 4Gb-4k */ |
| 181 | if ((u64)gd->ram_size > 0xfffff000) |
| 182 | bootpg = 0xfffff000; |
| 183 | else |
| 184 | bootpg = gd->ram_size - 4096; |
| 185 | |
| 186 | memcpy((void *)bootpg, (void *)fixup, 4096); |
| 187 | flush_cache(bootpg, 4096); |
| 188 | |
| 189 | pq3_mp_up(bootpg); |
| 190 | } |