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Stefano Babic1fdabed2012-02-07 23:29:34 +00001/*
2 * Copyright (C) 2011
3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
4 *
5 * Copyright (C) 2009 TechNexion Ltd.
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Stefano Babic1fdabed2012-02-07 23:29:34 +00008 */
9
10#include <common.h>
11#include <netdev.h>
Stefano Babic62986872012-08-29 01:22:07 +000012#include <malloc.h>
Stefano Babic1fdabed2012-02-07 23:29:34 +000013#include <fpga.h>
Stefano Babic62986872012-08-29 01:22:07 +000014#include <video_fb.h>
Stefano Babic1fdabed2012-02-07 23:29:34 +000015#include <asm/io.h>
16#include <asm/arch/mem.h>
17#include <asm/arch/mux.h>
18#include <asm/arch/sys_proto.h>
19#include <asm/omap_gpio.h>
20#include <asm/arch/mmc_host_def.h>
Stefano Babic62986872012-08-29 01:22:07 +000021#include <asm/arch/dss.h>
Lokesh Vutlaaf1d0022013-05-30 02:54:32 +000022#include <asm/arch/clock.h>
Stefano Babic1fdabed2012-02-07 23:29:34 +000023#include <i2c.h>
24#include <spartan3.h>
25#include <asm/gpio.h>
26#ifdef CONFIG_USB_EHCI
27#include <usb.h>
28#include <asm/ehci-omap.h>
29#endif
30#include "mt_ventoux.h"
31
32DECLARE_GLOBAL_DATA_PTR;
33
Stefano Babicff530fc2012-08-29 01:22:04 +000034#define BUZZER 140
35#define SPEAKER 141
Stefano Babic9f670542012-10-16 04:02:20 +000036#define USB1_PWR 127
37#define USB2_PWR 149
Stefano Babicff530fc2012-08-29 01:22:04 +000038
Stefano Babic1fdabed2012-02-07 23:29:34 +000039#ifndef CONFIG_FPGA
40#error "The Teejet mt_ventoux must have CONFIG_FPGA enabled"
41#endif
42
43#define FPGA_RESET 62
44#define FPGA_PROG 116
45#define FPGA_CCLK 117
46#define FPGA_DIN 118
47#define FPGA_INIT 119
48#define FPGA_DONE 154
49
Stefano Babic62986872012-08-29 01:22:07 +000050#define LCD_PWR 138
51#define LCD_PON_PIN 139
52
53#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
54static struct {
55 u32 xres;
56 u32 yres;
57} panel_resolution[] = {
58 { 480, 272 },
59 { 800, 480 }
60};
61
62static struct panel_config lcd_cfg[] = {
63 {
Stefano Babicfe2d59a2012-11-23 05:19:24 +000064 .timing_h = PANEL_TIMING_H(40, 5, 2),
65 .timing_v = PANEL_TIMING_V(8, 8, 2),
66 .pol_freq = 0x00003000, /* Pol Freq */
67 .divisor = 0x00010033, /* 9 Mhz Pixel Clock */
Stefano Babic62986872012-08-29 01:22:07 +000068 .panel_type = 0x01, /* TFT */
69 .data_lines = 0x03, /* 24 Bit RGB */
70 .load_mode = 0x02, /* Frame Mode */
71 .panel_color = 0,
Nikita Kiryanovbcc6cc92013-01-30 21:39:55 +000072 .gfx_format = GFXFORMAT_RGB24_UNPACKED,
Stefano Babic62986872012-08-29 01:22:07 +000073 },
74 {
75 .timing_h = PANEL_TIMING_H(20, 192, 4),
76 .timing_v = PANEL_TIMING_V(2, 20, 10),
77 .pol_freq = 0x00004000, /* Pol Freq */
78 .divisor = 0x0001000E, /* 36Mhz Pixel Clock */
79 .panel_type = 0x01, /* TFT */
80 .data_lines = 0x03, /* 24 Bit RGB */
81 .load_mode = 0x02, /* Frame Mode */
82 .panel_color = 0,
Nikita Kiryanovbcc6cc92013-01-30 21:39:55 +000083 .gfx_format = GFXFORMAT_RGB24_UNPACKED,
Stefano Babic62986872012-08-29 01:22:07 +000084 }
85};
86#endif
87
Stefano Babic1fdabed2012-02-07 23:29:34 +000088/* Timing definitions for FPGA */
89static const u32 gpmc_fpga[] = {
90 FPGA_GPMC_CONFIG1,
91 FPGA_GPMC_CONFIG2,
92 FPGA_GPMC_CONFIG3,
93 FPGA_GPMC_CONFIG4,
94 FPGA_GPMC_CONFIG5,
95 FPGA_GPMC_CONFIG6,
96};
97
98#ifdef CONFIG_USB_EHCI
99static struct omap_usbhs_board_data usbhs_bdata = {
100 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
101 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
102 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
103};
104
Troy Kisky127efc42013-10-10 15:27:57 -0700105int ehci_hcd_init(int index, enum usb_init_type init,
106 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
Stefano Babic1fdabed2012-02-07 23:29:34 +0000107{
Mateusz Zalega16297cf2013-10-04 19:22:26 +0200108 return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
Stefano Babic1fdabed2012-02-07 23:29:34 +0000109}
110
Lucas Stach676ae062012-09-26 00:14:35 +0200111int ehci_hcd_stop(int index)
Stefano Babic1fdabed2012-02-07 23:29:34 +0000112{
113 return omap_ehci_hcd_stop();
114}
115#endif
116
117
118static inline void fpga_reset(int nassert)
119{
120 gpio_set_value(FPGA_RESET, !nassert);
121}
122
123int fpga_pgm_fn(int nassert, int nflush, int cookie)
124{
125 debug("%s:%d: FPGA PROGRAM ", __func__, __LINE__);
126
127 gpio_set_value(FPGA_PROG, !nassert);
128
129 return nassert;
130}
131
132int fpga_init_fn(int cookie)
133{
134 return !gpio_get_value(FPGA_INIT);
135}
136
137int fpga_done_fn(int cookie)
138{
139 return gpio_get_value(FPGA_DONE);
140}
141
142int fpga_pre_config_fn(int cookie)
143{
144 debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__);
145
146 /* Setting GPIOs for programming Mode */
147 gpio_request(FPGA_RESET, "FPGA_RESET");
148 gpio_direction_output(FPGA_RESET, 1);
149 gpio_request(FPGA_PROG, "FPGA_PROG");
150 gpio_direction_output(FPGA_PROG, 1);
151 gpio_request(FPGA_CCLK, "FPGA_CCLK");
152 gpio_direction_output(FPGA_CCLK, 1);
153 gpio_request(FPGA_DIN, "FPGA_DIN");
154 gpio_direction_output(FPGA_DIN, 0);
155 gpio_request(FPGA_INIT, "FPGA_INIT");
156 gpio_direction_input(FPGA_INIT);
157 gpio_request(FPGA_DONE, "FPGA_DONE");
158 gpio_direction_input(FPGA_DONE);
159
160 /* Be sure that signal are deasserted */
161 gpio_set_value(FPGA_RESET, 1);
162 gpio_set_value(FPGA_PROG, 1);
163
164 return 0;
165}
166
167int fpga_post_config_fn(int cookie)
168{
169 debug("%s:%d: FPGA post-configuration\n", __func__, __LINE__);
170
York Sun472d5462013-04-01 11:29:11 -0700171 fpga_reset(true);
Stefano Babic1fdabed2012-02-07 23:29:34 +0000172 udelay(100);
York Sun472d5462013-04-01 11:29:11 -0700173 fpga_reset(false);
Stefano Babic1fdabed2012-02-07 23:29:34 +0000174
175 return 0;
176}
177
178/* Write program to the FPGA */
179int fpga_wr_fn(int nassert_write, int flush, int cookie)
180{
181 gpio_set_value(FPGA_DIN, nassert_write);
182
183 return nassert_write;
184}
185
186int fpga_clk_fn(int assert_clk, int flush, int cookie)
187{
188 gpio_set_value(FPGA_CCLK, assert_clk);
189
190 return assert_clk;
191}
192
Michal Simek2a6e3862014-03-13 11:28:42 +0100193xilinx_spartan3_slave_serial_fns mt_ventoux_fpga_fns = {
Stefano Babic1fdabed2012-02-07 23:29:34 +0000194 fpga_pre_config_fn,
195 fpga_pgm_fn,
196 fpga_clk_fn,
197 fpga_init_fn,
198 fpga_done_fn,
199 fpga_wr_fn,
200 fpga_post_config_fn,
201};
202
Michal Simekf8c1be92014-03-13 12:49:21 +0100203xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial,
Stefano Babic1fdabed2012-02-07 23:29:34 +0000204 (void *)&mt_ventoux_fpga_fns, 0);
205
206/* Initialize the FPGA */
207static void mt_ventoux_init_fpga(void)
208{
209 fpga_pre_config_fn(0);
210
211 /* Setting CS1 for FPGA access */
212 enable_gpmc_cs_config(gpmc_fpga, &gpmc_cfg->cs[1],
213 FPGA_BASE_ADDR, GPMC_SIZE_128M);
214
215 fpga_init();
216 fpga_add(fpga_xilinx, &fpga);
217}
218
219/*
220 * Routine: board_init
221 * Description: Early hardware init.
222 */
223int board_init(void)
224{
225 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
226
227 /* boot param addr */
228 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
229
230 mt_ventoux_init_fpga();
231
Stefano Babicff530fc2012-08-29 01:22:04 +0000232 /* GPIO_140: speaker #mute */
233 MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4))
234 /* GPIO_141: Buzz Hi */
235 MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4))
236
237 /* Turning off the buzzer */
238 gpio_request(BUZZER, "BUZZER_MUTE");
239 gpio_request(SPEAKER, "SPEAKER");
240 gpio_direction_output(BUZZER, 0);
241 gpio_direction_output(SPEAKER, 0);
242
Stefano Babic9f670542012-10-16 04:02:20 +0000243 /* Activate USB power */
244 gpio_request(USB1_PWR, "USB1_PWR");
245 gpio_request(USB2_PWR, "USB2_PWR");
246 gpio_direction_output(USB1_PWR, 1);
247 gpio_direction_output(USB2_PWR, 1);
248
Stefano Babic1fdabed2012-02-07 23:29:34 +0000249 return 0;
250}
251
Stefano Babic31f5b652012-11-23 05:19:25 +0000252#ifndef CONFIG_SPL_BUILD
Stefano Babic9d5fc232012-08-29 01:22:03 +0000253int misc_init_r(void)
254{
255 char *eth_addr;
Stefano Babic31f5b652012-11-23 05:19:25 +0000256 struct tam3517_module_info info;
257 int ret;
Stefano Babic9d5fc232012-08-29 01:22:03 +0000258
Stefano Babic31f5b652012-11-23 05:19:25 +0000259 TAM3517_READ_EEPROM(&info, ret);
Paul Kocialkowski679f82c2015-08-27 19:37:13 +0200260 omap_die_id_display();
Stefano Babic9d5fc232012-08-29 01:22:03 +0000261
Stefano Babic31f5b652012-11-23 05:19:25 +0000262 if (ret)
Stefano Babic9d5fc232012-08-29 01:22:03 +0000263 return 0;
Stefano Babic31f5b652012-11-23 05:19:25 +0000264 eth_addr = getenv("ethaddr");
265 if (!eth_addr)
266 TAM3517_READ_MAC_FROM_EEPROM(&info);
Stefano Babic9d5fc232012-08-29 01:22:03 +0000267
Stefano Babic31f5b652012-11-23 05:19:25 +0000268 TAM3517_PRINT_SOM_INFO(&info);
Stefano Babic9d5fc232012-08-29 01:22:03 +0000269 return 0;
270}
Stefano Babic31f5b652012-11-23 05:19:25 +0000271#endif
Stefano Babic9d5fc232012-08-29 01:22:03 +0000272
Stefano Babic1fdabed2012-02-07 23:29:34 +0000273/*
274 * Routine: set_muxconf_regs
275 * Description: Setting up the configuration Mux registers specific to the
276 * hardware. Many pins need to be moved from protect to primary
277 * mode.
278 */
279void set_muxconf_regs(void)
280{
281 MUX_MT_VENTOUX();
282}
283
284/*
285 * Initializes on-chip ethernet controllers.
286 * to override, implement board_eth_init()
287 */
288int board_eth_init(bd_t *bis)
289{
290 davinci_emac_initialize();
291 return 0;
292}
293
294#if defined(CONFIG_OMAP_HSMMC) && \
295 !defined(CONFIG_SPL_BUILD)
296int board_mmc_init(bd_t *bis)
297{
Nikita Kiryanove3913f52012-12-03 02:19:47 +0000298 return omap_mmc_init(0, 0, 0, -1, -1);
Stefano Babic1fdabed2012-02-07 23:29:34 +0000299}
300#endif
Stefano Babic62986872012-08-29 01:22:07 +0000301
302#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
303int board_video_init(void)
304{
305 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
306 struct panel_config *panel = &lcd_cfg[0];
307 char *s;
308 u32 index = 0;
309
310 void *fb;
311
312 fb = (void *)0x88000000;
313
314 s = getenv("panel");
315 if (s) {
316 index = simple_strtoul(s, NULL, 10);
317 if (index < ARRAY_SIZE(lcd_cfg))
318 panel = &lcd_cfg[index];
319 else
320 return 0;
321 }
322
323 panel->frame_buffer = fb;
324 printf("Panel: %dx%d\n", panel_resolution[index].xres,
325 panel_resolution[index].yres);
326 panel->lcd_size = (panel_resolution[index].yres - 1) << 16 |
327 (panel_resolution[index].xres - 1);
328
329 gpio_request(LCD_PWR, "LCD Power");
330 gpio_request(LCD_PON_PIN, "LCD Pon");
331 gpio_direction_output(LCD_PWR, 0);
332 gpio_direction_output(LCD_PON_PIN, 1);
333
334
335 setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
336 setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON);
337
338 omap3_dss_panel_config(panel);
339 omap3_dss_enable();
340
341 return 0;
342}
343#endif