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Prabhakar Kushwaha7d436072013-09-12 11:11:28 +05301/*
York Sunc60dee02014-03-27 17:54:48 -07002 * Copyright 2013-2014 Freescale Semiconductor, Inc.
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +05303 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#ifndef __CONFIG_H
24#define __CONFIG_H
25
26/*
27 * T1040 QDS board configuration file
28 */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053029
30#ifdef CONFIG_RAMBOOT_PBL
31#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
32#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
Masahiro Yamadae4536f82014-03-11 11:05:16 +090033#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg
34#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053035#endif
36
37/* High Level Configuration Options */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053038#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053039
Tang Yuantian48f6a9a2014-04-17 15:33:44 +080040/* support deep sleep */
41#define CONFIG_DEEP_SLEEP
Tang Yuantian48f6a9a2014-04-17 15:33:44 +080042
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053043#ifndef CONFIG_RESET_VECTOR_ADDRESS
44#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
45#endif
46
47#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
York Sun51370d52016-12-28 08:43:45 -080048#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053049#define CONFIG_PCI_INDIRECT_BRIDGE
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -040050#define CONFIG_PCIE1 /* PCIE controller 1 */
51#define CONFIG_PCIE2 /* PCIE controller 2 */
52#define CONFIG_PCIE3 /* PCIE controller 3 */
53#define CONFIG_PCIE4 /* PCIE controller 4 */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053054
55#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
56#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
57
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053058#define CONFIG_ENV_OVERWRITE
59
Masahiro Yamadae856bdc2017-02-11 22:43:54 +090060#ifdef CONFIG_MTD_NOR_FLASH
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053061#if defined(CONFIG_SPIFLASH)
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053062#define CONFIG_ENV_SPI_BUS 0
63#define CONFIG_ENV_SPI_CS 0
64#define CONFIG_ENV_SPI_MAX_HZ 10000000
65#define CONFIG_ENV_SPI_MODE 0
66#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
67#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
68#define CONFIG_ENV_SECT_SIZE 0x10000
69#elif defined(CONFIG_SDCARD)
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053070#define CONFIG_SYS_MMC_ENV_DEV 0
71#define CONFIG_ENV_SIZE 0x2000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053072#define CONFIG_ENV_OFFSET (512 * 1658)
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053073#elif defined(CONFIG_NAND)
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053074#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053075#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053076#else
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053077#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
78#define CONFIG_ENV_SIZE 0x2000
79#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
80#endif
Masahiro Yamadae856bdc2017-02-11 22:43:54 +090081#else /* CONFIG_MTD_NOR_FLASH */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053082#define CONFIG_ENV_SIZE 0x2000
83#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
84#endif
85
86#ifndef __ASSEMBLY__
87unsigned long get_board_sys_clk(void);
88unsigned long get_board_ddr_clk(void);
89#endif
90
91#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
92#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
93
94/*
95 * These can be toggled for performance analysis, otherwise use default.
96 */
97#define CONFIG_SYS_CACHE_STASHING
98#define CONFIG_BACKSIDE_L2_CACHE
99#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
100#define CONFIG_BTB /* toggle branch predition */
101#define CONFIG_DDR_ECC
102#ifdef CONFIG_DDR_ECC
103#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
104#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
105#endif
106
107#define CONFIG_ENABLE_36BIT_PHYS
108
109#define CONFIG_ADDR_MAP
110#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
111
112#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
113#define CONFIG_SYS_MEMTEST_END 0x00400000
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530114
115/*
116 * Config the L3 Cache as L3 SRAM
117 */
118#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
119
120#define CONFIG_SYS_DCSRBAR 0xf0000000
121#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
122
123/* EEPROM */
124#define CONFIG_ID_EEPROM
125#define CONFIG_SYS_I2C_EEPROM_NXID
126#define CONFIG_SYS_EEPROM_BUS_NUM 0
127#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
128#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
129#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
130#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
131
132/*
133 * DDR Setup
134 */
135#define CONFIG_VERY_BIG_RAM
136#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
137#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
138
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530139#define CONFIG_DIMM_SLOTS_PER_CTLR 1
Priyanka Jain2eb3ac72014-01-03 11:24:55 +0530140#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530141
142#define CONFIG_DDR_SPD
York Sun1b2af9b2014-10-27 11:45:11 -0700143#define CONFIG_FSL_DDR_INTERACTIVE
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530144
145#define CONFIG_SYS_SPD_BUS_NUM 0
146#define SPD_EEPROM_ADDRESS 0x51
147
148#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
149
150/*
151 * IFC Definitions
152 */
153#define CONFIG_SYS_FLASH_BASE 0xe0000000
154#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
155
156#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
157#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
158 + 0x8000000) | \
159 CSPR_PORT_SIZE_16 | \
160 CSPR_MSEL_NOR | \
161 CSPR_V)
162#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
163#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
164 CSPR_PORT_SIZE_16 | \
165 CSPR_MSEL_NOR | \
166 CSPR_V)
167#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
Sandeep Singh377ffcf2014-06-05 18:49:57 +0530168
169/*
170 * TDM Definition
171 */
172#define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
173
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530174/* NOR Flash Timing Params */
175#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
176#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
177 FTIM0_NOR_TEADC(0x5) | \
178 FTIM0_NOR_TEAHC(0x5))
179#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
180 FTIM1_NOR_TRAD_NOR(0x1A) |\
181 FTIM1_NOR_TSEQRAD_NOR(0x13))
182#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
183 FTIM2_NOR_TCH(0x4) | \
184 FTIM2_NOR_TWPH(0x0E) | \
185 FTIM2_NOR_TWP(0x1c))
186#define CONFIG_SYS_NOR_FTIM3 0x0
187
188#define CONFIG_SYS_FLASH_QUIET_TEST
189#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
190
191#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
192#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
193#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
194#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
195
196#define CONFIG_SYS_FLASH_EMPTY_INFO
197#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
198 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
199#define CONFIG_FSL_QIXIS /* use common QIXIS code */
200#define QIXIS_BASE 0xffdf0000
201#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
202#define QIXIS_LBMAP_SWITCH 0x06
203#define QIXIS_LBMAP_MASK 0x0f
204#define QIXIS_LBMAP_SHIFT 0
205#define QIXIS_LBMAP_DFLTBANK 0x00
206#define QIXIS_LBMAP_ALTBANK 0x04
207#define QIXIS_RST_CTL_RESET 0x31
208#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
209#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
210#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
Prabhakar Kushwaha8c618dd2013-12-26 12:40:55 +0530211#define QIXIS_RST_FORCE_MEM 0x01
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530212
213#define CONFIG_SYS_CSPR3_EXT (0xf)
214#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
215 | CSPR_PORT_SIZE_8 \
216 | CSPR_MSEL_GPCM \
217 | CSPR_V)
Rajesh Bhagat088d52c2018-11-05 18:01:19 +0000218#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530219#define CONFIG_SYS_CSOR3 0x0
220/* QIXIS Timing parameters for IFC CS3 */
221#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
222 FTIM0_GPCM_TEADC(0x0e) | \
223 FTIM0_GPCM_TEAHC(0x0e))
224#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
225 FTIM1_GPCM_TRAD(0x3f))
226#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
Prabhakar Kushwaha562de1d2013-12-12 12:09:01 +0530227 FTIM2_GPCM_TCH(0x8) | \
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530228 FTIM2_GPCM_TWP(0x1f))
229#define CONFIG_SYS_CS3_FTIM3 0x0
230
231#define CONFIG_NAND_FSL_IFC
232#define CONFIG_SYS_NAND_BASE 0xff800000
233#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
234
235#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
236#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
237 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
238 | CSPR_MSEL_NAND /* MSEL = NAND */ \
239 | CSPR_V)
240#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
241
242#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
243 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
244 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
245 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
246 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
247 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
248 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
249
250#define CONFIG_SYS_NAND_ONFI_DETECTION
251
252/* ONFI NAND Flash mode0 Timing Params */
253#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
254 FTIM0_NAND_TWP(0x18) | \
255 FTIM0_NAND_TWCHT(0x07) | \
256 FTIM0_NAND_TWH(0x0a))
257#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
258 FTIM1_NAND_TWBE(0x39) | \
259 FTIM1_NAND_TRR(0x0e) | \
260 FTIM1_NAND_TRP(0x18))
261#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
262 FTIM2_NAND_TREH(0x0a) | \
263 FTIM2_NAND_TWHRE(0x1e))
264#define CONFIG_SYS_NAND_FTIM3 0x0
265
266#define CONFIG_SYS_NAND_DDR_LAW 11
267#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
268#define CONFIG_SYS_MAX_NAND_DEVICE 1
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530269
270#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
271
272#if defined(CONFIG_NAND)
273#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
274#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
275#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
276#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
277#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
278#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
279#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
280#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
281#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
282#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
283#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
284#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
285#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
286#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
287#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
288#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
289#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
290#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
291#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
292#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
293#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
294#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
295#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
296#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
297#else
298#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
299#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
300#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
301#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
302#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
303#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
304#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
305#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
306#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
307#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
308#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
309#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
310#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
311#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
312#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
313#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
314#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
315#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
316#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
317#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
318#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
319#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
320#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
321#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
322#endif
323
324#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
325
326#if defined(CONFIG_RAMBOOT_PBL)
327#define CONFIG_SYS_RAMBOOT
328#endif
329
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530330#define CONFIG_HWCONFIG
331
332/* define to use L1 as initial stack */
333#define CONFIG_L1_INIT_RAM
334#define CONFIG_SYS_INIT_RAM_LOCK
335#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
336#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
York Sunb3142e22015-08-17 13:31:51 -0700337#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530338/* The assembler doesn't like typecast */
339#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
340 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
341 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
342#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
343
344#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
345 GENERATED_GBL_DATA_SIZE)
346#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
347
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530348#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Priyanka Jain337b0c52014-02-26 16:11:53 +0530349#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530350
351/* Serial Port - controlled on board with jumper J8
352 * open - index 2
353 * shorted - index 1
354 */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530355#define CONFIG_SYS_NS16550_SERIAL
356#define CONFIG_SYS_NS16550_REG_SIZE 1
357#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
358
359#define CONFIG_SYS_BAUDRATE_TABLE \
360 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
361
362#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
363#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
364#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
365#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530366
Priyanka Jain337b0c52014-02-26 16:11:53 +0530367/* Video */
368#define CONFIG_FSL_DIU_FB
369#ifdef CONFIG_FSL_DIU_FB
Wang Dongshengc53711b2014-03-19 10:47:55 +0800370#define CONFIG_FSL_DIU_CH7301
Priyanka Jain337b0c52014-02-26 16:11:53 +0530371#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
Priyanka Jain337b0c52014-02-26 16:11:53 +0530372#define CONFIG_VIDEO_LOGO
373#define CONFIG_VIDEO_BMP_LOGO
374#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
375/*
376 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
377 * disable empty flash sector detection, which is I/O-intensive.
378 */
379#undef CONFIG_SYS_FLASH_EMPTY_INFO
380#endif
381
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530382/* I2C */
383#define CONFIG_SYS_I2C
384#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
Priyanka Jain2eb3ac72014-01-03 11:24:55 +0530385#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
Shengzhou Liub0d97cd2014-07-07 12:17:47 +0800386#define CONFIG_SYS_FSL_I2C2_SPEED 50000
387#define CONFIG_SYS_FSL_I2C3_SPEED 50000
388#define CONFIG_SYS_FSL_I2C4_SPEED 50000
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530389#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530390#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
Shengzhou Liub0d97cd2014-07-07 12:17:47 +0800391#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
392#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530393#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
Shengzhou Liub0d97cd2014-07-07 12:17:47 +0800394#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
395#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
396#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530397
398#define I2C_MUX_PCA_ADDR 0x77
399#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
400
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530401/* I2C bus multiplexer */
402#define I2C_MUX_CH_DEFAULT 0x8
Priyanka Jain337b0c52014-02-26 16:11:53 +0530403#define I2C_MUX_CH_DIU 0xC
404
405/* LDI/DVI Encoder for display */
406#define CONFIG_SYS_I2C_LDI_ADDR 0x38
407#define CONFIG_SYS_I2C_DVI_ADDR 0x75
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530408
409/*
410 * RTC configuration
411 */
412#define RTC
413#define CONFIG_RTC_DS3231 1
414#define CONFIG_SYS_I2C_RTC_ADDR 0x68
415
416/*
417 * eSPI - Enhanced SPI
418 */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530419#define CONFIG_SF_DEFAULT_SPEED 10000000
420#define CONFIG_SF_DEFAULT_MODE 0
421
422/*
423 * General PCI
424 * Memory space is mapped 1-1, but I/O space must start from 0.
425 */
426
427#ifdef CONFIG_PCI
428/* controller 1, direct to uli, tgtid 3, Base address 20000 */
429#ifdef CONFIG_PCIE1
430#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
431#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
432#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
433#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
434#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
435#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
436#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
437#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
438#endif
439
440/* controller 2, Slot 2, tgtid 2, Base address 201000 */
441#ifdef CONFIG_PCIE2
442#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
443#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
444#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
445#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
446#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
447#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
448#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
449#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
450#endif
451
452/* controller 3, Slot 1, tgtid 1, Base address 202000 */
453#ifdef CONFIG_PCIE3
454#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
455#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
456#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
457#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
458#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
459#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
460#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
461#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
462#endif
463
464/* controller 4, Base address 203000 */
465#ifdef CONFIG_PCIE4
466#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
467#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
468#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
469#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
470#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
471#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
472#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
473#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
474#endif
475
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530476#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530477#endif /* CONFIG_PCI */
478
479/* SATA */
480#define CONFIG_FSL_SATA_V2
481#ifdef CONFIG_FSL_SATA_V2
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530482#define CONFIG_SYS_SATA_MAX_DEVICE 2
483#define CONFIG_SATA1
484#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
485#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
486#define CONFIG_SATA2
487#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
488#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
489
490#define CONFIG_LBA48
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530491#endif
492
493/*
494* USB
495*/
496#define CONFIG_HAS_FSL_DR_USB
497
498#ifdef CONFIG_HAS_FSL_DR_USB
Tom Rini8850c5d2017-05-12 22:33:27 -0400499#ifdef CONFIG_USB_EHCI_HCD
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530500#define CONFIG_USB_EHCI_FSL
501#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530502#endif
503#endif
504
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530505#ifdef CONFIG_MMC
Yangbo Lu12486f32015-09-17 10:27:38 +0800506#define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530507#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
Yangbo Lufa1e0352015-09-17 10:27:27 +0800508#define CONFIG_FSL_ESDHC_ADAPTER_IDENT
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530509#endif
510
511/* Qman/Bman */
512#ifndef CONFIG_NOBQFMAN
Jeffrey Ladouceur2a8b3422014-12-03 18:08:43 -0500513#define CONFIG_SYS_BMAN_NUM_PORTALS 10
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530514#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
515#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
516#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500517#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
518#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
519#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
520#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
521#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
522 CONFIG_SYS_BMAN_CENA_SIZE)
523#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
524#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
Jeffrey Ladouceur2a8b3422014-12-03 18:08:43 -0500525#define CONFIG_SYS_QMAN_NUM_PORTALS 10
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530526#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
527#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
528#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500529#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
530#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
531#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
532#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
533#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
534 CONFIG_SYS_QMAN_CENA_SIZE)
535#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
536#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530537
538#define CONFIG_SYS_DPAA_FMAN
539#define CONFIG_SYS_DPAA_PME
540
Zhao Qiang6259e292014-03-21 16:21:46 +0800541#define CONFIG_QE
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530542/* Default address of microcode for the Linux Fman driver */
543#if defined(CONFIG_SPIFLASH)
544/*
545 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
546 * env, so we got 0x110000.
547 */
548#define CONFIG_SYS_QE_FW_IN_SPIFLASH
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800549#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530550#elif defined(CONFIG_SDCARD)
551/*
552 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530553 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
554 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530555 */
556#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800557#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530558#elif defined(CONFIG_NAND)
559#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800560#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530561#else
562#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800563#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
Zhao Qiang6259e292014-03-21 16:21:46 +0800564#define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530565#endif
566#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
567#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
568#endif /* CONFIG_NOBQFMAN */
569
570#ifdef CONFIG_SYS_DPAA_FMAN
571#define CONFIG_FMAN_ENET
572#define CONFIG_PHYLIB_10G
573#define CONFIG_PHY_VITESSE
574#define CONFIG_PHY_REALTEK
575#define CONFIG_PHY_TERANETICS
576#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
577#define SGMII_CARD_PORT2_PHY_ADDR 0x10
578#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
579#define SGMII_CARD_PORT4_PHY_ADDR 0x11
580#endif
581
582#ifdef CONFIG_FMAN_ENET
Prabhakar Kushwaha5b7672f2014-01-27 15:55:20 +0530583#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01
584#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530585
586#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
587#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
588#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
589#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
590
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530591#define CONFIG_ETHPRIME "FM1@DTSEC1"
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530592#endif
593
Codrin Ciubotariua83fccc2015-01-21 11:54:11 +0200594/* Enable VSC9953 L2 Switch driver */
595#define CONFIG_VSC9953
Codrin Ciubotariua83fccc2015-01-21 11:54:11 +0200596#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14
597#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18
598
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530599/*
Prabhakar Kushwaha68b74732014-04-02 17:26:23 +0530600 * Dynamic MTD Partition support with mtdparts
601 */
Prabhakar Kushwaha68b74732014-04-02 17:26:23 +0530602
603/*
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530604 * Environment
605 */
606#define CONFIG_LOADS_ECHO /* echo on for serial download */
607#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
608
609/*
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530610 * Miscellaneous configurable options
611 */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530612#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530613
614/*
615 * For booting Linux, the board info and command line data
616 * have to be in the first 64 MB of memory, since this is
617 * the maximum mapped by the Linux kernel during initialization.
618 */
619#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
620#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
621
622#ifdef CONFIG_CMD_KGDB
623#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530624#endif
625
626/*
627 * Environment Configuration
628 */
629#define CONFIG_ROOTPATH "/opt/nfsroot"
630#define CONFIG_BOOTFILE "uImage"
631#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
632
633/* default location for tftp and bootm */
634#define CONFIG_LOADADDR 1000000
635
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530636#define __USB_PHY_TYPE utmi
637
638#define CONFIG_EXTRA_ENV_SETTINGS \
York Sun1b2af9b2014-10-27 11:45:11 -0700639 "hwconfig=fsl_ddr:bank_intlv=auto;" \
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530640 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
641 "netdev=eth0\0" \
Priyanka Jain337b0c52014-02-26 16:11:53 +0530642 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530643 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
644 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
645 "tftpflash=tftpboot $loadaddr $uboot && " \
646 "protect off $ubootaddr +$filesize && " \
647 "erase $ubootaddr +$filesize && " \
648 "cp.b $loadaddr $ubootaddr $filesize && " \
649 "protect on $ubootaddr +$filesize && " \
650 "cmp.b $loadaddr $ubootaddr $filesize\0" \
651 "consoledev=ttyS0\0" \
652 "ramdiskaddr=2000000\0" \
653 "ramdiskfile=t1040qds/ramdisk.uboot\0" \
Scott Woodb24a4f62016-07-19 17:52:06 -0500654 "fdtaddr=1e00000\0" \
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530655 "fdtfile=t1040qds/t1040qds.dtb\0" \
Kim Phillips32465842014-05-14 19:33:45 -0500656 "bdev=sda3\0"
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530657
658#define CONFIG_LINUX \
659 "setenv bootargs root=/dev/ram rw " \
660 "console=$consoledev,$baudrate $othbootargs;" \
661 "setenv ramdiskaddr 0x02000000;" \
662 "setenv fdtaddr 0x00c00000;" \
663 "setenv loadaddr 0x1000000;" \
664 "bootm $loadaddr $ramdiskaddr $fdtaddr"
665
666#define CONFIG_HDBOOT \
667 "setenv bootargs root=/dev/$bdev rw " \
668 "console=$consoledev,$baudrate $othbootargs;" \
669 "tftp $loadaddr $bootfile;" \
670 "tftp $fdtaddr $fdtfile;" \
671 "bootm $loadaddr - $fdtaddr"
672
673#define CONFIG_NFSBOOTCOMMAND \
674 "setenv bootargs root=/dev/nfs rw " \
675 "nfsroot=$serverip:$rootpath " \
676 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
677 "console=$consoledev,$baudrate $othbootargs;" \
678 "tftp $loadaddr $bootfile;" \
679 "tftp $fdtaddr $fdtfile;" \
680 "bootm $loadaddr - $fdtaddr"
681
682#define CONFIG_RAMBOOTCOMMAND \
683 "setenv bootargs root=/dev/ram rw " \
684 "console=$consoledev,$baudrate $othbootargs;" \
685 "tftp $ramdiskaddr $ramdiskfile;" \
686 "tftp $loadaddr $bootfile;" \
687 "tftp $fdtaddr $fdtfile;" \
688 "bootm $loadaddr $ramdiskaddr $fdtaddr"
689
690#define CONFIG_BOOTCOMMAND CONFIG_LINUX
691
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530692#include <asm/fsl_secure_boot.h>
Aneesh Bansalef6c55a2016-01-22 16:37:22 +0530693
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530694#endif /* __CONFIG_H */