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Andreas Bießmannad7a1782011-06-30 22:03:20 +00001/*
2 * Copyright (C) 2011
3 * Corscience GmbH & Co.KG, Andreas Bießmann <biessmann@corscience.de>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Andreas Bießmannad7a1782011-06-30 22:03:20 +00006 */
7#include <common.h>
8
9#include <asm/io.h>
10#include <asm/sdram.h>
11#include <asm/arch/clk.h>
12#include <asm/arch/hmatrix.h>
13#include <asm/arch/mmu.h>
14#include <asm/arch/portmux.h>
15#include <netdev.h>
16
17DECLARE_GLOBAL_DATA_PTR;
18
19struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
20 {
Andreas Bießmanne9ed41c2015-02-06 23:06:42 +010021 .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
22 .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
23 .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
Andreas Bießmannad7a1782011-06-30 22:03:20 +000024 | MMU_VMR_CACHE_NONE,
25 }, {
Andreas Bießmanne9ed41c2015-02-06 23:06:42 +010026 .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
27 .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
28 .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
Andreas Bießmannad7a1782011-06-30 22:03:20 +000029 | MMU_VMR_CACHE_WRBACK,
30 },
31};
32
33static const struct sdram_config sdram_config = {
34 /* Dual MT48LC16M16A2-7E (or equal) */
35 .data_bits = SDRAM_DATA_32BIT,
36 .row_bits = 13,
37 .col_bits = 9,
38 .bank_bits = 2,
39 .cas = 2,
40 .twr = 2,
41 .trc = 7,
42 .trp = 2,
43 .trcd = 2,
44 .tras = 4,
45 .txsr = 7,
46 /* 7.81 us */
47 .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
48};
49
50int board_early_init_f(void)
51{
52 /* Enable SDRAM in the EBI mux */
53 hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
54
55 portmux_enable_ebi(SDRAM_DATA_32BIT, 23, 0, PORTMUX_DRIVE_HIGH);
56 portmux_enable_usart0(PORTMUX_DRIVE_MIN);
57 portmux_enable_usart1(PORTMUX_DRIVE_MIN);
58#if defined(CONFIG_MACB)
Andreas Bießmanneba00ab2012-05-25 12:29:32 +020059 /* set PHY reset and pwrdown to low */
60 portmux_select_gpio(PORTMUX_PORT_B, (1 << 29) | (1 << 30),
61 PORTMUX_DIR_OUTPUT | PORTMUX_INIT_LOW);
62 udelay(100);
63 /* release PHYs reset */
64 gpio_set_value(GPIO_PIN_PB(29), 1);
65
Andreas Bießmannad7a1782011-06-30 22:03:20 +000066 portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_LOW);
67#endif
68
69 return 0;
70}
71
72phys_size_t initdram(int board_type)
73{
74 unsigned long expected_size;
75 unsigned long actual_size;
76 void *sdram_base;
77
78 sdram_base = uncached(EBI_SDRAM_BASE);
79
80 expected_size = sdram_init(sdram_base, &sdram_config);
81 actual_size = get_ram_size(sdram_base, expected_size);
82
83 if (expected_size != actual_size)
84 printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
85 actual_size >> 20, expected_size >> 20);
86
87 return actual_size;
88}
89
90int board_early_init_r(void)
91{
92 gd->bd->bi_phy_id[0] = 0x00;
93 return 0;
94}
95
96#ifdef CONFIG_CMD_NET
97int board_eth_init(bd_t *bi)
98{
99 macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
100 return 0;
101}
102#endif
103/* vim: set noet ts=8: */