blob: e9363ea394823a24b6d4cf9f8007d160f73b7e7d [file] [log] [blame]
wdenk56523f12004-07-11 17:40:54 +00001/*
Wolfgang Denk45a212c2006-07-19 17:52:30 +02002 * (C) Copyright 2003-2006
wdenk56523f12004-07-11 17:40:54 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2004
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
7 *
Wolfgang Denk45a212c2006-07-19 17:52:30 +02008 * (C) Copyright 2004-2006
wdenk56523f12004-07-11 17:40:54 +00009 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
10 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020011 * SPDX-License-Identifier: GPL-2.0+
wdenk56523f12004-07-11 17:40:54 +000012 */
13
14#include <common.h>
15#include <mpc5xxx.h>
16#include <pci.h>
Wolfgang Denk45a212c2006-07-19 17:52:30 +020017#include <asm/processor.h>
Grant Likelycf2817a2007-09-06 09:46:23 -060018#include <libfdt.h>
Ben Warren19403632008-08-31 10:03:22 -070019#include <netdev.h>
Bartlomiej Sieka8f8416f2007-06-08 14:52:22 +020020
wdenk8f0b7cb2005-03-27 23:41:39 +000021#ifdef CONFIG_VIDEO_SM501
22#include <sm501.h>
23#endif
24
wdenk56523f12004-07-11 17:40:54 +000025#if defined(CONFIG_MPC5200_DDR)
26#include "mt46v16m16-75.h"
27#else
28#include "mt48lc16m16a2-75.h"
29#endif
wdenk8f0b7cb2005-03-27 23:41:39 +000030
Martin Krausec313b2c2008-02-25 17:52:40 +010031#ifdef CONFIG_OF_LIBFDT
32#include <fdt_support.h>
33#endif /* CONFIG_OF_LIBFDT */
34
Wolfgang Denk1218abf2007-09-15 20:48:41 +020035DECLARE_GLOBAL_DATA_PTR;
36
wdenk7e6bf352004-12-12 22:06:17 +000037#ifdef CONFIG_PS2MULT
38void ps2mult_early_init(void);
39#endif
wdenk56523f12004-07-11 17:40:54 +000040
Wolfgang Denk42df1e12010-12-23 19:57:31 +010041#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) && \
42 defined(CONFIG_VIDEO)
Heiko Schocher98e69562010-12-04 08:34:04 +010043/*
44 * EDID block has been generated using Phoenix EDID Designer 1.3.
45 * This tool creates a text file containing:
46 *
47 * EDID BYTES:
48 *
49 * 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
50 * ------------------------------------------------
51 * 00 | 00 FF FF FF FF FF FF 00 04 21 00 00 00 00 00 00
52 * 10 | 01 00 01 03 00 00 00 00 00 00 00 00 00 00 00 00
53 * 20 | 00 00 00 21 00 00 01 01 01 01 01 01 01 01 01 01
54 * 30 | 01 01 01 01 01 01 64 00 00 00 00 00 00 00 00 00
55 * 40 | 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 00
56 * 50 | 00 00 00 00 00 00 00 00 00 00 00 00 00 10 00 00
57 * 60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10
58 * 70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 17
59 *
60 * Then this data has been manually converted to the char
61 * array below.
62 */
63static unsigned char edid_buf[128] = {
64 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
65 0x04, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
66 0x01, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00,
67 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
68 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x01, 0x01,
69 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
70 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x64, 0x00,
71 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
72 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
73 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00,
74 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
75 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
76 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
77 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
78 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
79 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x17,
80};
81#endif
82
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083#ifndef CONFIG_SYS_RAMBOOT
wdenk56523f12004-07-11 17:40:54 +000084static void sdram_start (int hi_addr)
85{
86 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
87
88 /* unlock mode register */
89 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
90 hi_addr_bit;
91 __asm__ volatile ("sync");
92
93 /* precharge all banks */
94 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
95 hi_addr_bit;
96 __asm__ volatile ("sync");
97
98#if SDRAM_DDR
99 /* set mode register: extended mode */
100 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
101 __asm__ volatile ("sync");
102
103 /* set mode register: reset DLL */
104 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
105 __asm__ volatile ("sync");
106#endif
107
108 /* precharge all banks */
109 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
110 hi_addr_bit;
111 __asm__ volatile ("sync");
112
113 /* auto refresh */
114 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
115 hi_addr_bit;
116 __asm__ volatile ("sync");
117
118 /* set mode register */
119 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
120 __asm__ volatile ("sync");
121
122 /* normal operation */
123 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
124 __asm__ volatile ("sync");
125}
126#endif
127
128/*
129 * ATTENTION: Although partially referenced initdram does NOT make real use
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
wdenk81050922004-07-11 20:04:51 +0000131 * is something else than 0x00000000.
wdenk56523f12004-07-11 17:40:54 +0000132 */
133
Becky Bruce9973e3c2008-06-09 16:03:40 -0500134phys_size_t initdram (int board_type)
wdenk56523f12004-07-11 17:40:54 +0000135{
136 ulong dramsize = 0;
137 ulong dramsize2 = 0;
Wolfgang Denk45a212c2006-07-19 17:52:30 +0200138 uint svr, pvr;
139
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#ifndef CONFIG_SYS_RAMBOOT
wdenk56523f12004-07-11 17:40:54 +0000141 ulong test1, test2;
142
143 /* setup SDRAM chip selects */
144 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
145 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
146 __asm__ volatile ("sync");
147
148 /* setup config registers */
149 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
150 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
151 __asm__ volatile ("sync");
152
153#if SDRAM_DDR
154 /* set tap delay */
155 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
156 __asm__ volatile ("sync");
157#endif
158
159 /* find RAM size using SDRAM CS0 only */
160 sdram_start(0);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
wdenk56523f12004-07-11 17:40:54 +0000162 sdram_start(1);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
wdenk56523f12004-07-11 17:40:54 +0000164 if (test1 > test2) {
165 sdram_start(0);
166 dramsize = test1;
167 } else {
168 dramsize = test2;
169 }
170
171 /* memory smaller than 1MB is impossible */
172 if (dramsize < (1 << 20)) {
173 dramsize = 0;
174 }
175
176 /* set SDRAM CS0 size according to the amount of RAM found */
177 if (dramsize > 0) {
178 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
179 __builtin_ffs(dramsize >> 20) - 1;
180 } else {
181 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
182 }
183
184 /* let SDRAM CS1 start right after CS0 */
185 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
186
187 /* find RAM size using SDRAM CS1 only */
Martin Krausef3a329a2008-02-25 13:27:52 +0100188 if (!dramsize)
189 sdram_start(0);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190 test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
Martin Krausef3a329a2008-02-25 13:27:52 +0100191 if (!dramsize) {
192 sdram_start(1);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193 test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
Martin Krausef3a329a2008-02-25 13:27:52 +0100194 }
wdenk56523f12004-07-11 17:40:54 +0000195 if (test1 > test2) {
196 sdram_start(0);
197 dramsize2 = test1;
198 } else {
199 dramsize2 = test2;
200 }
201
202 /* memory smaller than 1MB is impossible */
203 if (dramsize2 < (1 << 20)) {
204 dramsize2 = 0;
205 }
206
207 /* set SDRAM CS1 size according to the amount of RAM found */
208 if (dramsize2 > 0) {
209 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
210 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
211 } else {
212 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
213 }
214
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#else /* CONFIG_SYS_RAMBOOT */
wdenk56523f12004-07-11 17:40:54 +0000216
217 /* retrieve size of memory connected to SDRAM CS0 */
218 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
219 if (dramsize >= 0x13) {
220 dramsize = (1 << (dramsize - 0x13)) << 20;
221 } else {
222 dramsize = 0;
223 }
224
225 /* retrieve size of memory connected to SDRAM CS1 */
226 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
227 if (dramsize2 >= 0x13) {
228 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
229 } else {
230 dramsize2 = 0;
231 }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#endif /* CONFIG_SYS_RAMBOOT */
wdenk56523f12004-07-11 17:40:54 +0000233
Wolfgang Denk45a212c2006-07-19 17:52:30 +0200234 /*
235 * On MPC5200B we need to set the special configuration delay in the
236 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
237 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
238 *
239 * "The SDelay should be written to a value of 0x00000004. It is
240 * required to account for changes caused by normal wafer processing
241 * parameters."
242 */
243 svr = get_svr();
244 pvr = get_pvr();
245 if ((SVR_MJREV(svr) >= 2) &&
246 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
247
248 *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
249 __asm__ volatile ("sync");
250 }
251
252#if defined(CONFIG_TQM5200_B)
253 return dramsize + dramsize2;
254#else
wdenk56523f12004-07-11 17:40:54 +0000255 return dramsize;
Wolfgang Denk45a212c2006-07-19 17:52:30 +0200256#endif /* CONFIG_TQM5200_B */
wdenk56523f12004-07-11 17:40:54 +0000257}
258
wdenk56523f12004-07-11 17:40:54 +0000259int checkboard (void)
260{
Wolfgang Denk5078cce2006-07-21 11:16:34 +0200261#if defined(CONFIG_AEVFIFO)
Wolfgang Denk8f79e4c2005-08-10 15:14:32 +0200262 puts ("Board: AEVFIFO\n");
263 return 0;
264#endif
Wolfgang Denk5078cce2006-07-21 11:16:34 +0200265
266#if defined(CONFIG_TQM5200S)
267# define MODULE_NAME "TQM5200S"
Wolfgang Denk45a212c2006-07-19 17:52:30 +0200268#else
Wolfgang Denk5078cce2006-07-21 11:16:34 +0200269# define MODULE_NAME "TQM5200"
wdenk56523f12004-07-11 17:40:54 +0000270#endif
Wolfgang Denk5078cce2006-07-21 11:16:34 +0200271
272#if defined(CONFIG_STK52XX)
273# define CARRIER_NAME "STK52xx"
274#elif defined(CONFIG_TB5200)
275# define CARRIER_NAME "TB5200"
Wolfgang Denk135ae002006-07-22 01:20:03 +0200276#elif defined(CONFIG_CAM5200)
Wolfgang Denk78d620e2006-11-23 22:58:58 +0100277# define CARRIER_NAME "CAM5200"
Marian Balakowicz6d3bc9b2006-08-18 19:14:46 +0200278#elif defined(CONFIG_FO300)
279# define CARRIER_NAME "FO300"
Heiko Schocher98e69562010-12-04 08:34:04 +0100280#elif defined(CONFIG_CHARON)
281# define CARRIER_NAME "CHARON"
Wolfgang Denk5078cce2006-07-21 11:16:34 +0200282#else
Wolfgang Denk5196a7a2006-08-18 23:27:33 +0200283# error "UNKNOWN"
wdenk7e6bf352004-12-12 22:06:17 +0000284#endif
Wolfgang Denk5078cce2006-07-21 11:16:34 +0200285
286 puts ( "Board: " MODULE_NAME " (TQ-Components GmbH)\n"
287 " on a " CARRIER_NAME " carrier board\n");
wdenk7e6bf352004-12-12 22:06:17 +0000288
wdenk56523f12004-07-11 17:40:54 +0000289 return 0;
290}
291
Wolfgang Denk5078cce2006-07-21 11:16:34 +0200292#undef MODULE_NAME
293#undef CARRIER_NAME
294
wdenk56523f12004-07-11 17:40:54 +0000295void flash_preinit(void)
296{
297 /*
298 * Now, when we are in RAM, enable flash write
299 * access for detection process.
300 * Note that CS_BOOT cannot be cleared when
301 * executing in flash.
302 */
wdenk56523f12004-07-11 17:40:54 +0000303 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
304}
305
306
307#ifdef CONFIG_PCI
308static struct pci_controller hose;
309
310extern void pci_mpc5xxx_init(struct pci_controller *);
311
312void pci_init_board(void)
313{
314 pci_mpc5xxx_init(&hose);
315}
316#endif
317
Jon Loeligerd39b5742007-07-10 10:48:22 -0500318#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
wdenk56523f12004-07-11 17:40:54 +0000319
320#if defined (CONFIG_MINIFAP)
321#define SM501_POWER_MODE0_GATE 0x00000040UL
322#define SM501_POWER_MODE1_GATE 0x00000048UL
323#define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL
324#define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL
325#define SM501_GPIO_DATA_HIGH 0x00010004UL
326#define SM501_GPIO_51 0x00080000UL
Bartlomiej Siekadae80f32006-11-01 01:38:16 +0100327#endif /* CONFIG MINIFAP */
wdenk56523f12004-07-11 17:40:54 +0000328
329void init_ide_reset (void)
330{
331 debug ("init_ide_reset\n");
332
333#if defined (CONFIG_MINIFAP)
334 /* Configure GPIO_51 of the SM501 grafic controller as ATA reset */
335
336 /* enable GPIO control (in both power modes) */
337 *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |=
338 POWER_MODE_GATE_GPIO_PWM_I2C;
339 *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |=
340 POWER_MODE_GATE_GPIO_PWM_I2C;
341 /* configure GPIO51 as output */
342 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |=
343 SM501_GPIO_51;
344#else
345 /* Configure PSC1_4 as GPIO output for ATA reset */
346 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
347 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
Martin Krause8f2a68a2008-04-03 14:29:01 +0200348
349 /* by default the ATA reset is de-asserted */
350 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
wdenk56523f12004-07-11 17:40:54 +0000351#endif
352}
353
354void ide_set_reset (int idereset)
355{
356 debug ("ide_reset(%d)\n", idereset);
357
358#if defined (CONFIG_MINIFAP)
359 if (idereset) {
360 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
361 ~SM501_GPIO_51;
362 } else {
363 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
364 SM501_GPIO_51;
365 }
366#else
367 if (idereset) {
Bartlomiej Siekadae80f32006-11-01 01:38:16 +0100368 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
wdenk56523f12004-07-11 17:40:54 +0000369 } else {
Bartlomiej Siekadae80f32006-11-01 01:38:16 +0100370 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
wdenk56523f12004-07-11 17:40:54 +0000371 }
372#endif
373}
Jon Loeligerd39b5742007-07-10 10:48:22 -0500374#endif
wdenk56523f12004-07-11 17:40:54 +0000375
376#ifdef CONFIG_POST
377/*
378 * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
379 * is left open, no keypress is detected.
380 */
381int post_hotkeys_pressed(void)
382{
Wolfgang Denk1d92b2e2006-10-09 01:07:53 +0200383#ifdef CONFIG_STK52XX
wdenk56523f12004-07-11 17:40:54 +0000384 struct mpc5xxx_gpio *gpio;
385
386 gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
387
388 /*
Detlev Zundel95c44ec2009-10-07 16:38:05 +0200389 * Configure PSC6_0 through PSC6_3 as GPIO.
wdenk81050922004-07-11 20:04:51 +0000390 */
Detlev Zundel95c44ec2009-10-07 16:38:05 +0200391 gpio->port_config &= ~(0x00700000);
wdenk56523f12004-07-11 17:40:54 +0000392
393 /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
394 gpio->simple_gpioe |= 0x20000000;
395
396 /* Configure GPIO_IRDA_1 as input */
397 gpio->simple_ddr &= ~(0x20000000);
398
399 return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
Wolfgang Denk1d92b2e2006-10-09 01:07:53 +0200400#else
401 return 0;
402#endif
wdenk56523f12004-07-11 17:40:54 +0000403}
404#endif
405
wdenk7e6bf352004-12-12 22:06:17 +0000406#ifdef CONFIG_BOARD_EARLY_INIT_R
407int board_early_init_r (void)
408{
Markus Klotzbuecher6a40ef62008-01-09 13:57:10 +0100409
Wolfgang Denk409ecdc2007-11-18 16:36:27 +0100410 extern int usb_cpu_init(void);
411
Marian Balakowicz245a3622007-10-24 01:37:36 +0200412#ifdef CONFIG_PS2MULT
wdenk7e6bf352004-12-12 22:06:17 +0000413 ps2mult_early_init();
Marian Balakowicz245a3622007-10-24 01:37:36 +0200414#endif /* CONFIG_PS2MULT */
415
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
Marian Balakowicz245a3622007-10-24 01:37:36 +0200417 /* Low level USB init, required for proper kernel operation */
418 usb_cpu_init();
419#endif
420
wdenk7e6bf352004-12-12 22:06:17 +0000421 return (0);
422}
423#endif
wdenk7e6bf352004-12-12 22:06:17 +0000424
Wolfgang Denkaeec7822006-09-13 10:47:05 +0200425#ifdef CONFIG_FO300
426int silent_boot (void)
427{
428 vu_long timer3_status;
429
430 /* Configure GPT3 as GPIO input */
431 *(vu_long *)MPC5XXX_GPT3_ENABLE = 0x00000004;
432
433 /* Read in TIMER_3 pin status */
434 timer3_status = *(vu_long *)MPC5XXX_GPT3_STATUS;
435
436#ifdef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED
437 /* Force silent console mode if S1 switch
438 * is in closed position (TIMER_3 pin status is LOW). */
439 if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 0)
440 return 1;
441#else
442 /* Force silent console mode if S1 switch
443 * is in open position (TIMER_3 pin status is HIGH). */
444 if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 1)
445 return 1;
446#endif
447
448 return 0;
449}
450
451int board_early_init_f (void)
452{
Wolfgang Denkaeec7822006-09-13 10:47:05 +0200453 if (silent_boot())
454 gd->flags |= GD_FLG_SILENT;
455
456 return 0;
457}
458#endif /* CONFIG_FO300 */
459
Heiko Schocher98e69562010-12-04 08:34:04 +0100460#if defined(CONFIG_CHARON)
461#include <i2c.h>
462#include <asm/io.h>
463
464/* The TFP410 registers */
465#define TFP410_REG_VEN_ID_L 0x00
466#define TFP410_REG_VEN_ID_H 0x01
467#define TFP410_REG_DEV_ID_L 0x02
468#define TFP410_REG_DEV_ID_H 0x03
469#define TFP410_REG_REV_ID 0x04
470
471#define TFP410_REG_CTL_1_MODE 0x08
472#define TFP410_REG_CTL_2_MODE 0x09
473#define TFP410_REG_CTL_3_MODE 0x0A
474
475#define TFP410_REG_CFG 0x0B
476
477#define TFP410_REG_DE_DLY 0x32
478#define TFP410_REG_DE_CTL 0x33
479#define TFP410_REG_DE_TOP 0x34
480#define TFP410_REG_DE_CNT_L 0x36
481#define TFP410_REG_DE_CNT_H 0x37
482#define TFP410_REG_DE_LIN_L 0x38
483#define TFP410_REG_DE_LIN_H 0x39
484
485#define TFP410_REG_H_RES_L 0x3A
486#define TFP410_REG_H_RES_H 0x3B
487#define TFP410_REG_V_RES_L 0x3C
488#define TFP410_REG_V_RES_H 0x3D
489
490static int tfp410_read_reg(int reg, uchar *buf)
491{
492 if (i2c_read(CONFIG_SYS_TFP410_ADDR, reg, 1, buf, 1) != 0) {
493 puts ("Error reading the chip.\n");
494 return 1;
495 }
496 return 0;
497}
498
499static int tfp410_write_reg(int reg, uchar buf)
500{
501 if (i2c_write(CONFIG_SYS_TFP410_ADDR, reg, 1, &buf, 1) != 0) {
502 puts ("Error writing the chip.\n");
503 return 1;
504 }
505 return 0;
506}
507
508typedef struct _tfp410_config {
509 int reg;
510 uchar val;
511}TFP410_CONFIG;
512
513static TFP410_CONFIG tfp410_configtbl[] = {
514 {TFP410_REG_CTL_1_MODE, 0x37},
515 {TFP410_REG_CTL_2_MODE, 0x20},
516 {TFP410_REG_CTL_3_MODE, 0x80},
517 {TFP410_REG_DE_DLY, 0x90},
518 {TFP410_REG_DE_CTL, 0x00},
519 {TFP410_REG_DE_TOP, 0x23},
520 {TFP410_REG_DE_CNT_H, 0x02},
521 {TFP410_REG_DE_CNT_L, 0x80},
522 {TFP410_REG_DE_LIN_H, 0x01},
523 {TFP410_REG_DE_LIN_L, 0xe0},
524 {-1, 0},
525};
526
527static int charon_last_stage_init(void)
528{
529 volatile struct mpc5xxx_lpb *lpb =
530 (struct mpc5xxx_lpb *) MPC5XXX_LPB;
531 int oldbus = i2c_get_bus_num();
532 uchar buf;
533 int i = 0;
534
535 i2c_set_bus_num(CONFIG_SYS_TFP410_BUS);
536
537 /* check version */
538 if (tfp410_read_reg(TFP410_REG_DEV_ID_H, &buf) != 0)
539 return -1;
540 if (!(buf & 0x04))
541 return -1;
542 if (tfp410_read_reg(TFP410_REG_DEV_ID_L, &buf) != 0)
543 return -1;
544 if (!(buf & 0x10))
545 return -1;
546 /* OK, now init the chip */
547 while (tfp410_configtbl[i].reg != -1) {
548 int ret;
549
550 ret = tfp410_write_reg(tfp410_configtbl[i].reg,
551 tfp410_configtbl[i].val);
552 if (ret != 0)
553 return -1;
554 i++;
555 }
556 printf("TFP410 initialized.\n");
557 i2c_set_bus_num(oldbus);
558
559 /* set deadcycle for cs3 to 0 */
560 setbits_be32(&lpb->cs_deadcycle, 0xffffcfff);
561 return 0;
562}
563#endif
564
wdenk7e6bf352004-12-12 22:06:17 +0000565int last_stage_init (void)
566{
567 /*
568 * auto scan for really existing devices and re-set chip select
569 * configuration.
570 */
571 u16 save, tmp;
572 int restore;
573
574 /*
575 * Check for SRAM and SRAM size
576 */
577
Wolfgang Denke8aa8242005-08-18 11:55:22 +0200578 /* save original SRAM content */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200579 save = *(volatile u16 *)CONFIG_SYS_CS2_START;
wdenk7e6bf352004-12-12 22:06:17 +0000580 restore = 1;
wdenkefe2a4d2004-12-16 21:44:03 +0000581
wdenk7e6bf352004-12-12 22:06:17 +0000582 /* write test pattern to SRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200583 *(volatile u16 *)CONFIG_SYS_CS2_START = 0xA5A5;
wdenk7e6bf352004-12-12 22:06:17 +0000584 __asm__ volatile ("sync");
585 /*
586 * Put a different pattern on the data lines: otherwise they may float
587 * long enough to read back what we wrote.
588 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200589 tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
wdenk7e6bf352004-12-12 22:06:17 +0000590 if (tmp == 0xA5A5)
591 puts ("!! possible error in SRAM detection\n");
wdenkefe2a4d2004-12-16 21:44:03 +0000592
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200593 if (*(volatile u16 *)CONFIG_SYS_CS2_START != 0xA5A5) {
wdenk7e6bf352004-12-12 22:06:17 +0000594 /* no SRAM at all, disable cs */
595 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
596 *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
597 *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
598 restore = 0;
599 __asm__ volatile ("sync");
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200600 } else if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0xA5A5) {
wdenk7e6bf352004-12-12 22:06:17 +0000601 /* make sure that we access a mirrored address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200602 *(volatile u16 *)CONFIG_SYS_CS2_START = 0x1111;
wdenk7e6bf352004-12-12 22:06:17 +0000603 __asm__ volatile ("sync");
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200604 if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0x1111) {
wdenk7e6bf352004-12-12 22:06:17 +0000605 /* SRAM size = 512 kByte */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200606 *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START,
wdenk7e6bf352004-12-12 22:06:17 +0000607 0x80000);
608 __asm__ volatile ("sync");
609 puts ("SRAM: 512 kB\n");
610 }
611 else
wdenkefe2a4d2004-12-16 21:44:03 +0000612 puts ("!! possible error in SRAM detection\n");
Wolfgang Denke8aa8242005-08-18 11:55:22 +0200613 } else {
wdenkefe2a4d2004-12-16 21:44:03 +0000614 puts ("SRAM: 1 MB\n");
wdenk7e6bf352004-12-12 22:06:17 +0000615 }
616 /* restore origianl SRAM content */
617 if (restore) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200618 *(volatile u16 *)CONFIG_SYS_CS2_START = save;
wdenk7e6bf352004-12-12 22:06:17 +0000619 __asm__ volatile ("sync");
620 }
wdenkefe2a4d2004-12-16 21:44:03 +0000621
Martin Krause0fc0f912007-10-22 16:40:06 +0200622#ifndef CONFIG_TQM5200S /* The TQM5200S has no SM501 grafic controller */
wdenkefe2a4d2004-12-16 21:44:03 +0000623 /*
wdenk7e6bf352004-12-12 22:06:17 +0000624 * Check for Grafic Controller
625 */
626
627 /* save origianl FB content */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200628 save = *(volatile u16 *)CONFIG_SYS_CS1_START;
wdenk7e6bf352004-12-12 22:06:17 +0000629 restore = 1;
wdenkefe2a4d2004-12-16 21:44:03 +0000630
wdenk7e6bf352004-12-12 22:06:17 +0000631 /* write test pattern to FB memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200632 *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
wdenk7e6bf352004-12-12 22:06:17 +0000633 __asm__ volatile ("sync");
634 /*
635 * Put a different pattern on the data lines: otherwise they may float
636 * long enough to read back what we wrote.
637 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200638 tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
wdenk7e6bf352004-12-12 22:06:17 +0000639 if (tmp == 0xA5A5)
640 puts ("!! possible error in grafic controller detection\n");
wdenkefe2a4d2004-12-16 21:44:03 +0000641
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200642 if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
wdenk7e6bf352004-12-12 22:06:17 +0000643 /* no grafic controller at all, disable cs */
644 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
645 *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
646 *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
647 restore = 0;
648 __asm__ volatile ("sync");
Wolfgang Denke8aa8242005-08-18 11:55:22 +0200649 } else {
wdenkefe2a4d2004-12-16 21:44:03 +0000650 puts ("VGA: SMI501 (Voyager) with 8 MB\n");
wdenk7e6bf352004-12-12 22:06:17 +0000651 }
652 /* restore origianl FB content */
653 if (restore) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200654 *(volatile u16 *)CONFIG_SYS_CS1_START = save;
wdenk7e6bf352004-12-12 22:06:17 +0000655 __asm__ volatile ("sync");
656 }
wdenkefe2a4d2004-12-16 21:44:03 +0000657
Wolfgang Denkaeec7822006-09-13 10:47:05 +0200658#ifdef CONFIG_FO300
659 if (silent_boot()) {
660 setenv("bootdelay", "0");
661 disable_ctrlc(1);
662 }
663#endif
Wolfgang Denk409ecdc2007-11-18 16:36:27 +0100664#endif /* !CONFIG_TQM5200S */
Wolfgang Denkaeec7822006-09-13 10:47:05 +0200665
Heiko Schocher98e69562010-12-04 08:34:04 +0100666#if defined(CONFIG_CHARON)
667 charon_last_stage_init();
668#endif
wdenk7e6bf352004-12-12 22:06:17 +0000669 return 0;
670}
wdenk8f0b7cb2005-03-27 23:41:39 +0000671
672#ifdef CONFIG_VIDEO_SM501
673
Marian Balakowicz6d3bc9b2006-08-18 19:14:46 +0200674#ifdef CONFIG_FO300
675#define DISPLAY_WIDTH 800
676#else
wdenk8f0b7cb2005-03-27 23:41:39 +0000677#define DISPLAY_WIDTH 640
Marian Balakowicz6d3bc9b2006-08-18 19:14:46 +0200678#endif
wdenk8f0b7cb2005-03-27 23:41:39 +0000679#define DISPLAY_HEIGHT 480
680
681#ifdef CONFIG_VIDEO_SM501_8BPP
682#error CONFIG_VIDEO_SM501_8BPP not supported.
683#endif /* CONFIG_VIDEO_SM501_8BPP */
684
685#ifdef CONFIG_VIDEO_SM501_16BPP
686#error CONFIG_VIDEO_SM501_16BPP not supported.
687#endif /* CONFIG_VIDEO_SM501_16BPP */
688#ifdef CONFIG_VIDEO_SM501_32BPP
689static const SMI_REGS init_regs [] =
690{
691#if 0 /* CRT only */
692 {0x00004, 0x0},
693 {0x00048, 0x00021807},
694 {0x0004C, 0x10090a01},
695 {0x00054, 0x1},
696 {0x00040, 0x00021807},
697 {0x00044, 0x10090a01},
698 {0x00054, 0x0},
699 {0x80200, 0x00010000},
700 {0x80204, 0x0},
701 {0x80208, 0x0A000A00},
702 {0x8020C, 0x02fa027f},
703 {0x80210, 0x004a028b},
704 {0x80214, 0x020c01df},
705 {0x80218, 0x000201e9},
706 {0x80200, 0x00013306},
707#else /* panel + CRT */
Marian Balakowicz6d3bc9b2006-08-18 19:14:46 +0200708#ifdef CONFIG_FO300
709 {0x00004, 0x0},
710 {0x00048, 0x00021807},
711 {0x0004C, 0x301a0a01},
712 {0x00054, 0x1},
713 {0x00040, 0x00021807},
714 {0x00044, 0x091a0a01},
715 {0x00054, 0x0},
716 {0x80000, 0x0f013106},
717 {0x80004, 0xc428bb17},
718 {0x8000C, 0x00000000},
719 {0x80010, 0x0C800C80},
720 {0x80014, 0x03200000},
721 {0x80018, 0x01e00000},
722 {0x8001C, 0x00000000},
723 {0x80020, 0x01e00320},
724 {0x80024, 0x042a031f},
725 {0x80028, 0x0086034a},
726 {0x8002C, 0x020c01df},
727 {0x80030, 0x000201ea},
728 {0x80200, 0x00010000},
729#else
wdenk8f0b7cb2005-03-27 23:41:39 +0000730 {0x00004, 0x0},
731 {0x00048, 0x00021807},
732 {0x0004C, 0x091a0a01},
733 {0x00054, 0x1},
734 {0x00040, 0x00021807},
735 {0x00044, 0x091a0a01},
736 {0x00054, 0x0},
737 {0x80000, 0x0f013106},
738 {0x80004, 0xc428bb17},
739 {0x8000C, 0x00000000},
740 {0x80010, 0x0a000a00},
741 {0x80014, 0x02800000},
742 {0x80018, 0x01e00000},
743 {0x8001C, 0x00000000},
744 {0x80020, 0x01e00280},
745 {0x80024, 0x02fa027f},
746 {0x80028, 0x004a028b},
747 {0x8002C, 0x020c01df},
748 {0x80030, 0x000201e9},
749 {0x80200, 0x00010000},
Marian Balakowicz6d3bc9b2006-08-18 19:14:46 +0200750#endif /* #ifdef CONFIG_FO300 */
wdenk8f0b7cb2005-03-27 23:41:39 +0000751#endif
752 {0, 0}
753};
754#endif /* CONFIG_VIDEO_SM501_32BPP */
755
756#ifdef CONFIG_CONSOLE_EXTRA_INFO
757/*
758 * Return text to be printed besides the logo.
759 */
760void video_get_info_str (int line_number, char *info)
761{
762 if (line_number == 1) {
Wolfgang Denkcd65a3d2006-06-16 16:11:34 +0200763 strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
Heiko Schocher98e69562010-12-04 08:34:04 +0100764#if defined (CONFIG_CHARON) || defined (CONFIG_FO300) || \
765 defined(CONFIG_STK52XX) || defined(CONFIG_TB5200)
wdenk8f0b7cb2005-03-27 23:41:39 +0000766 } else if (line_number == 2) {
Heiko Schocher98e69562010-12-04 08:34:04 +0100767#if defined (CONFIG_CHARON)
768 strcpy (info, " on a CHARON carrier board");
769#endif
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200770#if defined (CONFIG_STK52XX)
Wolfgang Denk5078cce2006-07-21 11:16:34 +0200771 strcpy (info, " on a STK52xx carrier board");
wdenk8f0b7cb2005-03-27 23:41:39 +0000772#endif
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200773#if defined (CONFIG_TB5200)
Wolfgang Denk5078cce2006-07-21 11:16:34 +0200774 strcpy (info, " on a TB5200 carrier board");
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200775#endif
Marian Balakowicz6d3bc9b2006-08-18 19:14:46 +0200776#if defined (CONFIG_FO300)
777 strcpy (info, " on a FO300 carrier board");
778#endif
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200779#endif
wdenk8f0b7cb2005-03-27 23:41:39 +0000780 }
781 else {
782 info [0] = '\0';
783 }
784}
785#endif
786
787/*
Wolfgang Denke8aa8242005-08-18 11:55:22 +0200788 * Returns SM501 register base address. First thing called in the
789 * driver. Checks if SM501 is physically present.
wdenk8f0b7cb2005-03-27 23:41:39 +0000790 */
791unsigned int board_video_init (void)
792{
Wolfgang Denke8aa8242005-08-18 11:55:22 +0200793 u16 save, tmp;
794 int restore, ret;
795
796 /*
797 * Check for Grafic Controller
798 */
799
800 /* save origianl FB content */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200801 save = *(volatile u16 *)CONFIG_SYS_CS1_START;
Wolfgang Denke8aa8242005-08-18 11:55:22 +0200802 restore = 1;
803
804 /* write test pattern to FB memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200805 *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
Wolfgang Denke8aa8242005-08-18 11:55:22 +0200806 __asm__ volatile ("sync");
807 /*
808 * Put a different pattern on the data lines: otherwise they may float
809 * long enough to read back what we wrote.
810 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200811 tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
Wolfgang Denke8aa8242005-08-18 11:55:22 +0200812 if (tmp == 0xA5A5)
813 puts ("!! possible error in grafic controller detection\n");
814
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200815 if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
Wolfgang Denke8aa8242005-08-18 11:55:22 +0200816 /* no grafic controller found */
817 restore = 0;
818 ret = 0;
819 } else {
820 ret = SM501_MMIO_BASE;
821 }
822
823 if (restore) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200824 *(volatile u16 *)CONFIG_SYS_CS1_START = save;
Wolfgang Denke8aa8242005-08-18 11:55:22 +0200825 __asm__ volatile ("sync");
826 }
827 return ret;
wdenk8f0b7cb2005-03-27 23:41:39 +0000828}
829
830/*
831 * Returns SM501 framebuffer address
832 */
833unsigned int board_video_get_fb (void)
834{
835 return SM501_FB_BASE;
836}
837
838/*
839 * Called after initializing the SM501 and before clearing the screen.
840 */
841void board_validate_screen (unsigned int base)
842{
843}
844
845/*
846 * Return a pointer to the initialization sequence.
847 */
848const SMI_REGS *board_get_regs (void)
849{
850 return init_regs;
851}
852
853int board_get_width (void)
854{
855 return DISPLAY_WIDTH;
856}
857
858int board_get_height (void)
859{
860 return DISPLAY_HEIGHT;
861}
862
863#endif /* CONFIG_VIDEO_SM501 */
Bartlomiej Sieka8f8416f2007-06-08 14:52:22 +0200864
Grant Likelycf2817a2007-09-06 09:46:23 -0600865#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
Simon Glasse895a4b2014-10-23 18:58:47 -0600866int ft_board_setup(void *blob, bd_t *bd)
Bartlomiej Sieka8f8416f2007-06-08 14:52:22 +0200867{
868 ft_cpu_setup(blob, bd);
Heiko Schocher98e69562010-12-04 08:34:04 +0100869#if defined(CONFIG_VIDEO)
870 fdt_add_edid(blob, "smi,sm501", edid_buf);
871#endif
Simon Glasse895a4b2014-10-23 18:58:47 -0600872
873 return 0;
Bartlomiej Sieka8f8416f2007-06-08 14:52:22 +0200874}
Grant Likelycf2817a2007-09-06 09:46:23 -0600875#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
Ben Warren19403632008-08-31 10:03:22 -0700876
Heiko Schocher98e69562010-12-04 08:34:04 +0100877#if defined(CONFIG_RESET_PHY_R)
878#include <miiphy.h>
879
880void reset_phy(void)
881{
882 /* init Micrel KSZ8993 PHY */
883 miiphy_write("FEC", CONFIG_PHY_ADDR, 0x01, 0x09);
884}
885#endif
886
Ben Warren19403632008-08-31 10:03:22 -0700887int board_eth_init(bd_t *bis)
888{
Ben Warrene1d74802008-08-31 10:39:12 -0700889 cpu_eth_init(bis); /* Built in FEC comes first */
Ben Warren19403632008-08-31 10:03:22 -0700890 return pci_eth_init(bis);
891}