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Jon Loeliger25d83d72007-04-11 16:51:02 -05001/*
Kumar Gala6525d512010-07-08 22:37:44 -05002 * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
Jon Loeliger25d83d72007-04-11 16:51:02 -05003 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Jon Loeliger25d83d72007-04-11 16:51:02 -05005 */
6
7#include <common.h>
8#include <command.h>
Ed Swarthout837f1ba2007-07-27 01:50:51 -05009#include <pci.h>
Jon Loeliger25d83d72007-04-11 16:51:02 -050010#include <asm/processor.h>
Kumar Gala1167a2f2008-08-26 08:02:30 -050011#include <asm/mmu.h>
Jon Loeliger25d83d72007-04-11 16:51:02 -050012#include <asm/immap_85xx.h>
Kumar Galac8514622009-04-02 13:22:48 -050013#include <asm/fsl_pci.h>
York Sun5614e712013-09-30 09:22:09 -070014#include <fsl_ddr_sdram.h>
Kumar Gala5d27e022010-12-15 04:55:20 -060015#include <asm/fsl_serdes.h>
Kumar Gala56a92702007-08-30 16:18:18 -050016#include <asm/io.h>
Jon Loeliger25d83d72007-04-11 16:51:02 -050017#include <miiphy.h>
Kumar Galaaddce572007-11-26 17:12:24 -060018#include <libfdt.h>
19#include <fdt_support.h>
Andy Fleming063c1262011-04-08 02:10:54 -050020#include <fsl_mdio.h>
Andy Fleming216f2a72008-08-31 16:33:29 -050021#include <tsec.h>
Ben Warren0b252f52008-08-31 21:41:08 -070022#include <netdev.h>
Jon Loeliger25d83d72007-04-11 16:51:02 -050023
Andy Fleming216f2a72008-08-31 16:33:29 -050024#include "../common/sgmii_riser.h"
Jon Loeliger25d83d72007-04-11 16:51:02 -050025
Jon Loeliger25d83d72007-04-11 16:51:02 -050026int checkboard (void)
27{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020028 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Becky Brucef51cdaf2010-06-17 11:37:20 -050029 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020030 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
Kumar Gala6bb5b412009-07-14 22:42:01 -050031 u8 vboot;
32 u8 *pixis_base = (u8 *)PIXIS_BASE;
Jon Loeliger25d83d72007-04-11 16:51:02 -050033
Wolfgang Denk2f152782007-05-05 18:23:11 +020034 if ((uint)&gur->porpllsr != 0xe00e0000) {
Wolfgang Denk9b55a252008-07-11 01:16:00 +020035 printf("immap size error %lx\n",(ulong)&gur->porpllsr);
Jon Loeliger25d83d72007-04-11 16:51:02 -050036 }
Kumar Gala6bb5b412009-07-14 22:42:01 -050037 printf ("Board: MPC8544DS, Sys ID: 0x%02x, "
38 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
39 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
40 in_8(pixis_base + PIXIS_PVER));
41
42 vboot = in_8(pixis_base + PIXIS_VBOOT);
43 if (vboot & PIXIS_VBOOT_FMAP)
44 printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
45 else
46 puts ("Promjet\n");
Jon Loeliger25d83d72007-04-11 16:51:02 -050047
Ed Swarthout837f1ba2007-07-27 01:50:51 -050048 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
49 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
50 ecm->eedr = 0xffffffff; /* Clear ecm errors */
51 ecm->eeer = 0xffffffff; /* Enable ecm errors */
52
Jon Loeliger25d83d72007-04-11 16:51:02 -050053 return 0;
54}
55
Ed Swarthout837f1ba2007-07-27 01:50:51 -050056#ifdef CONFIG_PCI1
57static struct pci_controller pci1_hose;
58#endif
59
Ed Swarthout837f1ba2007-07-27 01:50:51 -050060#ifdef CONFIG_PCIE3
61static struct pci_controller pcie3_hose;
62#endif
63
Kumar Gala645d5a72009-11-04 10:22:26 -060064void pci_init_board(void)
Ed Swarthout837f1ba2007-07-27 01:50:51 -050065{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Kumar Gala64a16862010-12-17 06:01:24 -060067 struct fsl_pci_info pci_info;
Kumar Gala645d5a72009-11-04 10:22:26 -060068 u32 devdisr, pordevsr, io_sel;
69 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
70 int first_free_busno = 0;
Ed Swarthout837f1ba2007-07-27 01:50:51 -050071
Kumar Gala645d5a72009-11-04 10:22:26 -060072 int pcie_ep, pcie_configured;
73
74 devdisr = in_be32(&gur->devdisr);
75 pordevsr = in_be32(&gur->pordevsr);
76 porpllsr = in_be32(&gur->porpllsr);
77 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
78
79 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
Ed Swarthout837f1ba2007-07-27 01:50:51 -050080
Kumar Gala645d5a72009-11-04 10:22:26 -060081 puts("\n");
Ed Swarthout837f1ba2007-07-27 01:50:51 -050082
83#ifdef CONFIG_PCIE3
Kumar Gala5d27e022010-12-15 04:55:20 -060084 pcie_configured = is_serdes_configured(PCIE3);
Ed Swarthout837f1ba2007-07-27 01:50:51 -050085
Kumar Gala645d5a72009-11-04 10:22:26 -060086 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
Kumar Gala64a16862010-12-17 06:01:24 -060087 /* contains both PCIE3 MEM & IO space */
88 set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_4M,
89 LAW_TRGT_IF_PCIE_3);
90 SET_STD_PCIE_INFO(pci_info, 3);
91 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info.regs);
92
Ed Swarthout837f1ba2007-07-27 01:50:51 -050093 /* outbound memory */
Kumar Gala645d5a72009-11-04 10:22:26 -060094 pci_set_region(&pcie3_hose.regions[0],
Kumar Gala10795f42008-12-02 16:08:36 -060095 CONFIG_SYS_PCIE3_MEM_BUS2,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096 CONFIG_SYS_PCIE3_MEM_PHYS2,
97 CONFIG_SYS_PCIE3_MEM_SIZE2,
Ed Swarthout837f1ba2007-07-27 01:50:51 -050098 PCI_REGION_MEM);
Kumar Gala645d5a72009-11-04 10:22:26 -060099
100 pcie3_hose.region_count = 1;
Kumar Gala64a16862010-12-17 06:01:24 -0600101
Peter Tyser8ca78f22010-10-29 17:59:24 -0500102 printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
103 pcie_ep ? "Endpoint" : "Root Complex",
Kumar Gala64a16862010-12-17 06:01:24 -0600104 pci_info.regs);
105 first_free_busno = fsl_pci_init_port(&pci_info,
Kumar Gala645d5a72009-11-04 10:22:26 -0600106 &pcie3_hose, first_free_busno);
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500107
Kumar Gala56a92702007-08-30 16:18:18 -0500108 /*
109 * Activate ULI1575 legacy chip by performing a fake
110 * memory access. Needed to make ULI RTC work.
111 */
Kumar Gala10795f42008-12-02 16:08:36 -0600112 in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500113 } else {
Peter Tyser8ca78f22010-10-29 17:59:24 -0500114 printf("PCIE3: disabled\n");
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500115 }
Kumar Gala645d5a72009-11-04 10:22:26 -0600116 puts("\n");
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500117#else
Kumar Gala645d5a72009-11-04 10:22:26 -0600118 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500119#endif
120
121#ifdef CONFIG_PCIE1
Kumar Gala64a16862010-12-17 06:01:24 -0600122 SET_STD_PCIE_INFO(pci_info, 1);
123 first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE1, &pci_info);
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500124#else
Kumar Gala64a16862010-12-17 06:01:24 -0600125 setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500126#endif
127
128#ifdef CONFIG_PCIE2
Kumar Gala64a16862010-12-17 06:01:24 -0600129 SET_STD_PCIE_INFO(pci_info, 2);
130 first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE2, &pci_info);
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500131#else
Kumar Gala64a16862010-12-17 06:01:24 -0600132 setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500133#endif
134
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500135#ifdef CONFIG_PCI1
Kumar Gala645d5a72009-11-04 10:22:26 -0600136 pci_speed = 66666000;
137 pci_32 = 1;
138 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
139 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500140
141 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
Kumar Gala64a16862010-12-17 06:01:24 -0600142 SET_STD_PCI_INFO(pci_info, 1);
143 set_next_law(pci_info.mem_phys,
144 law_size_bits(pci_info.mem_size), pci_info.law);
145 set_next_law(pci_info.io_phys,
146 law_size_bits(pci_info.io_size), pci_info.law);
147
148 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
Peter Tyser8ca78f22010-10-29 17:59:24 -0500149 printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500150 (pci_32) ? 32 : 64,
151 (pci_speed == 33333000) ? "33" :
152 (pci_speed == 66666000) ? "66" : "unknown",
153 pci_clk_sel ? "sync" : "async",
154 pci_agent ? "agent" : "host",
155 pci_arb ? "arbiter" : "external-arbiter",
Kumar Gala64a16862010-12-17 06:01:24 -0600156 pci_info.regs);
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500157
Kumar Gala64a16862010-12-17 06:01:24 -0600158 first_free_busno = fsl_pci_init_port(&pci_info,
Kumar Gala645d5a72009-11-04 10:22:26 -0600159 &pci1_hose, first_free_busno);
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500160 } else {
Peter Tyser8ca78f22010-10-29 17:59:24 -0500161 printf("PCI: disabled\n");
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500162 }
Kumar Gala645d5a72009-11-04 10:22:26 -0600163
164 puts("\n");
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500165#else
Kumar Gala645d5a72009-11-04 10:22:26 -0600166 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500167#endif
168}
169
Jon Loeliger25d83d72007-04-11 16:51:02 -0500170int last_stage_init(void)
171{
172 return 0;
173}
174
175
176unsigned long
177get_board_sys_clk(ulong dummy)
178{
179 u8 i, go_bit, rd_clks;
180 ulong val = 0;
Kumar Gala048e7ef2009-07-22 10:12:39 -0500181 u8 *pixis_base = (u8 *)PIXIS_BASE;
Jon Loeliger25d83d72007-04-11 16:51:02 -0500182
Kumar Gala048e7ef2009-07-22 10:12:39 -0500183 go_bit = in_8(pixis_base + PIXIS_VCTL);
Jon Loeliger25d83d72007-04-11 16:51:02 -0500184 go_bit &= 0x01;
185
Kumar Gala048e7ef2009-07-22 10:12:39 -0500186 rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
Jon Loeliger25d83d72007-04-11 16:51:02 -0500187 rd_clks &= 0x1C;
188
189 /*
190 * Only if both go bit and the SCLK bit in VCFGEN0 are set
191 * should we be using the AUX register. Remember, we also set the
192 * GO bit to boot from the alternate bank on the on-board flash
193 */
194
195 if (go_bit) {
196 if (rd_clks == 0x1c)
Kumar Gala048e7ef2009-07-22 10:12:39 -0500197 i = in_8(pixis_base + PIXIS_AUX);
Jon Loeliger25d83d72007-04-11 16:51:02 -0500198 else
Kumar Gala048e7ef2009-07-22 10:12:39 -0500199 i = in_8(pixis_base + PIXIS_SPD);
Jon Loeliger25d83d72007-04-11 16:51:02 -0500200 } else {
Kumar Gala048e7ef2009-07-22 10:12:39 -0500201 i = in_8(pixis_base + PIXIS_SPD);
Jon Loeliger25d83d72007-04-11 16:51:02 -0500202 }
203
204 i &= 0x07;
205
206 switch (i) {
207 case 0:
208 val = 33333333;
209 break;
210 case 1:
211 val = 40000000;
212 break;
213 case 2:
214 val = 50000000;
215 break;
216 case 3:
217 val = 66666666;
218 break;
219 case 4:
220 val = 83000000;
221 break;
222 case 5:
223 val = 100000000;
224 break;
225 case 6:
226 val = 133333333;
227 break;
228 case 7:
229 val = 166666666;
230 break;
231 }
232
233 return val;
234}
235
Andy Fleming063c1262011-04-08 02:10:54 -0500236
237#define MIIM_CIS8204_SLED_CON 0x1b
238#define MIIM_CIS8204_SLEDCON_INIT 0x1115
239/*
240 * Hack to write all 4 PHYs with the LED values
241 */
242int board_phy_config(struct phy_device *phydev)
243{
244 static int do_once;
245 uint phyid;
246 struct mii_dev *bus = phydev->bus;
247
Troy Kisky9fafe7d2012-02-07 14:08:49 +0000248 if (phydev->drv->config)
249 phydev->drv->config(phydev);
Andy Fleming063c1262011-04-08 02:10:54 -0500250 if (do_once)
251 return 0;
252
253 for (phyid = 0; phyid < 4; phyid++)
254 bus->write(bus, phyid, MDIO_DEVAD_NONE, MIIM_CIS8204_SLED_CON,
255 MIIM_CIS8204_SLEDCON_INIT);
256
257 do_once = 1;
258
259 return 0;
260}
261
262
Andy Fleming216f2a72008-08-31 16:33:29 -0500263int board_eth_init(bd_t *bis)
264{
Ben Warren0b252f52008-08-31 21:41:08 -0700265#ifdef CONFIG_TSEC_ENET
Andy Fleming063c1262011-04-08 02:10:54 -0500266 struct fsl_pq_mdio_info mdio_info;
Andy Fleming216f2a72008-08-31 16:33:29 -0500267 struct tsec_info_struct tsec_info[2];
Andy Fleming216f2a72008-08-31 16:33:29 -0500268 int num = 0;
269
270#ifdef CONFIG_TSEC1
271 SET_STD_TSEC_INFO(tsec_info[num], 1);
Kumar Gala058d7dc2010-12-16 14:28:06 -0600272 if (is_serdes_configured(SGMII_TSEC1)) {
273 puts("eTSEC1 is in sgmii mode.\n");
Andy Fleming216f2a72008-08-31 16:33:29 -0500274 tsec_info[num].flags |= TSEC_SGMII;
Kumar Gala058d7dc2010-12-16 14:28:06 -0600275 }
Andy Fleming216f2a72008-08-31 16:33:29 -0500276 num++;
277#endif
278#ifdef CONFIG_TSEC3
279 SET_STD_TSEC_INFO(tsec_info[num], 3);
Kumar Gala058d7dc2010-12-16 14:28:06 -0600280 if (is_serdes_configured(SGMII_TSEC3)) {
281 puts("eTSEC3 is in sgmii mode.\n");
Andy Fleming216f2a72008-08-31 16:33:29 -0500282 tsec_info[num].flags |= TSEC_SGMII;
Kumar Gala058d7dc2010-12-16 14:28:06 -0600283 }
Andy Fleming216f2a72008-08-31 16:33:29 -0500284 num++;
285#endif
286
287 if (!num) {
288 printf("No TSECs initialized\n");
289
290 return 0;
291 }
292
Kumar Gala058d7dc2010-12-16 14:28:06 -0600293 if (is_serdes_configured(SGMII_TSEC1) ||
294 is_serdes_configured(SGMII_TSEC3)) {
Andy Fleming216f2a72008-08-31 16:33:29 -0500295 fsl_sgmii_riser_init(tsec_info, num);
Kumar Gala058d7dc2010-12-16 14:28:06 -0600296 }
Andy Fleming216f2a72008-08-31 16:33:29 -0500297
Andy Fleming063c1262011-04-08 02:10:54 -0500298 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
299 mdio_info.name = DEFAULT_MII_NAME;
300 fsl_pq_mdio_init(bis, &mdio_info);
Andy Fleming216f2a72008-08-31 16:33:29 -0500301
302 tsec_eth_init(bis, tsec_info, num);
Andy Fleming216f2a72008-08-31 16:33:29 -0500303#endif
Ben Warren0b252f52008-08-31 21:41:08 -0700304 return pci_eth_init(bis);
305}
Andy Fleming216f2a72008-08-31 16:33:29 -0500306
Kumar Galaaddce572007-11-26 17:12:24 -0600307#if defined(CONFIG_OF_BOARD_SETUP)
Simon Glasse895a4b2014-10-23 18:58:47 -0600308int ft_board_setup(void *blob, bd_t *bd)
Jon Loeliger25d83d72007-04-11 16:51:02 -0500309{
Wolfgang Denk2f152782007-05-05 18:23:11 +0200310 ft_cpu_setup(blob, bd);
Jon Loeliger25d83d72007-04-11 16:51:02 -0500311
Kumar Gala6525d512010-07-08 22:37:44 -0500312 FT_FSL_PCI_SETUP;
Kumar Gala2dba0de2008-10-21 08:28:33 -0500313
Andy Flemingfeede8b2008-12-05 20:10:22 -0600314#ifdef CONFIG_FSL_SGMII_RISER
315 fsl_sgmii_riser_fdt_fixup(blob);
316#endif
Simon Glasse895a4b2014-10-23 18:58:47 -0600317
318 return 0;
Jon Loeliger25d83d72007-04-11 16:51:02 -0500319}
320#endif