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Weijie Gao4bc01042022-05-20 11:22:21 +08001/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2022 MediaTek Inc. All rights reserved.
4 *
5 * Author: Weijie Gao <weijie.gao@mediatek.com>
6 */
7
8#ifndef __CONFIG_MT7621_H
9#define __CONFIG_MT7621_H
10
Tom Riniaa6e94d2022-11-16 13:10:37 -050011#define CFG_SYS_SDRAM_BASE 0x80000000
Weijie Gao4bc01042022-05-20 11:22:21 +080012
Tom Rini1d457db2022-12-04 10:04:50 -050013#define CFG_MAX_MEM_MAPPED 0x1c000000
Weijie Gao4bc01042022-05-20 11:22:21 +080014
Weijie Gaofd9385a2023-07-19 17:15:47 +080015#define CFG_SYS_INIT_SP_OFFSET 0x800000
Weijie Gao4bc01042022-05-20 11:22:21 +080016
Weijie Gao4bc01042022-05-20 11:22:21 +080017/* Serial SPL */
Simon Glassf38956a2024-09-29 19:49:49 -060018#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_SERIAL)
Tom Rini91092132022-11-16 13:10:28 -050019#define CFG_SYS_NS16550_CLK 50000000
20#define CFG_SYS_NS16550_COM1 0xbe000c00
Weijie Gao4bc01042022-05-20 11:22:21 +080021#endif
22
23/* Serial common */
Weijie Gaofd9385a2023-07-19 17:15:47 +080024#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
Weijie Gao4bc01042022-05-20 11:22:21 +080025 230400, 460800, 921600 }
26
27/* Dummy value */
Tom Rini65cc0e22022-11-16 13:10:41 -050028#define CFG_SYS_UBOOT_BASE 0
Weijie Gao4bc01042022-05-20 11:22:21 +080029
30#endif /* __CONFIG_MT7621_H */