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wdenk5b1d7132002-11-03 00:07:02 +00001/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk5b1d7132002-11-03 00:07:02 +00006 */
7
wdenk5b1d7132002-11-03 00:07:02 +00008/* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
9 * U-Boot port on RPXlite board
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15#define RPXLite_50MHz
16
17/*
18 * High Level Configuration Options
19 * (easy to change)
20 */
21
22#undef CONFIG_MPC860
23#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
24#define CONFIG_RPXLITE 1
25
Wolfgang Denk2ae18242010-10-06 09:05:45 +020026#define CONFIG_SYS_TEXT_BASE 0xfff00000
27
wdenk5b1d7132002-11-03 00:07:02 +000028#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
29#undef CONFIG_8xx_CONS_SMC2
30#undef CONFIG_8xx_CONS_NONE
31#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
32#if 0
33#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
34#else
35#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
36#endif
37
wdenk5b1d7132002-11-03 00:07:02 +000038#undef CONFIG_BOOTARGS
39#define CONFIG_BOOTCOMMAND \
Wolfgang Denk53677ef2008-05-20 16:00:29 +020040 "bootp; " \
41 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
42 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenk5b1d7132002-11-03 00:07:02 +000043 "bootm"
44
45#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020046#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenk5b1d7132002-11-03 00:07:02 +000047
Wolfgang Denkf47b6612006-03-12 01:48:55 +010048#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
wdenk5b1d7132002-11-03 00:07:02 +000049#undef CONFIG_WATCHDOG /* watchdog disabled */
50
Jon Loeliger18225e82007-07-09 21:31:24 -050051/*
52 * BOOTP options
53 */
54#define CONFIG_BOOTP_SUBNETMASK
55#define CONFIG_BOOTP_GATEWAY
56#define CONFIG_BOOTP_HOSTNAME
57#define CONFIG_BOOTP_BOOTPATH
58#define CONFIG_BOOTP_BOOTFILESIZE
59
wdenk5b1d7132002-11-03 00:07:02 +000060
Jon Loeligere9a0f8f2007-07-08 15:12:40 -050061/*
62 * Command line configuration.
63 */
64#include <config_cmd_default.h>
65
wdenk5b1d7132002-11-03 00:07:02 +000066
67/*
68 * Miscellaneous configurable options
69 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070#define CONFIG_SYS_LONGHELP /* undef to save memory */
71#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligere9a0f8f2007-07-08 15:12:40 -050072#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk5b1d7132002-11-03 00:07:02 +000074#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk5b1d7132002-11-03 00:07:02 +000076#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
78#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
79#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk5b1d7132002-11-03 00:07:02 +000080
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
82#define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
wdenk5b1d7132002-11-03 00:07:02 +000083
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#define CONFIG_SYS_RESET_ADDRESS 0x09900000
wdenk5b1d7132002-11-03 00:07:02 +000085
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
Wolfgang Denkf47b6612006-03-12 01:48:55 +010087
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk5b1d7132002-11-03 00:07:02 +000089
wdenk5b1d7132002-11-03 00:07:02 +000090/*
91 * Low Level Configuration Settings
92 * (address mappings, register initial values, etc.)
93 * You should know what you are doing if you make changes here.
94 */
95/*-----------------------------------------------------------------------
96 * Internal Memory Mapped Register
97 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_IMMR 0xFA200000
wdenk5b1d7132002-11-03 00:07:02 +000099
100/*-----------------------------------------------------------------------
101 * Definitions for initial stack pointer and data area (in DPRAM)
102 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200104#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200105#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk5b1d7132002-11-03 00:07:02 +0000107
108/*-----------------------------------------------------------------------
109 * Start addresses for the final memory configuration
110 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk5b1d7132002-11-03 00:07:02 +0000112 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_SDRAM_BASE 0x00000000
114#define CONFIG_SYS_FLASH_BASE 0xFFC00000
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200115#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
Wolfgang Denkf47b6612006-03-12 01:48:55 +0100117#ifdef CONFIG_BZIP2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve ~4 MB for malloc() */
wdenk5b1d7132002-11-03 00:07:02 +0000119#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
Wolfgang Denkf47b6612006-03-12 01:48:55 +0100121#endif /* CONFIG_BZIP2 */
wdenk5b1d7132002-11-03 00:07:02 +0000122
123/*
124 * For booting Linux, the board info and command line data
125 * have to be in the first 8 MB of memory, since this is
126 * the maximum mapped by the Linux kernel during initialization.
127 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk5b1d7132002-11-03 00:07:02 +0000129
130/*-----------------------------------------------------------------------
131 * FLASH organization
132 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
134#define CONFIG_SYS_MAX_FLASH_SECT 19 /* max number of sectors on one chip */
wdenk5b1d7132002-11-03 00:07:02 +0000135
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
137#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk5b1d7132002-11-03 00:07:02 +0000138
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_DIRECT_FLASH_TFTP
Wolfgang Denkf47b6612006-03-12 01:48:55 +0100140
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200141#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200142#define CONFIG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Wolfgang Denkf47b6612006-03-12 01:48:55 +0100144
145#define CONFIG_ENV_OVERWRITE
wdenk5b1d7132002-11-03 00:07:02 +0000146
147/*-----------------------------------------------------------------------
148 * Cache Configuration
149 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500151#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenk5b1d7132002-11-03 00:07:02 +0000153#endif
154
155/*-----------------------------------------------------------------------
156 * SYPCR - System Protection Control 11-9
157 * SYPCR can only be written once after reset!
158 *-----------------------------------------------------------------------
159 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
160 */
161#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenk5b1d7132002-11-03 00:07:02 +0000163 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
164#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenk5b1d7132002-11-03 00:07:02 +0000166#endif
167
168/*-----------------------------------------------------------------------
169 * SIUMCR - SIU Module Configuration 11-6
170 *-----------------------------------------------------------------------
171 * PCMCIA config., multi-function pin tri-state
172 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC10)
wdenk5b1d7132002-11-03 00:07:02 +0000174
175/*-----------------------------------------------------------------------
176 * TBSCR - Time Base Status and Control 11-26
177 *-----------------------------------------------------------------------
178 * Clear Reference Interrupt Status, Timebase freezing enabled
179 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
wdenk5b1d7132002-11-03 00:07:02 +0000181
182/*-----------------------------------------------------------------------
183 * RTCSC - Real-Time Clock Status and Control Register 11-27
184 *-----------------------------------------------------------------------
185 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186/*%%%#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
187#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_RTE)
wdenk5b1d7132002-11-03 00:07:02 +0000188
189/*-----------------------------------------------------------------------
190 * PISCR - Periodic Interrupt Status and Control 11-31
191 *-----------------------------------------------------------------------
192 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
193 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenk5b1d7132002-11-03 00:07:02 +0000195
196/*-----------------------------------------------------------------------
197 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
198 *-----------------------------------------------------------------------
199 * Reset PLL lock status sticky bit, timer expired status bit and timer
200 * interrupt status bit
201 *
202 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
203 */
204/* up to 50 MHz we use a 1:1 clock */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
wdenk5b1d7132002-11-03 00:07:02 +0000206
207/*-----------------------------------------------------------------------
208 * SCCR - System Clock and reset Control Register 15-27
209 *-----------------------------------------------------------------------
210 * Set clock output, timebase and RTC source and divider,
211 * power management and some other internal clocks
212 */
213#define SCCR_MASK SCCR_EBDF00
214/* up to 50 MHz we use a 1:1 clock */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_SCCR (SCCR_COM11 | SCCR_TBS)
wdenk5b1d7132002-11-03 00:07:02 +0000216
217/*-----------------------------------------------------------------------
218 * PCMCIA stuff
219 *-----------------------------------------------------------------------
220 *
221 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
223#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
224#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
225#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
226#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
227#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
228#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
229#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenk5b1d7132002-11-03 00:07:02 +0000230
231/*-----------------------------------------------------------------------
232 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
233 *-----------------------------------------------------------------------
234 */
235
Pavel Herrmann8d1165e11a2012-10-09 07:01:56 +0000236#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
wdenk5b1d7132002-11-03 00:07:02 +0000237#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
238
239#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
240#undef CONFIG_IDE_LED /* LED for ide not supported */
241#undef CONFIG_IDE_RESET /* reset for ide not supported */
242
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
244#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenk5b1d7132002-11-03 00:07:02 +0000245
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenk5b1d7132002-11-03 00:07:02 +0000247
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenk5b1d7132002-11-03 00:07:02 +0000249
250/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenk5b1d7132002-11-03 00:07:02 +0000252
253/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenk5b1d7132002-11-03 00:07:02 +0000255
256/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenk5b1d7132002-11-03 00:07:02 +0000258
259/*-----------------------------------------------------------------------
260 *
261 *-----------------------------------------------------------------------
262 *
263 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264/*#define CONFIG_SYS_DER 0x2002000F*/
265#define CONFIG_SYS_DER 0
wdenk5b1d7132002-11-03 00:07:02 +0000266
267/*
268 * Init Memory Controller:
269 *
270 * BR0 and OR0 (FLASH)
271 */
272
273#define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_PRELIM_OR_AM 0xFE000000 /* OR addr mask */
wdenk5b1d7132002-11-03 00:07:02 +0000275
276/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
wdenk5b1d7132002-11-03 00:07:02 +0000278
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
280#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
wdenk5b1d7132002-11-03 00:07:02 +0000281
282/*
283 * BR1 and OR1 (SDRAM)
284 *
285 */
286#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
287#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */
288
289/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000E00
wdenk5b1d7132002-11-03 00:07:02 +0000291
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
293#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenk5b1d7132002-11-03 00:07:02 +0000294
295/* RPXLITE mem setting */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296#define CONFIG_SYS_BR3_PRELIM 0xFA400001 /* BCSR */
297#define CONFIG_SYS_OR3_PRELIM 0xFFFF8910
298#define CONFIG_SYS_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */
299#define CONFIG_SYS_OR4_PRELIM 0xFFFE0970
wdenk5b1d7132002-11-03 00:07:02 +0000300
301/*
302 * Memory Periodic Timer Prescaler
303 */
304
305/* periodic timer for refresh */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_MAMR_PTA 58
wdenk5b1d7132002-11-03 00:07:02 +0000307
308/*
309 * Refresh clock Prescalar
310 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV8
wdenk5b1d7132002-11-03 00:07:02 +0000312
313/*
314 * MAMR settings for SDRAM
315 */
316
317/* 10 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenk5b1d7132002-11-03 00:07:02 +0000319 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \
320 MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)
321
wdenk5b1d7132002-11-03 00:07:02 +0000322/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
323/* Configuration variable added by yooth. */
324/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
325
326/*
327 * BCSRx
328 *
329 * Board Status and Control Registers
330 *
331 */
332
333#define BCSR0 0xFA400000
334#define BCSR1 0xFA400001
335#define BCSR2 0xFA400002
336#define BCSR3 0xFA400003
337
338#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200339#define BCSR0_ENNVRAM 0x02 /* CS4# Control */
Wolfgang Denkf47b6612006-03-12 01:48:55 +0100340#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
341#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
wdenk5b1d7132002-11-03 00:07:02 +0000342#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
343#define BCSR0_COLTEST 0x20
344#define BCSR0_ETHLPBK 0x40
Wolfgang Denkf47b6612006-03-12 01:48:55 +0100345#define BCSR0_ETHEN 0x80
wdenk5b1d7132002-11-03 00:07:02 +0000346
347#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */
348#define BCSR1_PCVCTL6 0x02
349#define BCSR1_PCVCTL5 0x04
350#define BCSR1_PCVCTL4 0x08
351#define BCSR1_IPB5SEL 0x10
352
353#define BCSR2_ENPA5HDR 0x08 /* USB Control */
354#define BCSR2_ENUSBCLK 0x10
355#define BCSR2_USBPWREN 0x20
356#define BCSR2_USBSPD 0x40
357#define BCSR2_USBSUSP 0x80
358
Wolfgang Denkf47b6612006-03-12 01:48:55 +0100359#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */
360#define BCSR3_BWNVR 0x02 /* NVRAM Battery */
wdenk5b1d7132002-11-03 00:07:02 +0000361#define BCSR3_RDY_BSY 0x04 /* Flash Operation */
Wolfgang Denkf47b6612006-03-12 01:48:55 +0100362#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */
363#define BCSR3_D27 0x10 /* Dip Switch settings */
364#define BCSR3_D26 0x20
365#define BCSR3_D25 0x40
366#define BCSR3_D24 0x80
wdenk5b1d7132002-11-03 00:07:02 +0000367
368#endif /* __CONFIG_H */