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Dirk Eibachd7b26d52008-10-08 15:37:50 +02001/*
2 * (C) Copyright 2007-2008
3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27
28#define CONFIG_405EP 1 /* this is a PPC405 CPU */
29#define CONFIG_4xx 1 /* member of PPC4xx family */
30#define CONFIG_NEO 1 /* on a Neo board */
31
32/*
33 * Include common defines/options for all AMCC eval boards
34 */
35#define CONFIG_HOSTNAME neo
36#include "amcc-common.h"
37
38#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
39
40#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
41
42/*
43 * Configure PLL
44 */
45#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
46#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
47
48/* new uImage format support */
49#define CONFIG_FIT
50#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
51
52#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
53
54/*
55 * Default environment variables
56 */
57#define CONFIG_EXTRA_ENV_SETTINGS \
58 CONFIG_AMCC_DEF_ENV \
59 CONFIG_AMCC_DEF_ENV_POWERPC \
60 CONFIG_AMCC_DEF_ENV_NOR_UPD \
61 "kernel_addr=fc000000\0" \
62 "fdt_addr=fc1e0000\0" \
63 "ramdisk_addr=fc200000\0" \
64 ""
65
66#define CONFIG_PHY_ADDR 4 /* PHY address */
67#define CONFIG_HAS_ETH0
68#define CONFIG_HAS_ETH1
69#define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */
70#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
71
72/*
73 * Commands additional to the ones defined in amcc-common.h
74 */
75#define CONFIG_CMD_CACHE
76#define CONFIG_CMD_DATE
77#define CONFIG_CMD_DTT
78#undef CONFIG_CMD_EEPROM
79
80/*
81 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
82 */
83#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
84
85/* SDRAM timings used in datasheet */
86#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
87#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
88#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
89#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
90#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
91
92/*
93 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
94 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
95 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
96 * The Linux BASE_BAUD define should match this configuration.
97 * baseBaud = cpuClock/(uartDivisor*16)
98 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
99 * set Linux BASE_BAUD to 403200.
100 */
101#undef CONFIG_SERIAL_SOFTWARE_FIFO
102#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
103#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
104#define CONFIG_SYS_BASE_BAUD 691200
105
106/*
107 * I2C stuff
108 */
109#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
110
111/* RTC */
112#define CONFIG_RTC_DS1337
113#define CONFIG_SYS_I2C_RTC_ADDR 0x68
114
115/* Temp sensor/hwmon/dtt */
116#define CONFIG_DTT_LM63 1 /* National LM63 */
117#define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */
118#define CONFIG_DTT_PWM_LOOKUPTABLE \
119 { { 40, 10 }, { 50, 20 }, { 60, 40 } }
120#define CONFIG_DTT_TACH_LIMIT 0xa10
121
122/*
123 * FLASH organization
124 */
125#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
126#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
127
128#define CONFIG_SYS_FLASH_BASE 0xFC000000
129#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
130
131#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
132#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
133
134#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
135#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
136
137#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
138#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
139
140#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
141#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
142
143#ifdef CONFIG_ENV_IS_IN_FLASH
144#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
145#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
146#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
147
148/* Address and size of Redundant Environment Sector */
149#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
150#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
151#endif
152
153/*
154 * PPC405 GPIO Configuration
155 */
156#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
157{ \
158/* GPIO Core 0 */ \
159{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
160{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
161{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
162{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
163{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
164{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO5 TS3 */ \
165{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
166{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
167{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
168{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
169{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
170{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
171{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
172{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
173{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
174{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
175{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
176{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
177{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
178{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
179{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
180{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
181{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
182{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
183{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
184{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
185{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
186{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
187{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
188{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
189{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
190{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
191} \
192}
193
194/*
195 * Definitions for initial stack pointer and data area (in data cache)
196 */
197/* use on chip memory (OCM) for temperary stack until sdram is tested */
198#define CONFIG_SYS_TEMP_STACK_OCM 1
199
200/* On Chip Memory location */
201#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
202#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
203#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
204#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
205
206#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
207#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
208#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
209
210/*
211 * External Bus Controller (EBC) Setup
212 */
213
214/* Memory Bank 0 (NOR-FLASH) initialization */
215#define CONFIG_SYS_EBC_PB0AP 0x92015480
216#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */
217
218/* Memory Bank 1 (NVRAM) initialization */
219#define CONFIG_SYS_EBC_PB1AP 0x92015480
220#define CONFIG_SYS_EBC_PB1CR 0xFB85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
221
222/* Memory Bank 2 (FPGA) initialization */
223#define CONFIG_FPGA_BASE 0x7f100000
224#define CONFIG_SYS_EBC_PB2AP 0x92015480
225#define CONFIG_SYS_EBC_PB2CR 0x7f11a000 /* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
226
227/* Memory Bank 3 (Latches) initialization */
228#define CONFIG_SYS_EBC_PB3AP 0x92015480
229#define CONFIG_SYS_EBC_PB3CR 0x7f21a000 /* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
230
231#endif /* __CONFIG_H */