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Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +09001/*
2 * Configuation settings for the Renesas Technology R0P7785LC0011RL board
3 *
4 * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#ifndef __SH7785LCR_H
26#define __SH7785LCR_H
27
28#undef DEBUG
29#define CONFIG_SH 1
30#define CONFIG_SH4A 1
31#define CONFIG_CPU_SH7785 1
32#define CONFIG_SH7785LCR 1
33
34#define CONFIG_CMD_FLASH
35#define CONFIG_CMD_MEMORY
36#define CONFIG_CMD_PCI
37#define CONFIG_CMD_NET
38#define CONFIG_CMD_PING
39#define CONFIG_CMD_NFS
40#define CONFIG_CMD_DFL
41#define CONFIG_CMD_SDRAM
42#define CONFIG_CMD_RUN
Mike Frysingerbdab39d2009-01-28 19:08:14 -050043#define CONFIG_CMD_SAVEENV
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +090044
45#define CONFIG_CMD_USB
46#define CONFIG_USB_STORAGE
47#define CONFIG_CMD_EXT2
48#define CONFIG_CMD_FAT
49#define CONFIG_DOS_PARTITION
50#define CONFIG_MAC_PARTITION
51
52#define CONFIG_BAUDRATE 115200
53#define CONFIG_BOOTDELAY 3
54#define CONFIG_BOOTARGS "console=ttySC1,115200 root=/dev/nfs ip=dhcp"
55
56#define CONFIG_EXTRA_ENV_SETTINGS \
57 "bootdevice=0:1\0" \
58 "usbload=usb reset;usbboot;usb stop;bootm\0"
59
60#define CONFIG_VERSION_VARIABLE
61#undef CONFIG_SHOW_BOOT_PROGRESS
62
63/* MEMORY */
Yoshihiro Shimodaada93182009-03-03 15:11:17 +090064#if defined(CONFIG_SH_32BIT)
Nobuhiro Iwamatsu915d6b72010-10-05 16:58:05 +090065/* 0x40000000 - 0x47FFFFFF does not use */
66#define CONFIG_SH_SDRAM_OFFSET (0x8000000)
67#define SH7785LCR_SDRAM_PHYS_BASE (0x40000000 + CONFIG_SH_SDRAM_OFFSET)
68#define SH7785LCR_SDRAM_BASE (0x80000000 + CONFIG_SH_SDRAM_OFFSET)
Yoshihiro Shimodaada93182009-03-03 15:11:17 +090069#define SH7785LCR_SDRAM_SIZE (384 * 1024 * 1024)
70#define SH7785LCR_FLASH_BASE_1 (0xa0000000)
71#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024)
72#define SH7785LCR_USB_BASE (0xa6000000)
73#else
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +090074#define SH7785LCR_SDRAM_BASE (0x08000000)
75#define SH7785LCR_SDRAM_SIZE (128 * 1024 * 1024)
76#define SH7785LCR_FLASH_BASE_1 (0xa0000000)
77#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024)
78#define SH7785LCR_USB_BASE (0xb4000000)
Yoshihiro Shimodaada93182009-03-03 15:11:17 +090079#endif
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +090080
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#define CONFIG_SYS_LONGHELP
82#define CONFIG_SYS_PROMPT "=> "
83#define CONFIG_SYS_CBSIZE 256
84#define CONFIG_SYS_PBSIZE 256
85#define CONFIG_SYS_MAXARGS 16
86#define CONFIG_SYS_BARGSIZE 512
87#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +090088
89/* SCIF */
Nobuhiro Iwamatsu1c981722008-08-28 14:53:31 +090090#define CONFIG_SCIF_CONSOLE 1
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +090091#define CONFIG_CONS_SCIF1 1
92#define CONFIG_SCIF_EXT_CLOCK 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#undef CONFIG_SYS_CONSOLE_INFO_QUIET
94#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
95#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +090096
97
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_MEMTEST_START (SH7785LCR_SDRAM_BASE)
99#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900100 (SH7785LCR_SDRAM_SIZE) - \
101 4 * 1024 * 1024)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#undef CONFIG_SYS_ALT_MEMTEST
103#undef CONFIG_SYS_MEMTEST_SCRATCH
104#undef CONFIG_SYS_LOADS_BAUD_CHANGE
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900105
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_SDRAM_BASE (SH7785LCR_SDRAM_BASE)
107#define CONFIG_SYS_SDRAM_SIZE (SH7785LCR_SDRAM_SIZE)
108#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900109
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_MONITOR_BASE (SH7785LCR_FLASH_BASE_1)
111#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
112#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900114
115/* FLASH */
Nobuhiro Iwamatsu1c981722008-08-28 14:53:31 +0900116#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_FLASH_CFI
118#undef CONFIG_SYS_FLASH_QUIET_TEST
119#define CONFIG_SYS_FLASH_EMPTY_INFO
120#define CONFIG_SYS_FLASH_BASE (SH7785LCR_FLASH_BASE_1)
121#define CONFIG_SYS_MAX_FLASH_SECT 512
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900122
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_MAX_FLASH_BANKS 1
124#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + \
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900125 (0 * SH7785LCR_FLASH_BANK_SIZE) }
126
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
128#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
129#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
130#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900131
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#undef CONFIG_SYS_FLASH_PROTECTION
133#undef CONFIG_SYS_DIRECT_FLASH_TFTP
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900134
135/* R8A66597 */
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900136#define CONFIG_USB_R8A66597_HCD
137#define CONFIG_R8A66597_BASE_ADDR SH7785LCR_USB_BASE
138#define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */
139#define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */
140#define CONFIG_R8A66597_ENDIAN 0x0000 /* little */
141
142/* PCI Controller */
143#define CONFIG_PCI
144#define CONFIG_SH4_PCI
145#define CONFIG_SH7780_PCI
Yoshihiro Shimodaada93182009-03-03 15:11:17 +0900146#if defined(CONFIG_SH_32BIT)
147#define CONFIG_SH7780_PCI_LSR 0x1ff00001
148#define CONFIG_SH7780_PCI_LAR 0x5f000000
149#define CONFIG_SH7780_PCI_BAR 0x5f000000
150#else
Yoshihiro Shimoda06b18162009-02-25 14:26:42 +0900151#define CONFIG_SH7780_PCI_LSR 0x07f00001
152#define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE
153#define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE
Yoshihiro Shimodaada93182009-03-03 15:11:17 +0900154#endif
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900155#define CONFIG_PCI_PNP
156#define CONFIG_PCI_SCAN_SHOW 1
157
158#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
159#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
160#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
161
162#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */
163#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
164#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */
165
Yoshihiro Shimodaada93182009-03-03 15:11:17 +0900166#if defined(CONFIG_SH_32BIT)
167#define CONFIG_PCI_SYS_PHYS SH7785LCR_SDRAM_PHYS_BASE
168#else
Yoshihiro Shimodab3061b42009-02-25 14:26:55 +0900169#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
Yoshihiro Shimodaada93182009-03-03 15:11:17 +0900170#endif
171#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
Yoshihiro Shimodab3061b42009-02-25 14:26:55 +0900172#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
173
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900174/* Network device (RTL8169) support */
175#define CONFIG_NET_MULTI
176#define CONFIG_RTL8169
177
178/* ENV setting */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200179#define CONFIG_ENV_IS_IN_FLASH
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900180#define CONFIG_ENV_OVERWRITE 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200181#define CONFIG_ENV_SECT_SIZE (256 * 1024)
182#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
184#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200185#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900186
187/* Board Clock */
188/* The SCIF used external clock. system clock only used timer. */
189#define CONFIG_SYS_CLK_FREQ 50000000
Jean-Christophe PLAGNIOL-VILLARDbe45c632009-06-04 12:06:48 +0200190#define CONFIG_SYS_TMU_CLK_DIV 4
Jean-Christophe PLAGNIOL-VILLARD8dd29c82009-06-04 12:06:47 +0200191#define CONFIG_SYS_HZ 1000
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900192
193#endif /* __SH7785LCR_H */