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Dave Liu19580e62007-09-18 12:37:57 +08001/*
2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Dave Liu19580e62007-09-18 12:37:57 +08006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
Dave Liu19580e62007-09-18 12:37:57 +080011/*
12 * High Level Configuration Options
13 */
14#define CONFIG_E300 1 /* E300 family */
Peter Tyser0f898602009-05-22 17:23:24 -050015#define CONFIG_MPC83xx 1 /* MPC83xx family */
Peter Tyser2c7920a2009-05-22 17:23:25 -050016#define CONFIG_MPC837x 1 /* MPC837x CPU specific */
Dave Liu19580e62007-09-18 12:37:57 +080017#define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */
18
Wolfgang Denk2ae18242010-10-06 09:05:45 +020019#define CONFIG_SYS_TEXT_BASE 0xFE000000
20
Dave Liu19580e62007-09-18 12:37:57 +080021/*
22 * System Clock Setup
23 */
24#ifdef CONFIG_PCISLAVE
25#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
26#else
27#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
28#endif
29
30#ifndef CONFIG_SYS_CLK_FREQ
31#define CONFIG_SYS_CLK_FREQ 66000000
32#endif
33
34/*
35 * Hardware Reset Configuration Word
36 * if CLKIN is 66MHz, then
37 * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz
38 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020039#define CONFIG_SYS_HRCW_LOW (\
Dave Liu19580e62007-09-18 12:37:57 +080040 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
41 HRCWL_DDR_TO_SCB_CLK_1X1 |\
42 HRCWL_SVCOD_DIV_2 |\
43 HRCWL_CSB_TO_CLKIN_6X1 |\
44 HRCWL_CORE_TO_CSB_1_5X1)
45
46#ifdef CONFIG_PCISLAVE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047#define CONFIG_SYS_HRCW_HIGH (\
Dave Liu19580e62007-09-18 12:37:57 +080048 HRCWH_PCI_AGENT |\
49 HRCWH_PCI1_ARBITER_DISABLE |\
50 HRCWH_CORE_ENABLE |\
51 HRCWH_FROM_0XFFF00100 |\
52 HRCWH_BOOTSEQ_DISABLE |\
53 HRCWH_SW_WATCHDOG_DISABLE |\
54 HRCWH_ROM_LOC_LOCAL_16BIT |\
55 HRCWH_RL_EXT_LEGACY |\
56 HRCWH_TSEC1M_IN_RGMII |\
57 HRCWH_TSEC2M_IN_RGMII |\
58 HRCWH_BIG_ENDIAN |\
59 HRCWH_LDP_CLEAR)
60#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020061#define CONFIG_SYS_HRCW_HIGH (\
Dave Liu19580e62007-09-18 12:37:57 +080062 HRCWH_PCI_HOST |\
63 HRCWH_PCI1_ARBITER_ENABLE |\
64 HRCWH_CORE_ENABLE |\
65 HRCWH_FROM_0X00000100 |\
66 HRCWH_BOOTSEQ_DISABLE |\
67 HRCWH_SW_WATCHDOG_DISABLE |\
68 HRCWH_ROM_LOC_LOCAL_16BIT |\
69 HRCWH_RL_EXT_LEGACY |\
70 HRCWH_TSEC1M_IN_RGMII |\
71 HRCWH_TSEC2M_IN_RGMII |\
72 HRCWH_BIG_ENDIAN |\
73 HRCWH_LDP_CLEAR)
74#endif
75
Dave Liubd4458c2008-03-04 16:59:22 +080076/* Arbiter Configuration Register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
Joe Hershberger8d858082011-10-11 23:57:18 -050078#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
Dave Liubd4458c2008-03-04 16:59:22 +080079
80/* System Priority Control Register */
Joe Hershberger8d858082011-10-11 23:57:18 -050081#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */
Dave Liubd4458c2008-03-04 16:59:22 +080082
Dave Liu19580e62007-09-18 12:37:57 +080083/*
Dave Liubd4458c2008-03-04 16:59:22 +080084 * IP blocks clock configuration
Dave Liu19580e62007-09-18 12:37:57 +080085 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */
87#define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */
Joe Hershberger8d858082011-10-11 23:57:18 -050088#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */
Dave Liu19580e62007-09-18 12:37:57 +080089
90/*
91 * System IO Config
92 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#define CONFIG_SYS_SICRH 0x00000000
94#define CONFIG_SYS_SICRL 0x00000000
Dave Liu19580e62007-09-18 12:37:57 +080095
96/*
97 * Output Buffer Impedance
98 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_OBIR 0x31100000
Dave Liu19580e62007-09-18 12:37:57 +0800100
101#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
102#define CONFIG_BOARD_EARLY_INIT_R
Anton Vorontsovc78c6782009-06-10 00:25:31 +0400103#define CONFIG_HWCONFIG
Dave Liu19580e62007-09-18 12:37:57 +0800104
105/*
106 * IMMR new address
107 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_IMMR 0xE0000000
Dave Liu19580e62007-09-18 12:37:57 +0800109
110/*
111 * DDR Setup
112 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
114#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
115#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
116#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
117#define CONFIG_SYS_83XX_DDR_USES_CS0
Joe Hershberger2fef4022011-10-11 23:57:29 -0500118#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \
119 | DDRCDR_ODT \
120 | DDRCDR_Q_DRN)
121 /* 0x80080001 */ /* ODT 150ohm on SoC */
Dave Liu19580e62007-09-18 12:37:57 +0800122
123#undef CONFIG_DDR_ECC /* support DDR ECC function */
124#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
125
126#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
127#define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
128
129#if defined(CONFIG_SPD_EEPROM)
130#define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */
131#else
132/*
133 * Manually set up DDR parameters
Dave Liu7e74d632008-01-10 23:07:23 +0800134 * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
Dave Liu19580e62007-09-18 12:37:57 +0800135 * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
136 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_DDR_SIZE 512 /* MB */
138#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
Joe Hershberger8d858082011-10-11 23:57:18 -0500139#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
Joe Hershberger2fef4022011-10-11 23:57:29 -0500140 | CSCONFIG_ODT_RD_NEVER /* ODT_RD to none */ \
141 | CSCONFIG_ODT_WR_ONLY_CURRENT /* ODT_WR to CSn */ \
142 | CSCONFIG_ROW_BIT_14 \
143 | CSCONFIG_COL_BIT_10)
144 /* 0x80010202 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_DDR_TIMING_3 0x00000000
Joe Hershberger8d858082011-10-11 23:57:18 -0500146#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
147 | (0 << TIMING_CFG0_WRT_SHIFT) \
148 | (0 << TIMING_CFG0_RRT_SHIFT) \
149 | (0 << TIMING_CFG0_WWT_SHIFT) \
150 | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
151 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
152 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
153 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
Dave Liu19580e62007-09-18 12:37:57 +0800154 /* 0x00620802 */
Joe Hershberger8d858082011-10-11 23:57:18 -0500155#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
156 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
157 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
158 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
159 | (13 << TIMING_CFG1_REFREC_SHIFT) \
160 | (3 << TIMING_CFG1_WRREC_SHIFT) \
161 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
162 | (2 << TIMING_CFG1_WRTORD_SHIFT))
Dave Liu19580e62007-09-18 12:37:57 +0800163 /* 0x3935d322 */
Joe Hershberger8d858082011-10-11 23:57:18 -0500164#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
165 | (6 << TIMING_CFG2_CPO_SHIFT) \
166 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
167 | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
168 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
169 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
170 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
Dave Liu7e74d632008-01-10 23:07:23 +0800171 /* 0x131088c8 */
Joe Hershberger8d858082011-10-11 23:57:18 -0500172#define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \
173 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
Dave Liu19580e62007-09-18 12:37:57 +0800174 /* 0x03E00100 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
176#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
Joe Hershberger8d858082011-10-11 23:57:18 -0500177#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
178 | (0x1432 << SDRAM_MODE_SD_SHIFT))
Dave Liu7e74d632008-01-10 23:07:23 +0800179 /* ODT 150ohm CL=3, AL=1 on SDRAM */
Joe Hershberger8d858082011-10-11 23:57:18 -0500180#define CONFIG_SYS_DDR_MODE2 0x00000000
Dave Liu19580e62007-09-18 12:37:57 +0800181#endif
182
183/*
184 * Memory test
185 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
187#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
188#define CONFIG_SYS_MEMTEST_END 0x00140000
Dave Liu19580e62007-09-18 12:37:57 +0800189
190/*
191 * The reserved memory
192 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200193#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Dave Liu19580e62007-09-18 12:37:57 +0800194
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
196#define CONFIG_SYS_RAMBOOT
Dave Liu19580e62007-09-18 12:37:57 +0800197#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#undef CONFIG_SYS_RAMBOOT
Dave Liu19580e62007-09-18 12:37:57 +0800199#endif
200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
Joe Hershberger8d858082011-10-11 23:57:18 -0500202#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
203#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
Dave Liu19580e62007-09-18 12:37:57 +0800204
205/*
206 * Initial RAM Base Address Setup
207 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_INIT_RAM_LOCK 1
209#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200210#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
Joe Hershberger8d858082011-10-11 23:57:18 -0500211#define CONFIG_SYS_GBL_DATA_OFFSET \
212 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Dave Liu19580e62007-09-18 12:37:57 +0800213
214/*
215 * Local Bus Configuration & Clock Setup
216 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500217#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
218#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_LBC_LBCR 0x00000000
Becky Bruce0914f482010-06-17 11:37:18 -0500220#define CONFIG_FSL_ELBC 1
Dave Liu19580e62007-09-18 12:37:57 +0800221
222/*
223 * FLASH on the Local Bus
224 */
Joe Hershberger8d858082011-10-11 23:57:18 -0500225#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200226#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Joe Hershberger8d858082011-10-11 23:57:18 -0500227#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
228#define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
229#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
Dave Liu19580e62007-09-18 12:37:57 +0800230
Joe Hershberger8d858082011-10-11 23:57:18 -0500231 /* Window base at flash base */
232#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500233#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
Dave Liu19580e62007-09-18 12:37:57 +0800234
Joe Hershberger8d858082011-10-11 23:57:18 -0500235#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500236 | BR_PS_16 /* 16 bit port */ \
237 | BR_MS_GPCM /* MSEL = GPCM */ \
238 | BR_V) /* valid */
239#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
Dave Liuded08312008-01-10 23:08:26 +0800240 | OR_UPM_XAM \
241 | OR_GPCM_CSNT \
Anton Vorontsovf9023af2008-05-29 18:14:56 +0400242 | OR_GPCM_ACS_DIV2 \
Dave Liuded08312008-01-10 23:08:26 +0800243 | OR_GPCM_XACS \
244 | OR_GPCM_SCY_15 \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500245 | OR_GPCM_TRLX_SET \
246 | OR_GPCM_EHTR_SET \
Joe Hershberger8d858082011-10-11 23:57:18 -0500247 | OR_GPCM_EAD)
Dave Liuded08312008-01-10 23:08:26 +0800248 /* 0xFE000FF7 */
Dave Liu19580e62007-09-18 12:37:57 +0800249
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
251#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
Dave Liu19580e62007-09-18 12:37:57 +0800252
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#undef CONFIG_SYS_FLASH_CHECKSUM
254#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
255#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Dave Liu19580e62007-09-18 12:37:57 +0800256
257/*
258 * BCSR on the Local Bus
259 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_BCSR 0xF8000000
Joe Hershberger8d858082011-10-11 23:57:18 -0500261 /* Access window base at BCSR base */
262#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500263#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
Dave Liu19580e62007-09-18 12:37:57 +0800264
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500265#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
266 | BR_PS_8 \
267 | BR_MS_GPCM \
268 | BR_V)
269 /* 0xF8000801 */
270#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
271 | OR_GPCM_XAM \
272 | OR_GPCM_CSNT \
273 | OR_GPCM_XACS \
274 | OR_GPCM_SCY_15 \
275 | OR_GPCM_TRLX_SET \
276 | OR_GPCM_EHTR_SET \
277 | OR_GPCM_EAD)
278 /* 0xFFFFE9F7 */
Dave Liu19580e62007-09-18 12:37:57 +0800279
280/*
281 * NAND Flash on the Local Bus
282 */
Anton Vorontsovb3379f32008-10-08 20:52:54 +0400283#define CONFIG_CMD_NAND 1
284#define CONFIG_MTD_NAND_VERIFY_WRITE 1
285#define CONFIG_SYS_MAX_NAND_DEVICE 1
Joe Hershberger8d858082011-10-11 23:57:18 -0500286#define CONFIG_NAND_FSL_ELBC 1
Anton Vorontsovb3379f32008-10-08 20:52:54 +0400287
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500288#define CONFIG_SYS_NAND_BASE 0xE0600000
Joe Hershberger8d858082011-10-11 23:57:18 -0500289#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500290 | BR_DECC_CHK_GEN /* Use HW ECC */ \
Joe Hershberger8d858082011-10-11 23:57:18 -0500291 | BR_PS_8 /* 8 bit port */ \
Dave Liu19580e62007-09-18 12:37:57 +0800292 | BR_MS_FCM /* MSEL = FCM */ \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500293 | BR_V) /* valid */
294#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \
Anton Vorontsovb3379f32008-10-08 20:52:54 +0400295 | OR_FCM_BCTLD \
Dave Liu19580e62007-09-18 12:37:57 +0800296 | OR_FCM_CST \
297 | OR_FCM_CHT \
298 | OR_FCM_SCY_1 \
Anton Vorontsovb3379f32008-10-08 20:52:54 +0400299 | OR_FCM_RST \
Dave Liu19580e62007-09-18 12:37:57 +0800300 | OR_FCM_TRLX \
Joe Hershberger8d858082011-10-11 23:57:18 -0500301 | OR_FCM_EHTR)
Anton Vorontsovb3379f32008-10-08 20:52:54 +0400302 /* 0xFFFF919E */
Dave Liu19580e62007-09-18 12:37:57 +0800303
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500305#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
Dave Liu19580e62007-09-18 12:37:57 +0800306
307/*
308 * Serial Port
309 */
310#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_NS16550
312#define CONFIG_SYS_NS16550_SERIAL
313#define CONFIG_SYS_NS16550_REG_SIZE 1
314#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Dave Liu19580e62007-09-18 12:37:57 +0800315
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hershberger8d858082011-10-11 23:57:18 -0500317 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
Dave Liu19580e62007-09-18 12:37:57 +0800318
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
320#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Dave Liu19580e62007-09-18 12:37:57 +0800321
322/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_HUSH_PARSER
Dave Liu19580e62007-09-18 12:37:57 +0800324
325/* Pass open firmware flat tree */
326#define CONFIG_OF_LIBFDT 1
327#define CONFIG_OF_BOARD_SETUP 1
Kim Phillips5b8bc602007-12-20 14:09:22 -0600328#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Dave Liu19580e62007-09-18 12:37:57 +0800329
330/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200331#define CONFIG_SYS_I2C
332#define CONFIG_SYS_I2C_FSL
333#define CONFIG_SYS_FSL_I2C_SPEED 400000
334#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
335#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
336#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
Dave Liu19580e62007-09-18 12:37:57 +0800337
338/*
339 * Config on-board RTC
340 */
341#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Dave Liu19580e62007-09-18 12:37:57 +0800343
344/*
345 * General PCI
346 * Addresses are mapped 1-1.
347 */
Joe Hershberger8d858082011-10-11 23:57:18 -0500348#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
349#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
350#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
352#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
353#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
354#define CONFIG_SYS_PCI_IO_BASE 0x00000000
355#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
356#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
Dave Liu19580e62007-09-18 12:37:57 +0800357
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200358#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
359#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
360#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
Dave Liu19580e62007-09-18 12:37:57 +0800361
Anton Vorontsov8b345572009-01-08 04:26:19 +0300362#define CONFIG_SYS_PCIE1_BASE 0xA0000000
363#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
364#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
365#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
366#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
367#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
368#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
369#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
370#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
371
372#define CONFIG_SYS_PCIE2_BASE 0xC0000000
373#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
374#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
375#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
376#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
377#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
378#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
379#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
380#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
381
Dave Liu19580e62007-09-18 12:37:57 +0800382#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000383#define CONFIG_PCI_INDIRECT_BRIDGE
Anton Vorontsov00f7bba2008-10-02 19:17:33 +0400384#ifndef __ASSEMBLY__
385extern int board_pci_host_broken(void);
386#endif
Kim Phillipsbe9b56d2009-07-23 14:09:38 -0500387#define CONFIG_PCIE
Dave Liu19580e62007-09-18 12:37:57 +0800388#define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */
389
Anton Vorontsov3bf1be32008-10-14 22:58:53 +0400390#define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */
391
Dave Liu19580e62007-09-18 12:37:57 +0800392#define CONFIG_PCI_PNP /* do pci plug-and-play */
393
394#undef CONFIG_EEPRO100
395#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200396#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
Dave Liu19580e62007-09-18 12:37:57 +0800397#endif /* CONFIG_PCI */
398
Dave Liu19580e62007-09-18 12:37:57 +0800399/*
400 * TSEC
401 */
402#define CONFIG_TSEC_ENET /* TSEC ethernet support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200403#define CONFIG_SYS_TSEC1_OFFSET 0x24000
Joe Hershberger8d858082011-10-11 23:57:18 -0500404#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200405#define CONFIG_SYS_TSEC2_OFFSET 0x25000
Joe Hershberger8d858082011-10-11 23:57:18 -0500406#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
Dave Liu19580e62007-09-18 12:37:57 +0800407
408/*
409 * TSEC ethernet configuration
410 */
411#define CONFIG_MII 1 /* MII PHY management */
412#define CONFIG_TSEC1 1
413#define CONFIG_TSEC1_NAME "eTSEC0"
414#define CONFIG_TSEC2 1
415#define CONFIG_TSEC2_NAME "eTSEC1"
416#define TSEC1_PHY_ADDR 2
417#define TSEC2_PHY_ADDR 3
Anton Vorontsov1da83a62008-10-02 18:32:25 +0400418#define TSEC1_PHY_ADDR_SGMII 8
419#define TSEC2_PHY_ADDR_SGMII 4
Dave Liu19580e62007-09-18 12:37:57 +0800420#define TSEC1_PHYIDX 0
421#define TSEC2_PHYIDX 0
422#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
423#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
424
425/* Options are: TSEC[0-1] */
426#define CONFIG_ETHPRIME "eTSEC1"
427
Dave Liu6f8c85e2008-03-26 22:56:36 +0800428/* SERDES */
429#define CONFIG_FSL_SERDES
430#define CONFIG_FSL_SERDES1 0xe3000
431#define CONFIG_FSL_SERDES2 0xe3100
432
Dave Liu19580e62007-09-18 12:37:57 +0800433/*
Dave Liu2eeb3e42008-03-26 22:57:19 +0800434 * SATA
435 */
436#define CONFIG_LIBATA
437#define CONFIG_FSL_SATA
438
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200439#define CONFIG_SYS_SATA_MAX_DEVICE 2
Dave Liu2eeb3e42008-03-26 22:57:19 +0800440#define CONFIG_SATA1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200441#define CONFIG_SYS_SATA1_OFFSET 0x18000
Joe Hershberger8d858082011-10-11 23:57:18 -0500442#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
443#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
Dave Liu2eeb3e42008-03-26 22:57:19 +0800444#define CONFIG_SATA2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200445#define CONFIG_SYS_SATA2_OFFSET 0x19000
Joe Hershberger8d858082011-10-11 23:57:18 -0500446#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
447#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
Dave Liu2eeb3e42008-03-26 22:57:19 +0800448
449#ifdef CONFIG_FSL_SATA
450#define CONFIG_LBA48
451#define CONFIG_CMD_SATA
452#define CONFIG_DOS_PARTITION
453#define CONFIG_CMD_EXT2
454#endif
455
456/*
Dave Liu19580e62007-09-18 12:37:57 +0800457 * Environment
458 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200459#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200460 #define CONFIG_ENV_IS_IN_FLASH 1
Joe Hershberger8d858082011-10-11 23:57:18 -0500461 #define CONFIG_ENV_ADDR \
462 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200463 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
464 #define CONFIG_ENV_SIZE 0x2000
Dave Liu19580e62007-09-18 12:37:57 +0800465#else
Joe Hershberger8d858082011-10-11 23:57:18 -0500466 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200467 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200468 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200469 #define CONFIG_ENV_SIZE 0x2000
Dave Liu19580e62007-09-18 12:37:57 +0800470#endif
471
472#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200473#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Dave Liu19580e62007-09-18 12:37:57 +0800474
475/*
476 * BOOTP options
477 */
478#define CONFIG_BOOTP_BOOTFILESIZE
479#define CONFIG_BOOTP_BOOTPATH
480#define CONFIG_BOOTP_GATEWAY
481#define CONFIG_BOOTP_HOSTNAME
482
483
484/*
485 * Command line configuration.
486 */
487#include <config_cmd_default.h>
488
489#define CONFIG_CMD_PING
490#define CONFIG_CMD_I2C
491#define CONFIG_CMD_MII
492#define CONFIG_CMD_DATE
493
494#if defined(CONFIG_PCI)
495 #define CONFIG_CMD_PCI
496#endif
497
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200498#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500499 #undef CONFIG_CMD_SAVEENV
Dave Liu19580e62007-09-18 12:37:57 +0800500 #undef CONFIG_CMD_LOADS
501#endif
502
503#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Kim Phillipsa059e902010-04-15 17:36:05 -0500504#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Dave Liu19580e62007-09-18 12:37:57 +0800505
506#undef CONFIG_WATCHDOG /* watchdog disabled */
507
Andy Fleminge1ac3872008-10-30 16:50:14 -0500508#define CONFIG_MMC 1
509
510#ifdef CONFIG_MMC
511#define CONFIG_FSL_ESDHC
Chenhui Zhaoa6da8b82011-01-04 17:23:05 +0800512#define CONFIG_FSL_ESDHC_PIN_MUX
Andy Fleminge1ac3872008-10-30 16:50:14 -0500513#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
514#define CONFIG_CMD_MMC
515#define CONFIG_GENERIC_MMC
516#define CONFIG_CMD_EXT2
517#define CONFIG_CMD_FAT
518#define CONFIG_DOS_PARTITION
519#endif
520
Dave Liu19580e62007-09-18 12:37:57 +0800521/*
522 * Miscellaneous configurable options
523 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200524#define CONFIG_SYS_LONGHELP /* undef to save memory */
525#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Dave Liu19580e62007-09-18 12:37:57 +0800526
527#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200528 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Dave Liu19580e62007-09-18 12:37:57 +0800529#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200530 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Dave Liu19580e62007-09-18 12:37:57 +0800531#endif
532
Joe Hershberger8d858082011-10-11 23:57:18 -0500533 /* Print Buffer Size */
534#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
535#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
536 /* Boot Argument Buffer Size */
537#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Dave Liu19580e62007-09-18 12:37:57 +0800538
539/*
540 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700541 * have to be in the first 256 MB of memory, since this is
Dave Liu19580e62007-09-18 12:37:57 +0800542 * the maximum mapped by the Linux kernel during initialization.
543 */
Joe Hershberger8d858082011-10-11 23:57:18 -0500544#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
Dave Liu19580e62007-09-18 12:37:57 +0800545
546/*
547 * Core HID Setup
548 */
Kim Phillips1a2e2032010-04-20 19:37:54 -0500549#define CONFIG_SYS_HID0_INIT 0x000000000
550#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
551 HID0_ENABLE_INSTRUCTION_CACHE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200552#define CONFIG_SYS_HID2 HID2_HBE
Dave Liu19580e62007-09-18 12:37:57 +0800553
554/*
Dave Liu19580e62007-09-18 12:37:57 +0800555 * MMU Setup
556 */
Becky Bruce31d82672008-05-08 19:02:12 -0500557#define CONFIG_HIGH_BATS 1 /* High BATs supported */
Dave Liu19580e62007-09-18 12:37:57 +0800558
559/* DDR: cache cacheable */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200560#define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE
561#define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
Dave Liu19580e62007-09-18 12:37:57 +0800562
Joe Hershberger8d858082011-10-11 23:57:18 -0500563#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500564 | BATL_PP_RW \
Joe Hershberger8d858082011-10-11 23:57:18 -0500565 | BATL_MEMCOHERENCE)
566#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \
567 | BATU_BL_256M \
568 | BATU_VS \
569 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200570#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
571#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
Dave Liu19580e62007-09-18 12:37:57 +0800572
Joe Hershberger8d858082011-10-11 23:57:18 -0500573#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500574 | BATL_PP_RW \
Joe Hershberger8d858082011-10-11 23:57:18 -0500575 | BATL_MEMCOHERENCE)
576#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \
577 | BATU_BL_256M \
578 | BATU_VS \
579 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200580#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
581#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
Dave Liu19580e62007-09-18 12:37:57 +0800582
583/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
Joe Hershberger8d858082011-10-11 23:57:18 -0500584#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500585 | BATL_PP_RW \
Joe Hershberger8d858082011-10-11 23:57:18 -0500586 | BATL_CACHEINHIBIT \
587 | BATL_GUARDEDSTORAGE)
588#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \
589 | BATU_BL_8M \
590 | BATU_VS \
591 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200592#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
593#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
Dave Liu19580e62007-09-18 12:37:57 +0800594
595/* BCSR: cache-inhibit and guarded */
Joe Hershberger8d858082011-10-11 23:57:18 -0500596#define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500597 | BATL_PP_RW \
Joe Hershberger8d858082011-10-11 23:57:18 -0500598 | BATL_CACHEINHIBIT \
599 | BATL_GUARDEDSTORAGE)
600#define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR \
601 | BATU_BL_128K \
602 | BATU_VS \
603 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200604#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
605#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
Dave Liu19580e62007-09-18 12:37:57 +0800606
607/* FLASH: icache cacheable, but dcache-inhibit and guarded */
Joe Hershberger8d858082011-10-11 23:57:18 -0500608#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500609 | BATL_PP_RW \
Joe Hershberger8d858082011-10-11 23:57:18 -0500610 | BATL_MEMCOHERENCE)
611#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \
612 | BATU_BL_32M \
613 | BATU_VS \
614 | BATU_VP)
615#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500616 | BATL_PP_RW \
Joe Hershberger8d858082011-10-11 23:57:18 -0500617 | BATL_CACHEINHIBIT \
618 | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200619#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
Dave Liu19580e62007-09-18 12:37:57 +0800620
621/* Stack in dcache: cacheable, no memory coherence */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500622#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
Joe Hershberger8d858082011-10-11 23:57:18 -0500623#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
624 | BATU_BL_128K \
625 | BATU_VS \
626 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200627#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
628#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
Dave Liu19580e62007-09-18 12:37:57 +0800629
630#ifdef CONFIG_PCI
631/* PCI MEM space: cacheable */
Joe Hershberger8d858082011-10-11 23:57:18 -0500632#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500633 | BATL_PP_RW \
Joe Hershberger8d858082011-10-11 23:57:18 -0500634 | BATL_MEMCOHERENCE)
635#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \
636 | BATU_BL_256M \
637 | BATU_VS \
638 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200639#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
640#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
Dave Liu19580e62007-09-18 12:37:57 +0800641/* PCI MMIO space: cache-inhibit and guarded */
Joe Hershberger8d858082011-10-11 23:57:18 -0500642#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500643 | BATL_PP_RW \
Joe Hershberger8d858082011-10-11 23:57:18 -0500644 | BATL_CACHEINHIBIT \
645 | BATL_GUARDEDSTORAGE)
646#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \
647 | BATU_BL_256M \
648 | BATU_VS \
649 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200650#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
651#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Dave Liu19580e62007-09-18 12:37:57 +0800652#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200653#define CONFIG_SYS_IBAT6L (0)
654#define CONFIG_SYS_IBAT6U (0)
655#define CONFIG_SYS_IBAT7L (0)
656#define CONFIG_SYS_IBAT7U (0)
657#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
658#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
659#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
660#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Dave Liu19580e62007-09-18 12:37:57 +0800661#endif
662
Dave Liu19580e62007-09-18 12:37:57 +0800663#if defined(CONFIG_CMD_KGDB)
664#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
Dave Liu19580e62007-09-18 12:37:57 +0800665#endif
666
667/*
668 * Environment Configuration
669 */
670
671#define CONFIG_ENV_OVERWRITE
672
673#if defined(CONFIG_TSEC_ENET)
674#define CONFIG_HAS_ETH0
Dave Liu19580e62007-09-18 12:37:57 +0800675#define CONFIG_HAS_ETH1
Dave Liu19580e62007-09-18 12:37:57 +0800676#endif
677
678#define CONFIG_BAUDRATE 115200
679
Kim Phillips79f516b2009-08-21 16:34:38 -0500680#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
Dave Liu19580e62007-09-18 12:37:57 +0800681
682#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
683#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
684
685#define CONFIG_EXTRA_ENV_SETTINGS \
Joe Hershberger8d858082011-10-11 23:57:18 -0500686 "netdev=eth0\0" \
687 "consoledev=ttyS0\0" \
688 "ramdiskaddr=1000000\0" \
689 "ramdiskfile=ramfs.83xx\0" \
690 "fdtaddr=780000\0" \
691 "fdtfile=mpc8379_mds.dtb\0" \
692 ""
Dave Liu19580e62007-09-18 12:37:57 +0800693
694#define CONFIG_NFSBOOTCOMMAND \
Joe Hershberger8d858082011-10-11 23:57:18 -0500695 "setenv bootargs root=/dev/nfs rw " \
696 "nfsroot=$serverip:$rootpath " \
697 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
698 "$netdev:off " \
699 "console=$consoledev,$baudrate $othbootargs;" \
700 "tftp $loadaddr $bootfile;" \
701 "tftp $fdtaddr $fdtfile;" \
702 "bootm $loadaddr - $fdtaddr"
Dave Liu19580e62007-09-18 12:37:57 +0800703
704#define CONFIG_RAMBOOTCOMMAND \
Joe Hershberger8d858082011-10-11 23:57:18 -0500705 "setenv bootargs root=/dev/ram rw " \
706 "console=$consoledev,$baudrate $othbootargs;" \
707 "tftp $ramdiskaddr $ramdiskfile;" \
708 "tftp $loadaddr $bootfile;" \
709 "tftp $fdtaddr $fdtfile;" \
710 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Dave Liu19580e62007-09-18 12:37:57 +0800711
712
713#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
714
715#endif /* __CONFIG_H */