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wdenk3d3befa2004-03-14 15:06:13 +00001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * (C) Copyright 2002
7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
8 *
9 * (C) Copyright 2003
10 * Texas Instruments, <www.ti.com>
11 * Kshitij Gupta <Kshitij@ti.com>
12 *
13 * (C) Copyright 2004
14 * ARM Ltd.
15 * Philippe Robin, <philippe.robin@arm.com>
16 *
17 * See file CREDITS for list of people who contributed to this
18 * project.
19 *
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 * MA 02111-1307 USA
34 */
35
36#include <common.h>
37
Wolfgang Denkd87080b2006-03-31 18:32:53 +020038DECLARE_GLOBAL_DATA_PTR;
39
wdenk3d3befa2004-03-14 15:06:13 +000040void flash__init (void);
41void ether__init (void);
42void peripheral_power_enable (void);
43
44#if defined(CONFIG_SHOW_BOOT_PROGRESS)
45void show_boot_progress(int progress)
46{
47 printf("Boot reached stage %d\n", progress);
48}
49#endif
50
51#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
52
53static inline void delay (unsigned long loops)
54{
55 __asm__ volatile ("1:\n"
56 "subs %0, %1, #1\n"
57 "bne 1b":"=r" (loops):"0" (loops));
58}
59
60/*
61 * Miscellaneous platform dependent initialisations
62 */
63
64int board_init (void)
65{
wdenk3d3befa2004-03-14 15:06:13 +000066 /*
67 * set clock frequency:
68 * VERSATILE_REFCLK is 32KHz
69 * VERSATILE_TIMCLK is 1MHz
70 */
71 *(volatile unsigned int *)(VERSATILE_SCTL_BASE) |=
72 ((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
73 (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel));
74
75 /* arch number of Versatile Board */
wdenk731215e2004-10-10 18:41:04 +000076 gd->bd->bi_arch_number = MACH_TYPE_VERSATILE_PB;
wdenk3d3befa2004-03-14 15:06:13 +000077
78 /* adress of boot parameters */
79 gd->bd->bi_boot_params = 0x00000100;
80
wdenkbc54f302004-07-11 18:10:30 +000081 gd->flags = 0;
82
wdenk3d3befa2004-03-14 15:06:13 +000083 icache_enable ();
84
85 flash__init ();
86 ether__init ();
87 return 0;
88}
89
90
91int misc_init_r (void)
92{
93 setenv("verify", "n");
94 return (0);
95}
96
97/******************************
98 Routine:
99 Description:
100******************************/
101void flash__init (void)
102{
103}
104/*************************************************************
105 Routine:ether__init
106 Description: take the Ethernet controller out of reset and wait
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200107 for the EEPROM load to complete.
wdenk3d3befa2004-03-14 15:06:13 +0000108*************************************************************/
109void ether__init (void)
110{
111}
112
113/******************************
114 Routine:
115 Description:
116******************************/
117int dram_init (void)
118{
119 return 0;
120}