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gerrit.cesnet.cz / github / trini / u-boot / e63e5904b48528f3f3cc98317df6fc62fab25bf9 / . / board / ti / sdp3430 / sdp.h
blob: 3526e946727faeb5ff370bb0167db65ae2d15ee8 [file] [log] [blame]
Tom Rixe63e5902009-10-17 12:41:06 -0500[diff] [blame^]1/*
2 * (C) Copyright 2004-2009
3 * Texas Instruments Incorporated
4 * Richard Woodruff <r-woodruff2@ti.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24#ifndef _BOARD_SDP_H_
25#define _BOARD_SDP_H_
26
27#define OFF_IN_PD 0
28#define OFF_OUT_PD 0
29
30/*
31 * IEN - Input Enable
32 * IDIS - Input Disable
33 * PTD - Pull type Down
34 * PTU - Pull type Up
35 * DIS - Pull type selection is inactive
36 * EN - Pull type selection is active
37 * M0 - Mode 0
38 * The commented string gives the final mux configuration for that pin
39 */
40#define MUX_SDP3430()\
41 /*SDRC*/\
42 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0))\
43 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0))\
44 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0))\
45 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0))\
46 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0))\
47 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0))\
48 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0))\
49 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0))\
50 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0))\
51 MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0))\
52 MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0))\
53 MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0))\
54 MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0))\
55 MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0))\
56 MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0))\
57 MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0))\
58 MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0))\
59 MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0))\
60 MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0))\
61 MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0))\
62 MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0))\
63 MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0))\
64 MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0))\
65 MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0))\
66 MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0))\
67 MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0))\
68 MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0))\
69 MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0))\
70 MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0))\
71 MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0))\
72 MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0))\
73 MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0))\
74 MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0))\
75 MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0))\
76 MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0))\
77 MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0))\
78 MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0))\
79 /*GPMC*/\
80 MUX_VAL(CP(GPMC_A1), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
81 MUX_VAL(CP(GPMC_A2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
82 MUX_VAL(CP(GPMC_A3), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
83 MUX_VAL(CP(GPMC_A4), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
84 MUX_VAL(CP(GPMC_A5), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
85 MUX_VAL(CP(GPMC_A6), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
86 MUX_VAL(CP(GPMC_A7), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
87 MUX_VAL(CP(GPMC_A8), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
88 MUX_VAL(CP(GPMC_A9), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
89 MUX_VAL(CP(GPMC_A10), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
90 MUX_VAL(CP(GPMC_D0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
91 MUX_VAL(CP(GPMC_D1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
92 MUX_VAL(CP(GPMC_D2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
93 MUX_VAL(CP(GPMC_D3), (OFF_IN_PD | IEN | PTD | DIS | M0))\
94 MUX_VAL(CP(GPMC_D4), (OFF_IN_PD | IEN | PTD | DIS | M0))\
95 MUX_VAL(CP(GPMC_D5), (OFF_IN_PD | IEN | PTD | DIS | M0))\
96 MUX_VAL(CP(GPMC_D6), (OFF_IN_PD | IEN | PTD | DIS | M0))\
97 MUX_VAL(CP(GPMC_D7), (OFF_IN_PD | IEN | PTD | DIS | M0))\
98 MUX_VAL(CP(GPMC_D8), (OFF_IN_PD | IEN | PTD | DIS | M0))\
99 MUX_VAL(CP(GPMC_D9), (OFF_IN_PD | IEN | PTD | DIS | M0))\
100 MUX_VAL(CP(GPMC_D10), (OFF_IN_PD | IEN | PTD | DIS | M0))\
101 MUX_VAL(CP(GPMC_D11), (OFF_IN_PD | IEN | PTD | DIS | M0))\
102 MUX_VAL(CP(GPMC_D12), (OFF_IN_PD | IEN | PTD | DIS | M0))\
103 MUX_VAL(CP(GPMC_D13), (OFF_IN_PD | IEN | PTD | DIS | M0))\
104 MUX_VAL(CP(GPMC_D14), (OFF_IN_PD | IEN | PTD | DIS | M0))\
105 MUX_VAL(CP(GPMC_D15), (OFF_IN_PD | IEN | PTD | DIS | M0))\
106 MUX_VAL(CP(GPMC_NCS0), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
107 MUX_VAL(CP(GPMC_NCS1), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
108 MUX_VAL(CP(GPMC_NCS2), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
109 MUX_VAL(CP(GPMC_NCS3), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
110 MUX_VAL(CP(GPMC_NCS4), (OFF_IN_PD | IEN | PTU | EN | M4)) /*G55-F_DIS*/\
111 MUX_VAL(CP(GPMC_NCS5), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G56T_EN*/\
112 MUX_VAL(CP(GPMC_NCS6), (OFF_IN_PD | IEN | PTD | DIS | M4))/*G57-AGPSP*/\
113 MUX_VAL(CP(GPMC_NCS7), (OFF_IN_PD | IEN | PTU | EN | M4))/*G58-WLNIQ*/\
114 MUX_VAL(CP(GPMC_CLK), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
115 MUX_VAL(CP(GPMC_NADV_ALE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
116 MUX_VAL(CP(GPMC_NOE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
117 MUX_VAL(CP(GPMC_NWE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
118 MUX_VAL(CP(GPMC_NBE0_CLE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
119 MUX_VAL(CP(GPMC_NBE1), (OFF_IN_PD | IEN | PTD | DIS | M4)) /*G61-BTST*/\
120 MUX_VAL(CP(GPMC_NWP), (OFF_IN_PD | IEN | PTD | DIS | M0))\
121 MUX_VAL(CP(GPMC_WAIT0), (OFF_IN_PD | IEN | PTU | EN | M0))\
122 MUX_VAL(CP(GPMC_WAIT1), (OFF_IN_PD | IEN | PTU | EN | M0))\
123 MUX_VAL(CP(GPMC_WAIT2), (OFF_IN_PD | IEN | PTU | EN | M4)) /*GPIO_64*/\
124 MUX_VAL(CP(GPMC_WAIT3), (OFF_IN_PD | IEN | PTU | EN | M4)) /*GPIO_65*/\
125 /*DSS*/\
126 MUX_VAL(CP(DSS_PCLK), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
127 MUX_VAL(CP(DSS_HSYNC), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
128 MUX_VAL(CP(DSS_VSYNC), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
129 MUX_VAL(CP(DSS_ACBIAS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
130 MUX_VAL(CP(DSS_DATA0), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
131 MUX_VAL(CP(DSS_DATA1), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
132 MUX_VAL(CP(DSS_DATA2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
133 MUX_VAL(CP(DSS_DATA3), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
134 MUX_VAL(CP(DSS_DATA4), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
135 MUX_VAL(CP(DSS_DATA5), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
136 MUX_VAL(CP(DSS_DATA6), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
137 MUX_VAL(CP(DSS_DATA7), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
138 MUX_VAL(CP(DSS_DATA8), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
139 MUX_VAL(CP(DSS_DATA9), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
140 MUX_VAL(CP(DSS_DATA10), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
141 MUX_VAL(CP(DSS_DATA11), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
142 MUX_VAL(CP(DSS_DATA12), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
143 MUX_VAL(CP(DSS_DATA13), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
144 MUX_VAL(CP(DSS_DATA14), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
145 MUX_VAL(CP(DSS_DATA15), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
146 MUX_VAL(CP(DSS_DATA16), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
147 MUX_VAL(CP(DSS_DATA17), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
148 MUX_VAL(CP(DSS_DATA18), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
149 MUX_VAL(CP(DSS_DATA19), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
150 MUX_VAL(CP(DSS_DATA20), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
151 MUX_VAL(CP(DSS_DATA21), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
152 MUX_VAL(CP(DSS_DATA22), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
153 MUX_VAL(CP(DSS_DATA23), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
154 /*CAMERA*/\
155 MUX_VAL(CP(CAM_HS), (OFF_IN_PD | IEN | PTU | EN | M0))\
156 MUX_VAL(CP(CAM_VS), (OFF_IN_PD | IEN | PTU | EN | M0))\
157 MUX_VAL(CP(CAM_XCLKA), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
158 MUX_VAL(CP(CAM_PCLK), (OFF_IN_PD | IEN | PTU | EN | M0))\
159 MUX_VAL(CP(CAM_FLD), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G98-C_RST*/\
160 MUX_VAL(CP(CAM_D0), (OFF_IN_PD | IEN | PTD | DIS | M2)) /*CAM_D0 */\
161 MUX_VAL(CP(CAM_D1), (OFF_IN_PD | IEN | PTD | DIS | M2)) /*CAM_D1 */\
162 MUX_VAL(CP(CAM_D2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
163 MUX_VAL(CP(CAM_D3), (OFF_IN_PD | IEN | PTD | DIS | M0))\
164 MUX_VAL(CP(CAM_D4), (OFF_IN_PD | IEN | PTD | DIS | M0))\
165 MUX_VAL(CP(CAM_D5), (OFF_IN_PD | IEN | PTD | DIS | M0))\
166 MUX_VAL(CP(CAM_D6), (OFF_IN_PD | IEN | PTD | DIS | M0))\
167 MUX_VAL(CP(CAM_D7), (OFF_IN_PD | IEN | PTD | DIS | M0))\
168 MUX_VAL(CP(CAM_D8), (OFF_IN_PD | IEN | PTD | DIS | M0))\
169 MUX_VAL(CP(CAM_D9), (OFF_IN_PD | IEN | PTD | DIS | M0))\
170 MUX_VAL(CP(CAM_D10), (OFF_IN_PD | IEN | PTD | DIS | M0))\
171 MUX_VAL(CP(CAM_D11), (OFF_IN_PD | IEN | PTD | DIS | M0))\
172 MUX_VAL(CP(CAM_XCLKB), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
173 MUX_VAL(CP(CAM_WEN), (OFF_IN_PD | IEN | PTD | DIS | M4)) /*GPIO_167*/\
174 MUX_VAL(CP(CAM_STROBE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
175 MUX_VAL(CP(CSI2_DX0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
176 MUX_VAL(CP(CSI2_DY0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
177 MUX_VAL(CP(CSI2_DX1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
178 MUX_VAL(CP(CSI2_DY1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
179 /*Audio InterfACe */\
180 MUX_VAL(CP(MCBSP2_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
181 MUX_VAL(CP(MCBSP2_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
182 MUX_VAL(CP(MCBSP2_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
183 MUX_VAL(CP(MCBSP2_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
184 /*Expansion Card */\
185 MUX_VAL(CP(MMC1_CLK), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
186 MUX_VAL(CP(MMC1_CMD), (OFF_IN_PD | IEN | PTU | EN | M0))\
187 MUX_VAL(CP(MMC1_DAT0), (OFF_IN_PD | IEN | PTU | EN | M0))\
188 MUX_VAL(CP(MMC1_DAT1), (OFF_IN_PD | IEN | PTU | EN | M0))\
189 MUX_VAL(CP(MMC1_DAT2), (OFF_IN_PD | IEN | PTU | EN | M0))\
190 MUX_VAL(CP(MMC1_DAT3), (OFF_IN_PD | IEN | PTU | EN | M0))\
191 MUX_VAL(CP(MMC1_DAT4), (OFF_IN_PD | IEN | PTU | EN | M0))\
192 MUX_VAL(CP(MMC1_DAT5), (OFF_IN_PD | IEN | PTU | EN | M0))\
193 MUX_VAL(CP(MMC1_DAT6), (OFF_IN_PD | IEN | PTU | EN | M0))\
194 MUX_VAL(CP(MMC1_DAT7), (OFF_IN_PD | IEN | PTU | EN | M0))\
195 /*Wireless LAN */\
196 MUX_VAL(CP(MMC2_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
197 MUX_VAL(CP(MMC2_CMD), (OFF_IN_PD | IEN | PTU | EN | M0))\
198 MUX_VAL(CP(MMC2_DAT0), (OFF_IN_PD | IEN | PTU | EN | M0))\
199 MUX_VAL(CP(MMC2_DAT1), (OFF_IN_PD | IEN | PTU | EN | M0))\
200 MUX_VAL(CP(MMC2_DAT2), (OFF_IN_PD | IEN | PTU | EN | M0))\
201 MUX_VAL(CP(MMC2_DAT3), (OFF_IN_PD | IEN | PTU | EN | M0))\
202 MUX_VAL(CP(MMC2_DAT4), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DRD0*/\
203 MUX_VAL(CP(MMC2_DAT5), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DRD1*/\
204 MUX_VAL(CP(MMC2_DAT6), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DCMD*/\
205 MUX_VAL(CP(MMC2_DAT7), (OFF_IN_PD | IEN | PTU | EN | M1))/*CLKIN*/\
206 /*Bluetooth*/\
207 MUX_VAL(CP(MCBSP3_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
208 MUX_VAL(CP(MCBSP3_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
209 MUX_VAL(CP(MCBSP3_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
210 MUX_VAL(CP(MCBSP3_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
211 MUX_VAL(CP(UART2_CTS), (OFF_IN_PD | IEN | PTU | EN | M0))\
212 MUX_VAL(CP(UART2_RTS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
213 MUX_VAL(CP(UART2_TX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
214 MUX_VAL(CP(UART2_RX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
215 /*Modem Interface */\
216 MUX_VAL(CP(UART1_TX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
217 MUX_VAL(CP(UART1_RTS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
218 MUX_VAL(CP(UART1_CTS), (OFF_IN_PD | IEN | PTU | DIS | M0))\
219 MUX_VAL(CP(UART1_RX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
220 MUX_VAL(CP(MCBSP4_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1DRX*/\
221 MUX_VAL(CP(MCBSP4_DR), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1FLGRX*/\
222 MUX_VAL(CP(MCBSP4_DX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1RDYRX*/\
223 MUX_VAL(CP(MCBSP4_FSX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1WAKE*/\
224 MUX_VAL(CP(MCBSP1_CLKR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
225 MUX_VAL(CP(MCBSP1_FSR), (OFF_OUT_PD | IDIS | PTU | EN | M4))/*G157BWP*/\
226 MUX_VAL(CP(MCBSP1_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
227 MUX_VAL(CP(MCBSP1_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
228 MUX_VAL(CP(MCBSP_CLKS), (OFF_IN_PD | IEN | PTU | DIS | M0))\
229 MUX_VAL(CP(MCBSP1_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
230 MUX_VAL(CP(MCBSP1_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
231 /*Serial Interface*/\
232 MUX_VAL(CP(UART3_CTS_RCTX), (OFF_IN_PD | IEN | PTD | EN | M0))\
233 MUX_VAL(CP(UART3_RTS_SD), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
234 MUX_VAL(CP(UART3_RX_IRRX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
235 MUX_VAL(CP(UART3_TX_IRTX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
236 MUX_VAL(CP(HSUSB0_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
237 MUX_VAL(CP(HSUSB0_STP), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
238 MUX_VAL(CP(HSUSB0_DIR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
239 MUX_VAL(CP(HSUSB0_NXT), (OFF_IN_PD | IEN | PTD | DIS | M0))\
240 MUX_VAL(CP(HSUSB0_DATA0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
241 MUX_VAL(CP(HSUSB0_DATA1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
242 MUX_VAL(CP(HSUSB0_DATA2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
243 MUX_VAL(CP(HSUSB0_DATA3), (OFF_IN_PD | IEN | PTD | DIS | M0))\
244 MUX_VAL(CP(HSUSB0_DATA4), (OFF_IN_PD | IEN | PTD | DIS | M0))\
245 MUX_VAL(CP(HSUSB0_DATA5), (OFF_IN_PD | IEN | PTD | DIS | M0))\
246 MUX_VAL(CP(HSUSB0_DATA6), (OFF_IN_PD | IEN | PTD | DIS | M0))\
247 MUX_VAL(CP(HSUSB0_DATA7), (OFF_IN_PD | IEN | PTD | DIS | M0))\
248 /* NOTE db: removed off-mode from I2C 1/2/3 ... external pullups!! */\
249 MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0))\
250 MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0))\
251 MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0))\
252 MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0))\
253 MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0))\
254 MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0))\
255 MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0))\
256 MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0))\
257 MUX_VAL(CP(HDQ_SIO), (OFF_IN_PD | IEN | PTU | EN | M0))\
258 MUX_VAL(CP(MCSPI1_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
259 MUX_VAL(CP(MCSPI1_SIMO), (OFF_IN_PD | IEN | PTD | DIS | M0))\
260 MUX_VAL(CP(MCSPI1_SOMI), (OFF_IN_PD | IEN | PTD | DIS | M0))\
261 MUX_VAL(CP(MCSPI1_CS0), (OFF_IN_PD | IEN | PTD | EN | M0))\
262 MUX_VAL(CP(MCSPI1_CS1), (OFF_OUT_PD | IDIS | PTD | EN | M0))\
263 MUX_VAL(CP(MCSPI1_CS2), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G176*/\
264 MUX_VAL(CP(MCSPI1_CS3), (OFF_IN_PD | IEN | PTD | EN | M0))\
265 MUX_VAL(CP(MCSPI2_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
266 MUX_VAL(CP(MCSPI2_SIMO), (OFF_IN_PD | IEN | PTD | DIS | M0))\
267 MUX_VAL(CP(MCSPI2_SOMI), (OFF_IN_PD | IEN | PTD | DIS | M0))\
268 MUX_VAL(CP(MCSPI2_CS0), (OFF_IN_PD | IEN | PTD | EN | M0))\
269 MUX_VAL(CP(MCSPI2_CS1), (OFF_IN_PD | IEN | PTD | EN | M0))\
270 /*Control and debug */\
271 MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0))\
272 MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0))\
273 MUX_VAL(CP(SYS_NIRQ), (OFF_IN_PD | IEN | PTU | EN | M0))\
274 MUX_VAL(CP(SYS_BOOT0), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G2PENIRQ*/\
275 MUX_VAL(CP(SYS_BOOT1), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*GPIO_3 */\
276 MUX_VAL(CP(SYS_BOOT2), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G4MMC1WP*/\
277 MUX_VAL(CP(SYS_BOOT3), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G5LCDENV*/\
278 MUX_VAL(CP(SYS_BOOT4), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G6LANINT*/\
279 MUX_VAL(CP(SYS_BOOT5), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G7MMC2WP*/\
280 MUX_VAL(CP(SYS_BOOT6), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G8ENBKL*/\
281 MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0))\
282 MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0))\
283 MUX_VAL(CP(SYS_CLKOUT2), (OFF_IN_PD | IEN | PTU | EN | M4))/*GPIO_186*/\
284 MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0))\
285 MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0))\
286 MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0))\
287 MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0))\
288 MUX_VAL(CP(JTAG_EMU0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
289 MUX_VAL(CP(JTAG_EMU1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
290 MUX_VAL(CP(ETK_CLK_ES2), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
291 MUX_VAL(CP(ETK_CTL_ES2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
292 MUX_VAL(CP(ETK_D0_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*USB1TLD0*/\
293 MUX_VAL(CP(ETK_D1_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SPI3_CS0*/\
294 MUX_VAL(CP(ETK_D2_ES2), (OFF_IN_PD | IEN | PTD | EN | M1))/*USB1TLD2*/\
295 MUX_VAL(CP(ETK_D3_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*USB1TLD7*/\
296 MUX_VAL(CP(ETK_D4_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
297 MUX_VAL(CP(ETK_D5_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
298 MUX_VAL(CP(ETK_D6_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
299 MUX_VAL(CP(ETK_D7_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
300 MUX_VAL(CP(ETK_D8_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
301 MUX_VAL(CP(ETK_D9_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
302 MUX_VAL(CP(ETK_D10_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
303 MUX_VAL(CP(ETK_D11_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
304 MUX_VAL(CP(ETK_D12_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
305 MUX_VAL(CP(ETK_D13_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
306 MUX_VAL(CP(ETK_D14_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
307 MUX_VAL(CP(ETK_D15_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
308 /*Die to Die */\
309 MUX_VAL(CP(D2D_MCAD0), (OFF_IN_PD | IEN | PTD | EN | M0))\
310 MUX_VAL(CP(D2D_MCAD1), (OFF_IN_PD | IEN | PTD | EN | M0))\
311 MUX_VAL(CP(D2D_MCAD2), (OFF_IN_PD | IEN | PTD | EN | M0))\
312 MUX_VAL(CP(D2D_MCAD3), (OFF_IN_PD | IEN | PTD | EN | M0))\
313 MUX_VAL(CP(D2D_MCAD4), (OFF_IN_PD | IEN | PTD | EN | M0))\
314 MUX_VAL(CP(D2D_MCAD5), (OFF_IN_PD | IEN | PTD | EN | M0))\
315 MUX_VAL(CP(D2D_MCAD6), (OFF_IN_PD | IEN | PTD | EN | M0))\
316 MUX_VAL(CP(D2D_MCAD7), (OFF_IN_PD | IEN | PTD | EN | M0))\
317 MUX_VAL(CP(D2D_MCAD8), (OFF_IN_PD | IEN | PTD | EN | M0))\
318 MUX_VAL(CP(D2D_MCAD9), (OFF_IN_PD | IEN | PTD | EN | M0))\
319 MUX_VAL(CP(D2D_MCAD10), (OFF_IN_PD | IEN | PTD | EN | M0))\
320 MUX_VAL(CP(D2D_MCAD11), (OFF_IN_PD | IEN | PTD | EN | M0))\
321 MUX_VAL(CP(D2D_MCAD12), (OFF_IN_PD | IEN | PTD | EN | M0))\
322 MUX_VAL(CP(D2D_MCAD13), (OFF_IN_PD | IEN | PTD | EN | M0))\
323 MUX_VAL(CP(D2D_MCAD14), (OFF_IN_PD | IEN | PTD | EN | M0))\
324 MUX_VAL(CP(D2D_MCAD15), (OFF_IN_PD | IEN | PTD | EN | M0))\
325 MUX_VAL(CP(D2D_MCAD16), (OFF_IN_PD | IEN | PTD | EN | M0))\
326 MUX_VAL(CP(D2D_MCAD17), (OFF_IN_PD | IEN | PTD | EN | M0))\
327 MUX_VAL(CP(D2D_MCAD18), (OFF_IN_PD | IEN | PTD | EN | M0))\
328 MUX_VAL(CP(D2D_MCAD19), (OFF_IN_PD | IEN | PTD | EN | M0))\
329 MUX_VAL(CP(D2D_MCAD20), (OFF_IN_PD | IEN | PTD | EN | M0))\
330 MUX_VAL(CP(D2D_MCAD21), (OFF_IN_PD | IEN | PTD | EN | M0))\
331 MUX_VAL(CP(D2D_MCAD22), (OFF_IN_PD | IEN | PTD | EN | M0))\
332 MUX_VAL(CP(D2D_MCAD23), (OFF_IN_PD | IEN | PTD | EN | M0))\
333 MUX_VAL(CP(D2D_MCAD24), (OFF_IN_PD | IEN | PTD | EN | M0))\
334 MUX_VAL(CP(D2D_MCAD25), (OFF_IN_PD | IEN | PTD | EN | M0))\
335 MUX_VAL(CP(D2D_MCAD26), (OFF_IN_PD | IEN | PTD | EN | M0))\
336 MUX_VAL(CP(D2D_MCAD27), (OFF_IN_PD | IEN | PTD | EN | M0))\
337 MUX_VAL(CP(D2D_MCAD28), (OFF_IN_PD | IEN | PTD | EN | M0))\
338 MUX_VAL(CP(D2D_MCAD29), (OFF_IN_PD | IEN | PTD | EN | M0))\
339 MUX_VAL(CP(D2D_MCAD30), (OFF_IN_PD | IEN | PTD | EN | M0))\
340 MUX_VAL(CP(D2D_MCAD31), (OFF_IN_PD | IEN | PTD | EN | M0))\
341 MUX_VAL(CP(D2D_MCAD32), (OFF_IN_PD | IEN | PTD | EN | M0))\
342 MUX_VAL(CP(D2D_MCAD33), (OFF_IN_PD | IEN | PTD | EN | M0))\
343 MUX_VAL(CP(D2D_MCAD34), (OFF_IN_PD | IEN | PTD | EN | M0))\
344 MUX_VAL(CP(D2D_MCAD35), (OFF_IN_PD | IEN | PTD | EN | M0))\
345 MUX_VAL(CP(D2D_MCAD36), (OFF_IN_PD | IEN | PTD | EN | M0))\
346 MUX_VAL(CP(D2D_CLK26MI), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
347 MUX_VAL(CP(D2D_NRESPWRON), (OFF_OUT_PD | IEN | PTD | EN | M0))\
348 MUX_VAL(CP(D2D_NRESWARM), (OFF_IN_PD | IEN | PTU | EN | M0))\
349 MUX_VAL(CP(D2D_ARM9NIRQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
350 MUX_VAL(CP(D2D_UMA2P6FIQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
351 MUX_VAL(CP(D2D_SPINT), (OFF_IN_PD | IEN | PTD | EN | M0))\
352 MUX_VAL(CP(D2D_FRINT), (OFF_IN_PD | IEN | PTD | EN | M0))\
353 MUX_VAL(CP(D2D_DMAREQ0), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
354 MUX_VAL(CP(D2D_DMAREQ1), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
355 MUX_VAL(CP(D2D_DMAREQ2), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
356 MUX_VAL(CP(D2D_DMAREQ3), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
357 MUX_VAL(CP(D2D_N3GTRST), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
358 MUX_VAL(CP(D2D_N3GTDI), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
359 MUX_VAL(CP(D2D_N3GTDO), (OFF_IN_PD | IEN | PTD | DIS | M0))\
360 MUX_VAL(CP(D2D_N3GTMS), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
361 MUX_VAL(CP(D2D_N3GTCK), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
362 MUX_VAL(CP(D2D_N3GRTCK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
363 MUX_VAL(CP(D2D_MSTDBY), (OFF_IN_PD | IEN | PTU | EN | M0))\
364 MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0))\
365 MUX_VAL(CP(D2D_IDLEREQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
366 MUX_VAL(CP(D2D_IDLEACK), (OFF_IN_PD | IEN | PTU | EN | M0))\
367 MUX_VAL(CP(D2D_MWRITE), (OFF_IN_PD | IEN | PTD | DIS | M0))\
368 MUX_VAL(CP(D2D_SWRITE), (OFF_IN_PD | IEN | PTD | DIS | M0))\
369 MUX_VAL(CP(D2D_MREAD), (OFF_IN_PD | IEN | PTD | DIS | M0))\
370 MUX_VAL(CP(D2D_SREAD), (OFF_IN_PD | IEN | PTD | DIS | M0))\
371 MUX_VAL(CP(D2D_MBUSFLAG), (OFF_IN_PD | IEN | PTD | DIS | M0))\
372 MUX_VAL(CP(D2D_SBUSFLAG), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
373 MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0))\
374 MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*SDRC_CKE1 NOT USED*/
375
376/*
377 * GPMC Timing definitions for SDP3430
378 * at L3 = 166Mhz
379 */
380
381/* Timing definitions for GPMC controller for Sibley NOR */
382#define SDP3430_NOR_GPMC_CONF1 0x00001200
383#define SDP3430_NOR_GPMC_CONF2 0x001F1F00
384#define SDP3430_NOR_GPMC_CONF3 0x00080802
385#define SDP3430_NOR_GPMC_CONF4 0x1C091C09
386#define SDP3430_NOR_GPMC_CONF5 0x01131F1F
387#define SDP3430_NOR_GPMC_CONF6 0x1F0F03C2
388
389/*
390 * Timing definitions for GPMC controller for Debug Board
391 * Debug board contains access to ethernet and DIP Switch setting
392 * information etc.
393 */
394#define SDP3430_DEBUG_GPMC_CONF1 0x00611200
395#define SDP3430_DEBUG_GPMC_CONF2 0x001F1F01
396#define SDP3430_DEBUG_GPMC_CONF3 0x00080803
397#define SDP3430_DEBUG_GPMC_CONF4 0x1D091D09
398#define SDP3430_DEBUG_GPMC_CONF5 0x041D1F1F
399#define SDP3430_DEBUG_GPMC_CONF6 0x1D0904C4
400
401/* Timing defintions for GPMC OneNAND */
402#define SDP3430_ONENAND_GPMC_CONF1 0x00001200
403#define SDP3430_ONENAND_GPMC_CONF2 0x000F0F01
404#define SDP3430_ONENAND_GPMC_CONF3 0x00030301
405#define SDP3430_ONENAND_GPMC_CONF4 0x0F040F04
406#define SDP3430_ONENAND_GPMC_CONF5 0x010F1010
407#define SDP3430_ONENAND_GPMC_CONF6 0x1F060000
408
409/* GPMC definitions for GPMC NAND */
410#define SDP3430_NAND_GPMC_CONF1 0x00000800
411#define SDP3430_NAND_GPMC_CONF2 0x00141400
412#define SDP3430_NAND_GPMC_CONF3 0x00141400
413#define SDP3430_NAND_GPMC_CONF4 0x0F010F01
414#define SDP3430_NAND_GPMC_CONF5 0x010C1414
415#define SDP3430_NAND_GPMC_CONF6 0x1F040A80
416
417#endif /* _BOARD_SDP_H_ */