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wdenk4a9cbbe2002-08-27 09:48:53 +00001/*
2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <watchdog.h>
26
27#include <mpc8xx.h>
28#include <commproc.h>
29
30#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH)
31void cpm_load_patch (volatile immap_t * immr);
32#endif
33
34/*
35 * Breath some life into the CPU...
36 *
37 * Set up the memory map,
38 * initialize a bunch of registers,
39 * initialize the UPM's
40 */
41void cpu_init_f (volatile immap_t * immr)
42{
43#ifndef CONFIG_MBX
44 volatile memctl8xx_t *memctl = &immr->im_memctl;
wdenkc178d3d2004-01-24 20:25:54 +000045# ifdef CFG_PLPRCR
wdenk180d3f72004-01-04 16:28:35 +000046 ulong mfmask;
wdenkc178d3d2004-01-24 20:25:54 +000047# endif
wdenk4a9cbbe2002-08-27 09:48:53 +000048#endif
wdenk3bac3512003-03-12 10:41:04 +000049 ulong reg;
wdenk4a9cbbe2002-08-27 09:48:53 +000050
51 /* SYPCR - contains watchdog control (11-9) */
52
53 immr->im_siu_conf.sc_sypcr = CFG_SYPCR;
54
55#if defined(CONFIG_WATCHDOG)
56 reset_8xx_watchdog (immr);
57#endif /* CONFIG_WATCHDOG */
58
59 /* SIUMCR - contains debug pin configuration (11-6) */
wdenkdc7c9a12003-03-26 06:55:25 +000060#ifndef CONFIG_SVM_SC8xx
wdenk4a9cbbe2002-08-27 09:48:53 +000061 immr->im_siu_conf.sc_siumcr |= CFG_SIUMCR;
wdenkdc7c9a12003-03-26 06:55:25 +000062#else
63 immr->im_siu_conf.sc_siumcr = CFG_SIUMCR;
64#endif
wdenk4a9cbbe2002-08-27 09:48:53 +000065 /* initialize timebase status and control register (11-26) */
66 /* unlock TBSCRK */
67
68 immr->im_sitk.sitk_tbscrk = KAPWR_KEY;
69 immr->im_sit.sit_tbscr = CFG_TBSCR;
70
71 /* initialize the PIT (11-31) */
72
73 immr->im_sitk.sitk_piscrk = KAPWR_KEY;
74 immr->im_sit.sit_piscr = CFG_PISCR;
75
wdenk1cb8e982003-03-06 21:55:29 +000076 /* System integration timers. Don't change EBDF! (15-27) */
77
78 immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
79 reg = immr->im_clkrst.car_sccr;
80 reg &= SCCR_MASK;
81 reg |= CFG_SCCR;
82 immr->im_clkrst.car_sccr = reg;
83
wdenk4a9cbbe2002-08-27 09:48:53 +000084 /* PLL (CPU clock) settings (15-30) */
85
86 immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
87
88#ifndef CONFIG_MBX /* MBX board does things different */
89
90 /* If CFG_PLPRCR (set in the various *_config.h files) tries to
91 * set the MF field, then just copy CFG_PLPRCR over car_plprcr,
wdenk180d3f72004-01-04 16:28:35 +000092 * otherwise OR in CFG_PLPRCR so we do not change the current MF
wdenk4a9cbbe2002-08-27 09:48:53 +000093 * field value.
wdenk180d3f72004-01-04 16:28:35 +000094 *
95 * For newer (starting MPC866) chips PLPRCR layout is different.
wdenk4a9cbbe2002-08-27 09:48:53 +000096 */
wdenkc178d3d2004-01-24 20:25:54 +000097#ifdef CFG_PLPRCR
wdenk180d3f72004-01-04 16:28:35 +000098 if (get_immr(0xFFFF) >= MPC8xx_NEW_CLK)
99 mfmask = PLPRCR_MFACT_MSK;
100 else
101 mfmask = PLPRCR_MF_MSK;
102
103 if ((CFG_PLPRCR & mfmask) != 0)
104 reg = CFG_PLPRCR; /* reset control bits */
105 else {
106 reg = immr->im_clkrst.car_plprcr;
107 reg &= mfmask; /* isolate MF-related fields */
108 reg |= CFG_PLPRCR; /* reset control bits */
109 }
wdenk4a9cbbe2002-08-27 09:48:53 +0000110 immr->im_clkrst.car_plprcr = reg;
wdenkc178d3d2004-01-24 20:25:54 +0000111#endif
wdenk4a9cbbe2002-08-27 09:48:53 +0000112
wdenk4a9cbbe2002-08-27 09:48:53 +0000113 /*
114 * Memory Controller:
115 */
116
117 /* perform BR0 reset that MPC850 Rev. A can't guarantee */
118 reg = memctl->memc_br0;
119 reg &= BR_PS_MSK; /* Clear everything except Port Size bits */
120 reg |= BR_V; /* then add just the "Bank Valid" bit */
121 memctl->memc_br0 = reg;
122
123 /* Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at
124 * preliminary addresses - these have to be modified later
125 * when FLASH size has been determined
126 *
127 * Depending on the size of the memory region defined by
128 * CFG_OR0_REMAP some boards (wide address mask) allow to map the
129 * CFG_MONITOR_BASE, while others (narrower address mask) can't
130 * map CFG_MONITOR_BASE.
131 *
132 * For example, for CONFIG_IVMS8, the CFG_MONITOR_BASE is
133 * 0xff000000, but CFG_OR0_REMAP's address mask is 0xfff80000.
134 *
135 * If BR0 wasn't loaded with address base 0xff000000, then BR0's
136 * base address remains as 0x00000000. However, the address mask
137 * have been narrowed to 512Kb, so CFG_MONITOR_BASE wasn't mapped
138 * into the Bank0.
139 *
140 * This is why CONFIG_IVMS8 and similar boards must load BR0 with
141 * CFG_BR0_PRELIM in advance.
142 *
143 * [Thanks to Michael Liao for this explanation.
144 * I owe him a free beer. - wd]
145 */
146
wdenk0cb61d72003-08-30 00:05:50 +0000147#if defined(CONFIG_ADDERII) || \
148 defined(CONFIG_GTH) || \
wdenk4a9cbbe2002-08-27 09:48:53 +0000149 defined(CONFIG_HERMES) || \
150 defined(CONFIG_ICU862) || \
151 defined(CONFIG_IP860) || \
152 defined(CONFIG_IVML24) || \
153 defined(CONFIG_IVMS8) || \
154 defined(CONFIG_LWMON) || \
155 defined(CONFIG_MHPC) || \
156 defined(CONFIG_PCU_E) || \
157 defined(CONFIG_R360MPI) || \
wdenk7e780362004-04-08 22:31:29 +0000158 defined(CONFIG_RMU) || \
wdenk4a9cbbe2002-08-27 09:48:53 +0000159 defined(CONFIG_RPXCLASSIC) || \
160 defined(CONFIG_RPXLITE) || \
wdenkb028f712003-12-07 21:39:28 +0000161 defined(CONFIG_SPD823TS)
wdenk4a9cbbe2002-08-27 09:48:53 +0000162
163 memctl->memc_br0 = CFG_BR0_PRELIM;
164#endif
165
166#if defined(CFG_OR0_REMAP)
167 memctl->memc_or0 = CFG_OR0_REMAP;
168#endif
169#if defined(CFG_OR1_REMAP)
170 memctl->memc_or1 = CFG_OR1_REMAP;
171#endif
172#if defined(CFG_OR5_REMAP)
173 memctl->memc_or5 = CFG_OR5_REMAP;
174#endif
175
176 /* now restrict to preliminary range */
177 memctl->memc_br0 = CFG_BR0_PRELIM;
178 memctl->memc_or0 = CFG_OR0_PRELIM;
179
180#if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM))
181 memctl->memc_or1 = CFG_OR1_PRELIM;
182 memctl->memc_br1 = CFG_BR1_PRELIM;
183#endif
184
185#if defined(CONFIG_IP860) /* disable CS0 now that Flash is mapped on CS1 */
186 memctl->memc_br0 = 0;
187#endif
188
189#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
190 memctl->memc_or2 = CFG_OR2_PRELIM;
191 memctl->memc_br2 = CFG_BR2_PRELIM;
192#endif
193
194#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
195 memctl->memc_or3 = CFG_OR3_PRELIM;
196 memctl->memc_br3 = CFG_BR3_PRELIM;
197#endif
198
199#if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM)
200 memctl->memc_or4 = CFG_OR4_PRELIM;
201 memctl->memc_br4 = CFG_BR4_PRELIM;
202#endif
203
204#if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM)
205 memctl->memc_or5 = CFG_OR5_PRELIM;
206 memctl->memc_br5 = CFG_BR5_PRELIM;
207#endif
208
209#if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM)
210 memctl->memc_or6 = CFG_OR6_PRELIM;
211 memctl->memc_br6 = CFG_BR6_PRELIM;
212#endif
213
214#if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM)
215 memctl->memc_or7 = CFG_OR7_PRELIM;
216 memctl->memc_br7 = CFG_BR7_PRELIM;
217#endif
218
219#endif /* ! CONFIG_MBX */
220
221 /*
222 * Reset CPM
223 */
224 immr->im_cpm.cp_cpcr = CPM_CR_RST | CPM_CR_FLG;
225 do { /* Spin until command processed */
226 __asm__ ("eieio");
227 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
228
229#ifdef CONFIG_MBX
230 /*
231 * on the MBX, things are a little bit different:
232 * - we need to read the VPD to get board information
233 * - the plprcr is set up dynamically
234 * - the memory controller is set up dynamically
235 */
236 mbx_init ();
237#endif /* CONFIG_MBX */
238
239#ifdef CONFIG_RPXCLASSIC
240 rpxclassic_init ();
241#endif
242
wdenke63c8ee2004-06-09 21:04:48 +0000243#if defined(CONFIG_RPXLITE) && defined(CFG_ENV_IS_IN_NVRAM)
244 rpxlite_init ();
245#endif
246
wdenk4a9cbbe2002-08-27 09:48:53 +0000247#ifdef CFG_RCCR /* must be done before cpm_load_patch() */
248 /* write config value */
249 immr->im_cpm.cp_rccr = CFG_RCCR;
250#endif
251
252#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH)
253 cpm_load_patch (immr); /* load mpc8xx microcode patch */
254#endif
255}
256
257/*
258 * initialize higher level parts of CPU like timers
259 */
260int cpu_init_r (void)
261{
262#if defined(CFG_RTCSC) || defined(CFG_RMDS)
263 DECLARE_GLOBAL_DATA_PTR;
264
265 bd_t *bd = gd->bd;
266 volatile immap_t *immr = (volatile immap_t *) (bd->bi_immr_base);
267#endif
268
269#ifdef CFG_RTCSC
270 /* Unlock RTSC register */
271 immr->im_sitk.sitk_rtcsck = KAPWR_KEY;
272 /* write config value */
273 immr->im_sit.sit_rtcsc = CFG_RTCSC;
274#endif
275
276#ifdef CFG_RMDS
277 /* write config value */
278 immr->im_cpm.cp_rmds = CFG_RMDS;
279#endif
280 return (0);
281}