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Stefano Babic64fdf452010-01-20 18:19:32 +01001/*
2 * (C) Copyright 2007
3 * Sascha Hauer, Pengutronix
4 *
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Stefano Babic64fdf452010-01-20 18:19:32 +01008 */
9
10#include <common.h>
11#include <asm/io.h>
Stefano Babic782bb0d2012-02-06 12:52:36 +010012#include <div64.h>
Stefano Babic64fdf452010-01-20 18:19:32 +010013#include <asm/arch/imx-regs.h>
Benoît Thébaudeau833b6432012-09-27 10:19:58 +000014#include <asm/arch/clock.h>
Ye.Li1a1f7952014-10-30 18:20:55 +080015#include <asm/arch/sys_proto.h>
Stefano Babic64fdf452010-01-20 18:19:32 +010016
17/* General purpose timers registers */
18struct mxc_gpt {
19 unsigned int control;
20 unsigned int prescaler;
21 unsigned int status;
22 unsigned int nouse[6];
23 unsigned int counter;
24};
25
26static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
27
28/* General purpose timers bitfields */
Jason Liu18936ee2011-11-25 00:18:01 +000029#define GPTCR_SWR (1 << 15) /* Software reset */
Ye.Li1a1f7952014-10-30 18:20:55 +080030#define GPTCR_24MEN (1 << 10) /* Enable 24MHz clock input */
Jason Liu18936ee2011-11-25 00:18:01 +000031#define GPTCR_FRR (1 << 9) /* Freerun / restart */
Ye.Li1a1f7952014-10-30 18:20:55 +080032#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source 32khz */
33#define GPTCR_CLKSOURCE_OSC (5 << 6) /* Clock source OSC */
34#define GPTCR_CLKSOURCE_PRE (1 << 6) /* Clock source PRECLK */
35#define GPTCR_CLKSOURCE_MASK (0x7 << 6)
Jason Liu18936ee2011-11-25 00:18:01 +000036#define GPTCR_TEN 1 /* Timer enable */
Stefano Babic64fdf452010-01-20 18:19:32 +010037
Ye.Li1a1f7952014-10-30 18:20:55 +080038#define GPTPR_PRESCALER24M_SHIFT 12
39#define GPTPR_PRESCALER24M_MASK (0xF << GPTPR_PRESCALER24M_SHIFT)
40
Stefano Babicdb106ef2011-01-21 21:16:15 +010041DECLARE_GLOBAL_DATA_PTR;
42
Ye.Li1a1f7952014-10-30 18:20:55 +080043static inline int gpt_has_clk_source_osc(void)
44{
45#if defined(CONFIG_MX6)
Peng Fan27cd0da2016-05-23 18:35:56 +080046 if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) ||
Peng Fan988acd22016-08-11 14:02:42 +080047 is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul() ||
Peng Fanfddac802016-12-11 19:24:23 +080048 is_mx6ull() || is_mx6sll())
Ye.Li1a1f7952014-10-30 18:20:55 +080049 return 1;
50
51 return 0;
52#else
53 return 0;
54#endif
55}
56
57static inline ulong gpt_get_clk(void)
58{
59#ifdef CONFIG_MXC_GPT_HCLK
60 if (gpt_has_clk_source_osc())
61 return MXC_HCLK >> 3;
62 else
63 return mxc_get_clock(MXC_IPG_PERCLK);
64#else
65 return MXC_CLK32;
66#endif
67}
Stefano Babic782bb0d2012-02-06 12:52:36 +010068
Stefano Babic64fdf452010-01-20 18:19:32 +010069int timer_init(void)
70{
71 int i;
72
73 /* setup GP Timer 1 */
74 __raw_writel(GPTCR_SWR, &cur_gpt->control);
75
76 /* We have no udelay by now */
77 for (i = 0; i < 100; i++)
78 __raw_writel(0, &cur_gpt->control);
79
Stefano Babic64fdf452010-01-20 18:19:32 +010080 i = __raw_readl(&cur_gpt->control);
Ye.Li1a1f7952014-10-30 18:20:55 +080081 i &= ~GPTCR_CLKSOURCE_MASK;
82
83#ifdef CONFIG_MXC_GPT_HCLK
84 if (gpt_has_clk_source_osc()) {
85 i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
86
Peng Fanfddac802016-12-11 19:24:23 +080087 /*
88 * For DL/S, SX, UL, ULL, SLL set 24Mhz OSC
89 * Enable bit and prescaler
90 */
91 if (is_mx6sdl() || is_mx6sx() || is_mx6ul() || is_mx6ull() ||
92 is_mx6sll()) {
Ye.Li1a1f7952014-10-30 18:20:55 +080093 i |= GPTCR_24MEN;
94
95 /* Produce 3Mhz clock */
96 __raw_writel((7 << GPTPR_PRESCALER24M_SHIFT),
97 &cur_gpt->prescaler);
98 }
99 } else {
100 i |= GPTCR_CLKSOURCE_PRE | GPTCR_TEN;
101 }
102#else
103 __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */
104 i |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
105#endif
106 __raw_writel(i, &cur_gpt->control);
Stefano Babic64fdf452010-01-20 18:19:32 +0100107
Knut Wohlrab982a3c42013-03-04 04:16:02 +0000108 gd->arch.tbl = __raw_readl(&cur_gpt->counter);
109 gd->arch.tbu = 0;
Graeme Russ17659d72011-07-15 02:21:14 +0000110
111 return 0;
Stefano Babic64fdf452010-01-20 18:19:32 +0100112}
113
Peng Fan2bb01482015-08-26 15:40:58 +0800114unsigned long timer_read_counter(void)
Stefano Babic782bb0d2012-02-06 12:52:36 +0100115{
Peng Fan2bb01482015-08-26 15:40:58 +0800116 return __raw_readl(&cur_gpt->counter); /* current tick value */
Stefano Babic782bb0d2012-02-06 12:52:36 +0100117}
Stefano Babic64fdf452010-01-20 18:19:32 +0100118
Stefano Babic782bb0d2012-02-06 12:52:36 +0100119/*
120 * This function is derived from PowerPC code (timebase clock frequency).
121 * On ARM it returns the number of timer ticks per second.
122 */
123ulong get_tbclk(void)
124{
Ye.Li1a1f7952014-10-30 18:20:55 +0800125 return gpt_get_clk();
Stefano Babic64fdf452010-01-20 18:19:32 +0100126}
Peng Fan436baaa2016-08-25 19:03:17 +0200127
128/*
129 * This function is intended for SHORT delays only.
130 * It will overflow at around 10 seconds @ 400MHz,
131 * or 20 seconds @ 200MHz.
132 */
133unsigned long usec2ticks(unsigned long _usec)
134{
135 unsigned long long usec = _usec;
136
137 usec *= get_tbclk();
138 usec += 999999;
139 do_div(usec, 1000000);
140
141 return usec;
142}