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Alex Nemirovsky7d706a82020-01-30 12:34:59 -08001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2020 Cortina Access Inc.
4 *
Alex Nemirovskyc34a9272021-01-14 13:34:13 -08005 * Configuration for Cortina-Access Presidio board
Alex Nemirovsky7d706a82020-01-30 12:34:59 -08006 */
7
8#ifndef __PRESIDIO_ASIC_H
9#define __PRESIDIO_ASIC_H
10
Alex Nemirovsky7d706a82020-01-30 12:34:59 -080011#define CONFIG_SYS_BOOTM_LEN 0x00c00000
12
13/* Generic Timer Definitions */
Peng Fanc5b9bf52022-04-13 17:47:21 +080014#define CONFIG_SYS_TIMER_RATE 25000000
Alex Nemirovsky7d706a82020-01-30 12:34:59 -080015#define CONFIG_SYS_TIMER_COUNTER 0xf4321008
16
17/* note: arch/arm/cpu/armv8/start.S which references GICD_BASE/GICC_BASE
18 * does not yet support DT. Thus define it here.
19 */
Alex Nemirovsky7d706a82020-01-30 12:34:59 -080020#define GICD_BASE 0xf7011000
21#define GICC_BASE 0xf7012000
22
Alex Nemirovsky7d706a82020-01-30 12:34:59 -080023#define CONFIG_SYS_TIMER_BASE 0xf4321000
24
25/* Use external clock source */
26#define PRESIDIO_APB_CLK 125000000
27#define CORTINA_PER_IO_FREQ PRESIDIO_APB_CLK
28
29/* Cortina Serial Configuration */
30#define CORTINA_UART_CLOCK (PRESIDIO_APB_CLK)
31#define CORTINA_SERIAL_PORTS {(void *)CONFIG_SYS_SERIAL0, \
32 (void *)CONFIG_SYS_SERIAL1}
33
Alex Nemirovsky7d706a82020-01-30 12:34:59 -080034#define CONFIG_SYS_SERIAL0 PER_UART0_CFG
35#define CONFIG_SYS_SERIAL1 PER_UART1_CFG
36
Alex Nemirovsky7d706a82020-01-30 12:34:59 -080037/* SDRAM Bank #1 */
38#define DDR_BASE 0x00000000
39#define PHYS_SDRAM_1 DDR_BASE
40#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2GB */
41#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
42
43/* Console I/O Buffer Size */
Alex Nemirovsky7d706a82020-01-30 12:34:59 -080044
Alex Nemirovskyc34a9272021-01-14 13:34:13 -080045#define KSEG1_ATU_XLAT(x) (x)
46
47/* HW REG ADDR */
48#define NI_READ_POLL_COUNT 1000
49#define CA_NI_MDIO_REG_BASE 0xF4338
50#define NI_HV_GLB_MAC_ADDR_CFG0_OFFSET 0x010
51#define NI_HV_GLB_MAC_ADDR_CFG1_OFFSET 0x014
52#define NI_HV_PT_BASE 0x400
53#define NI_HV_XRAM_BASE 0x820
54#define GLOBAL_BLOCK_RESET_OFFSET 0x04
55#define GLOBAL_GLOBAL_CONFIG_OFFSET 0x20
56#define GLOBAL_IO_DRIVE_CONTROL_OFFSET 0x4c
57
Alex Nemirovsky7d706a82020-01-30 12:34:59 -080058/* max command args */
Alex Nemirovsky7d706a82020-01-30 12:34:59 -080059#define CONFIG_EXTRA_ENV_SETTINGS "silent=y\0"
60
Kate Liu34a5add2020-12-11 13:46:13 -080061/* nand driver parameters */
62#ifdef CONFIG_TARGET_PRESIDIO_ASIC
Kate Liu34a5add2020-12-11 13:46:13 -080063 #define CONFIG_SYS_MAX_NAND_DEVICE 1
Kate Liu34a5add2020-12-11 13:46:13 -080064 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_FLASH_BASE
65 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
66#endif
67
Alex Nemirovsky7d706a82020-01-30 12:34:59 -080068#endif /* __PRESIDIO_ASIC_H */